JP2003345407A - Data equivalence method among duplexed plcs - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem that when an unoccupied time of a CPU is utilized for data memory equivalence of duplexed PLCs, the CPU's load increases and its processing speed is adversely affected. <P>SOLUTION: A data memory 11B of a CPU of a PLC1 on a master side is composed by a dual port memory. A current data memory 13B of a duplexed interface 13 reads data from one of the ports of the dual port memory on a steady basis. A previous value data memory 13C copies data of a current data memory at the time of completion of data reading. Equivalence processing parts 13A and 14A transfer data of the previous value data memory to a data memory 12B of a PLC2 on a slave side in the event of occurrence of abnormality in the PLC on the master side and obtain data equivalence. <P>COPYRIGHT: (C)2004,JPO

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a data equalization method between duplicated PLCs in a computer system in which PLCs (Programmable Logic Controllers) are duplicated.

[0002]

2. Description of the Related Art In general, computer systems requiring high reliability, such as supervisory control systems, are often duplicated, and when one system fails in system operation, it is switched to the other system to enable continuous system operation. To

FIG. 2 shows a main configuration of a supervisory control system in which PLCs are duplicated. The PLC1 and the PLC2 are equipped with a power supply board (POW), a processing board (CPU), a duplex interface, a network interface, and a device interface, respectively. PLC1 having such a hardware configuration,
2 enables communication with the host computer 3 via the network, transmits monitoring information collected from the controller unit 4 for the group of field devices to the host computer 3, and transmits control information from the host computer 3 to the controller unit 4. Equipped with a software configuration that has the function of transmitting data to

Here, the PLC 1 is, for example, a master side,
PLC2 is the slave side, and normally the master PLC1
Outputs the result of the input processing and the arithmetic processing, and outputs
C2 performs the same input processing and arithmetic processing in parallel with the master PLC1 and stores the same processing data, but locks the output. Then, when an abnormality occurs in the master PLC1, switching is performed to set the slave PLC2 to the master side, and the system operation by the PLC2 is continued.

[0005]

FIG. 3 shows an example of a memory configuration of a PLC. Basic data and DF are stored in a data memory.
Memory areas for C data and device data are provided. The program memory is provided with memory areas for a ladder program, a common subroutine program, a DFC / device program, and an extended operation program.

A dual PLC having such a memory configuration
At the slave PLC for the data of the master side PLC.
The data equalization method for keeping the LC equivalent is as follows.

(1) When starting up the initial equivalent system, all data memory areas of the memory areas of both PLCs are equalized.

(2) All data memory areas are equalized in several times by always using the idle time of the equivalent CPU.

(3) Equivalence at the time of program change When the program on the master side is changed, the program memory on the slave side is made equivalent.

[0010] Of the data equivalents described above, the constant equalization increases the load on the CPU, and in a system with a large data memory capacity, there is a problem that the processing speed of the CPU is affected.

An object of the present invention is to provide a data equalization method between duplex PLCs which solves the above problems.

[0012]

According to the present invention, in order to solve the above-mentioned problems, the data memory of the CPU is a dual-port memory, and the duplex interface of the master PLC is provided with a current data memory and a previous value data memory.
The data is always read from one port of the dual port memory to the current data memory, and when the reading is completed, the data is copied from the current data memory to the previous value data memory. Is transferred to the slave PLC, and is characterized by the following method.

The system has a master PLC and a slave P
An LC is provided, and a duplex interface is provided in both PLCs, in which a data interface and a program memory data provided on a processing board of the master PLC are provided in both PLCs. The data memory of the arithmetic processing board of the master-side PLC comprises a dual-port memory, and the dual interface of the master-side PLC includes a current data memory for constantly reading data from one port of the dual-port memory. A previous value data memory for copying the data when the data reading of the current data memory is completed, and transferring the data of the previous value data memory to the slave PLC when an abnormality occurs in the master PLC. Data equivalency processing And performing.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a block diagram showing a main part of a duplexed PLC showing an embodiment of the present invention. PLC1 and 2 CP
U11 and U12 have program memories 11A,
12A and data memories 11B and 12B are mounted to store programs and data necessary for monitoring control processing and perform data processing.

Dual interface 1 for PLCs 1 and 2
Equivalent processing units 13A and 14A are mounted on 3 and 14, respectively, and perform data equalization processing between the PLCs 1 and 2.

Here, in the present embodiment, the data memory 1
1B is a dual port memory, and the duplicated interface 13 includes a current data memory 13B and a previous value data memory 13C. Redundant interface 1
3 is a process for sequentially reading one memory data of the data memory 11B to be a dual port memory into the current data memory 13B, and copying the data into the previous value data memory 13C at the end of the reading of the current data memory 13B. Do.

In the above configuration, data equalization at the time of program change is performed in the same manner as in the prior art, by the equalization processing units 13A and 13A.
A performs data read / write processing between the program memories 11A and 12A.

[0018] The initial equivalent is the data memory 1
This is performed in data read / write processing between 1B and 12B. This initial equivalence processing is performed directly from the memory 11B through the equivalence processing units 13A and 14A.
2B or data via the data memories 13B and 13C.

Next, the constant equivalent is the conventional method, that is, C
The data is not read / written in a plurality of times using the idle time of the PU, and the data of one port of the data memory 11B which becomes a dual port memory is always read to the current data memory 13B regardless of the idle time of the CPU. / Write, and when this read / write operation is completed once, the data in the current data memory 13B is copied to the previous value data memory 13C.
The data copy processing by the current data memory 13B and the previous value data memory 13C is performed by the data memory 11B.
When an abnormal switching condition occurs while data is being read into the current data memory 13B, data loss or data buckling is prevented.

When the CPU 11 detects the occurrence of an abnormality in the master-side PLC 1, the CPU 11 uses this as an abnormality switching condition.
The PU 11 notifies the duplex interface 13, the equivalent processing unit 13A reads the data written in the data memory 13C, the equivalent processing unit 14A transfers the data to the data memory 12B, and the slave PLC 2 CPU 12 Continue system operation.

Therefore, according to the present embodiment, data is always read from the data memory 11B, which is a dual port memory, so that the data is always equivalent, but this does not impose a load on the CPU. Further, since the data equalization from the master PLC to the slave PLC is performed only when the abnormal switching condition is satisfied, wasteful processing is not required as compared with the conventional method in which the PLCs are always equalized, and the data equalization processing is simplified. Become.

[0022]

As described above, according to the present invention, the CPU
The dual memory of the master PLC is provided with a current data memory and a previous value data memory. Data is always read from one port of the dual port memory to the current data memory. Copy from the memory to the previous value data memory
The data equivalent processing method of transferring the data of the previous value data memory to the slave PLC when an abnormality occurs in the LC. This has an effect on the processing speed of the CPU even in a system with a large data memory capacity without increasing the load on the CPU. Has no effect.

[Brief description of the drawings]

FIG. 1 is a main part configuration diagram of a duplexed PLC showing an embodiment of the present invention.

FIG. 2 shows an example of a duplicated PLC system.

FIG. 3 is an example of a memory configuration of a PLC.

[Explanation of symbols]

1, 2, ... PLC 11, 12 ... CPU 13, 14 ... Duplex interface 11A, 12A: Program memory 11B, 12B ... data memory 13A, 14A: Equivalent processing unit 13B: Current data memory 13C: Previous value data memory

Claims (1)

[Claims] 1. A system in which a master-side PLC and a slave-side PLC are provided, and data in a data memory and data in a program memory provided on an arithmetic processing board of the master-side PLC are duplicated to be equivalent to the data memory and the program memory of the slave-side PLC, respectively. An interface is a data equalization method between PLCs provided in both PLCs, wherein a data memory of an arithmetic processing board of the master PLC is constituted by a dual port memory, and a duplicated interface of the master PLC is a dual port memory of the dual PLC memory. A current data memory for constantly reading data from one port; and a previous value data memory for copying the data upon completion of data reading of the current data memory. Data in data memory A data equalization method for transferring data to the slave-side PLC.