JPH0676599A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To shorten a burn-in test time by shortening the time for selecting all word lines. CONSTITUTION:A row selecting circuit 2 is operated by ordinary operation selecting one line among plural word lines WL1-WL4 according to an address signal AD when test row selecting signals PHI1, PHI2 are in an inactive state and separated from all word lines when test row selecting signals PHI1, PHI2 are in an active state. A selecting circuit 3 for a test row simultaneously selecting at least two lines among plural word lines WL1-WL4 according to the test row selecting signals PHI1, PHI2 while being separated from all word lines in the inactive state is provided.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device,
In particular, the present invention relates to a semiconductor memory device having a structure in which a word line is set to a selection level during a burn-in test to write and read data.

[0002]

2. Description of the Related Art Conventionally, in a burn-in test of a semiconductor memory device, a high bias of a power supply voltage is applied in a high temperature atmosphere to perform a read operation or a write operation to stress each circuit element or wiring.

FIG. 3 is a circuit diagram showing an example of a conventional semiconductor memory device of this type.

This semiconductor memory device has a plurality of word lines W.
L1 to WL4 and a plurality of digit lines DL11, DL12, D that are insulated from and cross the word lines WL1 to WL4.
L21, DL22, word lines WL1 to WL4 and digit lines DL11, DL12, DL21, DL22
A plurality of memory cells MC11 to MC14 which are provided at predetermined crossing points of the corresponding word lines and write and store the data transmitted to the corresponding digit lines when the corresponding word lines are at the selected level and read the stored data to the corresponding digit lines. , MC2
1 to MC24, the sense amplifiers SA1 and SA2 for amplifying the difference potentials between the digit lines DL11 and DL12, DL21 and DL22, and the address signal AD when the word line drive signal RA is activated. The row selection circuit 2a has a configuration in which one of the plurality of word lines WL1 to WL4 is set to a selection level.

Next, the operation of the semiconductor memory device in the burn-in test will be described.

Also in the burn-in test, the word lines selected by the row selection circuit 2a are one by one as in the normal operation. For example, when the word line WL1 is selected and becomes the selected level, the memory cells MC11 and MC21 are selected and the transistor Qs thereof is turned on, and the data of the digit lines DL11 and DL21 are stored in the capacitive element Cs and are stored. Data is digit line DL
11, transmitted to the DL 21.

This operation is sequentially performed on all word lines under high temperature and high bias power supply voltage, and stress is applied to all memory cells and wirings.

[0008]

In the conventional semiconductor memory device, the word lines are sequentially selected one by one even in the burn-in test, and the memory cells connected to all the word lines are stressed. There is a problem that the burn-in test takes a long time.

An object of the present invention is to provide a semiconductor memory device capable of shortening the burn-in test time.

[0010]

A semiconductor memory device according to the present invention is provided at a plurality of word lines, a plurality of digit lines which insulate the word lines and intersect, and an intersection of the word lines and the digit lines. A memory cell array having a plurality of memory cells for writing and storing the data transmitted to the corresponding digit line when the selected word line is at the selected level and reading the stored data to the corresponding digit line; When the activated test row selection signal is inactive, one of the plurality of word lines is set to the selection level in accordance with the address signal, and when activated, the word lines are insulated from each other. The row selection circuit to be turned on and at least one of the plurality of word lines according to the test row selection signal when the test row selection signal is in the activated state. And simultaneously selected level 2, and when the inactive mode and a test row selection circuit for an insulating state between said plurality of word lines.

[0011]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

This embodiment is different from the conventional semiconductor memory device shown in FIG. 3 in that the row selection circuit 2 is a test row selection signal Φ which is activated in the burn-in test mode.
When 1 and Φ2 are inactive, when the word line drive signal RA is active, one of the plurality of word lines WL1 to WL4 is set to the selection level according to the address signal, and the test row selection signals Φ1 and Φ2 are activated. In the activated state, a circuit for insulating between a plurality of word lines is provided, and the transistor Q1 to Q12 are provided, and when the test row selection signals Φ1 and Φ2 are activated, the word line drive signal RA is activated. In the state, at least two of the plurality of word lines WL1 to WL4 are simultaneously set to the selection level in accordance with the test row selection signals Φ1 and Φ2, and when the test row selection signals Φ1 and Φ2 are inactive, the plurality of word lines WL1 to WL1 are selected. A test row selection circuit 3 for insulating between WL4 and a test row selection signal Φ
1, and a NOR gate G1 for controlling the operation of the row selection circuit 2 depending on whether Φ2 is in the activated state or the inactivated state.

Next, the operation of this embodiment will be described.

The test row selection signals Φ1 and Φ2 have complementary level relationships in the activated state, and have a low level in the inactivated state.

When the test row selection signals Φ1 and Φ2 are inactive, the output of the NOR gate G1 becomes high level, and the row selection circuit 2 receives a plurality of word lines W according to the address signal AD.
One of L1 to WL4 is set to the selection level in synchronization with the word line drive signal RA. At this time, the transistors Q2, Q3, Q5, Q6, Q8, Q of the test row selection circuit 3
9, Q11, Q12 are off, so that the test row selection circuit 3 is separated from the word lines WL1 to WL4. That is, the word line is selected by the row selection circuit 2.

When the test row selection signals Φ1 and Φ2 are activated, one of them (eg, Φ1) becomes high level and the other becomes low level, so that the output of the NOR gate G1 becomes low level and the row selection circuit 2 becomes word-wise. The lines WL1 to W4 are separated.

On the other hand, the transistors Q2, Q6, Q9, Q11 are turned on by the test row selection signal Φ1, and Q is turned by Φ2.
Since 3, Q5, Q8, and Q12 are turned off, the word line W
At least two of L1 and WL4 are word line drive signals RA
To the selection level in synchronization with the word lines WL2, WL3
Is the non-selection level. That is, at least two word lines are simultaneously selected by the test row selection circuit 3.

As described above, during the burn-in test, a plurality of word lines are simultaneously set to the selection level, so that the time for setting all the word lines to the selection level, that is, the burn-in test time can be shortened.

FIG. 2 is a circuit diagram showing a second embodiment of the present invention.

In the first embodiment, word lines WL1 and WL4
Is at the selection level, the word lines WL2 and WL3 are at the non-selection level, but in the second embodiment, the test lines selection signal Φ1 causes the word lines WL1 to WL4 to simultaneously become the selection level. At this time, the test row selection signal Φ2
As a result, the other word lines not shown in FIG. 2 become the non-selected level.

That is, this embodiment and the first embodiment are
At the same time, the combinations of word lines that become the selection level are different. Other than this, the basic operation and effects are the same as those of the first embodiment.

[0023]

As described above, according to the present invention, since a plurality of word lines are selected at the same time during the burn-in test, it is possible to shorten the time for selecting all the word lines, thus shortening the burn-in test time. There is an effect that can be.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a second embodiment of the present invention.

FIG. 3 is a circuit diagram showing an example of a conventional semiconductor memory device.

[Explanation of symbols]

1 memory cell array 2, 2a row selection circuit 3, 3a test row selection circuit DL11, DL12, DL21, DL22 digit line G1 NOR gate MC11 to MC14, MC21, DL22 digit line Q1 to Q12 transistor SA1, SA2 sense amplifier WL1 to WL4 word line

Claims (1)

[Claims] 1. A plurality of word lines, a plurality of digit lines that intersect the word lines in an insulated manner, and digit lines that are provided at the intersections of the word lines and the digit lines and the corresponding word lines are at a selected level. The memory cell array having a plurality of memory cells for writing and storing the data transmitted to and reading the stored data to the corresponding digit line, and the test row selection signal which is activated in a predetermined test mode are inactive A row selection circuit that sets one of the plurality of word lines to a selection level according to an address signal when in the state, and an isolation state between the plurality of word lines when in the activated state; and the test row selection When the signal is in the activated state, at least two of the plurality of word lines are simultaneously set to the selection level in accordance with the test row selection signal, and the inactivated state. In this case, the semiconductor memory device further comprises a test row selection circuit for insulating the plurality of word lines from each other.