JPH0675767A - Processor - Google Patents

Abstract

PURPOSE:To improve the processing speed of a processor by deciding the address of the memory which designates an instruction that is carried out by the signal outputted based on all comparison results. CONSTITUTION:When it is checked whether the value X is included in a range shown by Xmin<X<Xmax or not, a subtraction Xmax-X is carried out by a comparison instruction (subtraction instruction). Thus a comparison result Z is acquired and the most significant bit MSB (Z) of the result Z is inputted to a flag generating circuit 5. The circuit 5 calculates a NOR between the most significant bit MSB (Y) of the arithmetic result Y or X-Xmin and the MSB (Z). Then a flag signal FLG is outputted as an arithmetic result. A conditional branch instruction decides whether the value of the signal FLG is equal to 1 or 0, and a memory address control circuit 3 performs the address control so as to decide the address of a memory 4 which designates the instruction to be carried out next.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a processor, and more particularly to a processor having an arithmetic operation unit and performing operations such as addition and subtraction operations and non-linear operations by instructions written in a memory.

[0002]

2. Description of the Related Art FIG. 4 shows an arithmetic operation unit of a conventional horizontal microprogram type processor. In FIG. 4, 51 is an adder / subtractor, 52 is a type of operation, Is a calculation control circuit for controlling the adder / subtractor 51 so as to perform the calculation of, and 53 is a memory address control circuit for controlling the address of the memory 54 in which the program is written. The adder / subtractor 51 calculates the input data A and data B under the control of the calculation control circuit 52, and outputs a calculation result C.

Generally, in a horizontal microprogram type processor having such an arithmetic operation unit, one process is executed only when a plurality of conditions are all satisfied, while at least one of the plurality of conditions is not satisfied. When another process is executed, a conditional branch instruction related to the operation result C and an unconditional branch instruction not related to the operation result C are prepared. Then, as an instruction to determine whether or not the first condition is satisfied, first, the magnitude of the value of the data A and the value of the data B are compared, and then it is determined that the first condition is satisfied based on the comparison result. In this case, a conditional branch instruction that branches to an instruction that determines whether the next condition is satisfied is executed. Hereinafter, the same instruction is executed for all conditions to determine whether or not the conditions are satisfied.

FIG. 5 shows the flow of instruction execution for checking whether or not the value X is within the range expressed by Xmin <X <Xmax. In FIG. 5, the first condition X
As an instruction for determining the success or failure of> Xmin, first, in the comparison instruction (that is, the subtraction instruction) of step S51, X and Xmi
The magnitude is compared with n, that is, X-Xmin is subtracted to obtain the operation result Y, and then step S52.
, The most significant bit MSB (Y) of the operation result Y as the comparison result in step S51 is 1
Or 0, MSB (Y) = 1
If it is, it is determined that the first condition: X> Xmin does not hold, and the process proceeds to the instruction of step S53, while MSB
If (Y) = 0, it is determined that the first condition: X> Xmin is satisfied, and the process proceeds to the instruction of step S54. In this conditional branch instruction, the memory address control circuit 53 performs address control so that the address of the memory 54 designating the next instruction to be executed is determined. Step S5
In the unconditional branch instruction of 3, the instruction of step S58 is designated as the instruction to be executed next, so that the step S58 is executed.
Move to 58. As a command for determining the success or failure of X <Xmax which is the second condition, the comparison command (that is, the subtraction command) in step S54 compares the magnitudes of X and Xmax, that is,
Xmax-X is subtracted to obtain the operation result Z. Next, in the conditional branch instruction of step S55, the most significant bit MSB (Z) of the operation result Z as the comparison result in step S54 is 1. Or 0, and when MSB (Z) = 1, the second condition: X <
When it is determined that Xmax does not hold, the process moves to the instruction of step S56, while when MSB (Z) = 0, it is determined that the second condition: X <Xmax holds and step S5.
Move on to 7. In this conditional branch instruction, the memory address control circuit 53 performs address control so that the address of the memory 54 designating the next instruction to be executed is determined. In the unconditional branch instruction of step S56, the instruction of step S58 is designated as the instruction to be executed next, and the process proceeds to step S58. And X-Xmi
The most significant bit MSB (Y) of the operation result Y of n is 0 and the most significant bit MSB of the operation result Z of Xmax-X
When (Z) is 0, that is, the first condition: X> Xmi
n and the second condition: when X <Xmax is satisfied, the value X is Xmin <X <Xma in step S57.
The processing when it is within the range represented by x is executed. On the other hand, the most significant bit MSB of the operation result Y of X-Xmin
(Y) is 1 or the most significant bit MSB (Z) of the operation result Z of Xmax-X is 1, that is, the first
If at least one of the condition: X> Xmin and the second condition: X <Xmax is not satisfied, the process in the case where the value X is not within the range represented by Xmin <X <Xmax in step S58 is performed. Run.

At this time, step S51 and step S
The comparison of the magnitudes of the two data values in 54 can be realized by subtraction (value of data A-value of data B) in the adder / subtractor 51, and in the conditional branch instructions of step S52 and step S55, respectively, step S51, Most significant bit MSB of operation result C in step S54
Memory 5 that specifies the next instruction to be executed based on the value of
The address 4 is determined by the memory address control circuit 53.

In such a conventional processor, when selecting a case where the value X is within the range represented by Xmin <X <Xmax, one comparison instruction and one conditional branch instruction and one conditional branch instruction are selected for each condition. Since a total of three instructions including one unconditional branch instruction are executed, a total of 3 × 2 = 6 instructions are executed.

[0007]

By the way, in application examples of image processing, since processing is often performed only within a specific area, it is determined whether or not all of the above-described plurality of conditions are satisfied. Are often used for
Further, since the amount of data is enormous, high processing speed is required.

However, in the conventional processor as described above, when selecting a case where all of a plurality of conditions are satisfied, a conditional branch instruction is executed for each condition, so the number of instructions is three times the number of conditions. Therefore, there is a problem that the processing speed may decrease.

The present invention has been made in view of the above,
An object of the present invention is to provide a processor capable of improving the processing speed when selecting a case where a plurality of conditions are all satisfied.

[0010]

To achieve the above object, the present invention compares the magnitudes of two data values by an adder / subtractor, outputs the comparison result, and outputs all the comparison results. Based on the signal, the address of the memory designating the instruction to be executed is determined based on the signal to select the case where all the plurality of magnitude relations are satisfied.

Specifically, the solving means implemented by the present invention comprises an adder / subtractor which compares the magnitudes of two data values and outputs the comparison result, and among the instructions written in the memory, Flag generation means for outputting a flag signal based on all of the plurality of comparison results output by the adder / subtractor, and a flag signal output by the flag generation means, targeting a processor that executes an instruction specified by a memory address And a memory address determining means for determining the address of the memory based on the above.

[0012]

With the above configuration, when the plurality of magnitude relations between the two data values are all satisfied, each comparison result output from the adder / subtractor is satisfied with each of the plurality of magnitude relations. Therefore, the flag signal output by the flag generating means indicates that all the conditions of the plurality of magnitude relations are satisfied. Therefore, the memory address determining means can determine the address of the memory that specifies the instruction to be executed when all the plurality of magnitude relations are satisfied, based on the flag signal.

At this time, since the comparison instruction is executed by the adder / subtractor and the conditional branch instruction is executed by the flag generating means and the memory address determining means, selection in the case where all of the plurality of magnitude relational conditions are satisfied. Can be performed only by executing the same number of comparison instructions and one conditional branch instruction as the number of the magnitude relation conditions.

[0014]

1 shows the configuration of an arithmetic operation unit of a signal processor as a processor according to an embodiment of the present invention. In FIG. 1, 1 is an adder / subtractor, and 2 is a type of operation. And adder / subtractor 1 to perform the operation of the type
Is an arithmetic control circuit for controlling the memory address, and 3 is a memory address control circuit as a memory address determining means for controlling the address of the memory 4 in which the program is written.
Reference numeral 5 is a flag generation circuit as a flag generation means, and 6
Is a flag control circuit for controlling the flag generation circuit 5,
The flag generation circuit 5 outputs a flag signal FLG. The adder / subtractor 1 calculates the input data A and data B under the control of the calculation control circuit 2 and outputs the calculation result C.

FIG. 2 shows an example of the flag generation circuit 5. In FIG. 2, 5a is a NOR gate.
b is a flip-flop circuit. Flag control circuit 6
The operation control circuit 2 controls the clock signal CLK to the flip-flop circuit 5b when the instruction is a comparison instruction.
When the instruction refers to the flag signal FLG, for example, a conditional branch instruction, the clear signal CLR is output to the flip-flop circuit 5b. As a result, the flag signal FL
The value of G is the most significant bit MSB of the operation result of the currently executed comparison instruction or subtraction instruction and the most significant bit MSB of the operation result of the comparison instruction or subtraction instruction executed before that.
It is given by the NOR operation with. The memory address control circuit 3 determines the address of the memory 4 designating the instruction to be executed according to the value of the flag signal FLG of the flag generation circuit 5.

FIG. 3 shows the flow of instruction execution in the case of checking whether the value X is within the range represented by Xmin <X <Xmax, and in FIG. 3, the first condition X
> Xmin and the second condition X <Xmax as a command to determine the success or failure, first, in the comparison command (that is, the subtraction command) in step S1, the size of X and Xmin is compared, that is, X-Xmin Subtraction is performed to obtain the operation result Y, the most significant bit MSB (Y) of the operation result Y as the comparison result is input to the flag generation circuit 5, and then the comparison instruction (that is, the subtraction instruction) in step S2. Then X
And Xmax are compared, that is, Xmax-X is subtracted to obtain an operation result Z, and the most significant bit MSB (Z) of the operation result Z as a comparison result is input to the flag generation circuit 5. Then, in the flag generation circuit 5, X-
The most significant bit MSB (Y) and X of the operation result Y of Xmin
A NOR operation is performed with the most significant bit MSB (Z) of the operation result Z of max-X, and the flag signal FLG as the operation result is output. Next, in the conditional branch instruction of step S3, it is determined whether the value of the flag signal FLG is 1 or 0 by referring to the flag signal FLG output from the flag generation circuit 5, and the flag signal FLG When the value is 1, it is determined that the first condition: X> Xmin and the second condition: X <Xmax are both satisfied, and the process proceeds to the instruction of step S4, while the value of the flag signal FLG is 0. The first condition: X> Xmin and the second condition:
When it is determined that at least one condition of X <Xmax is not satisfied, the process proceeds to the instruction of step S5. In this conditional branch instruction, the memory address control circuit 3 performs address control so that the address of the memory 4 designating the next instruction to be executed is determined. Then, the flag signal FLG
Is 1, that is, the first condition: X> Xmin
And the second condition: when X <Xmax holds together, the process when the value X is in the range represented by Xmin <X <Xmax is executed in step S4. On the other hand, when the value of the flag signal FLG is 0, that is, when at least one of the first condition: X> Xmin and the second condition: X <Xmax is not satisfied, the value X is determined in step S5. The processing is executed when it is not within the range represented by Xmin <X <Xmax.

At this time, step S1 and step S2
The comparison of the magnitudes of the two data values can be realized by subtraction (value of data A-value of data B) in the adder / subtractor 1, and the NOR operation in step S2 is the NOR gate of the flag generation circuit 5. 5a,
In the conditional branch instruction of step S3, the address of the memory 4 designating the instruction to be executed next is determined by the memory address control circuit 3 based on the flag signal FLG output from the NOR gate 5a.

When selecting the case where the value X is within the range represented by Xmin <X <Xmax, the flag generating circuit 5 and the flag control circuit 6 are excluded from the configuration of the processor according to the above embodiment. In the conventional processor, since three instructions are executed for one condition, it is necessary to execute a total of 3 × 2 = 6 instructions. In the processor according to the above embodiment, the first condition is used. : X>
It is only necessary to execute a total of three instructions, that is, two comparison instructions and one conditional branch instruction corresponding to Xmin and the second condition: X <Xmax. Further, when the range is a two-dimensional area, 3 × 4 = 12 instructions need to be executed in the conventional processor, but 4 + 1 = 5 instructions in the processor according to the embodiment. Only the instructions are executed. In the processor according to the above-described embodiment, the greater the number of conditions, the greater the effect of shortening the processing time.

[0019]

As described above, in the processor according to the present invention, each comparison result output from the adder / subtractor is the above when the conditions of plural magnitude relations between two data values are all satisfied. Since it is shown that each of the plurality of magnitude relation conditions is satisfied, the flag signal output based on all of the plurality of comparison results indicates that the plurality of magnitude relation conditions are all satisfied.
Based on the flag signal, it is possible to determine the address of the memory designating the instruction to be executed when the plurality of magnitude relations are all satisfied. At this time, since the execution of the comparison instruction is realized by the adder / subtractor and the execution of the conditional branch instruction is realized by the flag generating means and the memory address determining means, the selection in the case where all the conditions of the plurality of magnitude relations are satisfied is described above. This can be performed only by executing the same number of comparison instructions and one conditional branch instruction as the number of magnitude-related conditions.

Therefore, according to the present invention, it is possible to significantly improve the processing speed when selecting a case where all of a plurality of conditions are satisfied, without significantly increasing the hardware configuration scale. Since the processing time can be shortened to half or less as compared with the conventional processor equipped with, the practical effect is great.

[Brief description of drawings]

FIG. 1 is a block diagram illustrating a processor according to an exemplary embodiment of the present invention.

FIG. 2 is a block diagram showing a flag generation circuit of the processor according to the embodiment.

FIG. 3 shows that the value X is X in the processor according to the above embodiment.
It is a flowchart figure which shows the flow of execution of the instruction at the time of checking whether it exists in the range represented by min <X <Xmax.

FIG. 4 is a block diagram showing a processor according to a conventional example.

FIG. 5 shows that the value X is X in the processor according to the conventional example.
It is a flowchart figure which shows the flow of execution of the instruction at the time of checking whether it exists in the range represented by min <X <Xmax.

[Explanation of symbols]

 1 adder / subtractor 2 arithmetic control circuit 3 memory address control circuit 4 memory 5 flag generation circuit 6 flag control circuit

Claims (1)

[Claims] 1. An adder / subtractor that compares the magnitudes of two data values and outputs the comparison result, and executes an instruction specified by an address of the memory among instructions written in the memory. A flag generating means for outputting a flag signal based on all of the plurality of comparison results output by the adder / subtractor, and an address of the memory based on the flag signal output by the flag generating means. A processor comprising a memory address determining means.