JPH0675008A - Test jig for integrated circuit - Google Patents

Test jig for integrated circuit

Info

Publication number
JPH0675008A
JPH0675008A JP4229073A JP22907392A JPH0675008A JP H0675008 A JPH0675008 A JP H0675008A JP 4229073 A JP4229073 A JP 4229073A JP 22907392 A JP22907392 A JP 22907392A JP H0675008 A JPH0675008 A JP H0675008A
Authority
JP
Japan
Prior art keywords
integrated circuit
substrate
board
test
electrode pattern
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4229073A
Other languages
Japanese (ja)
Inventor
Hiroshi Inose
浩 猪瀬
Hisao Sekine
久夫 関根
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP4229073A priority Critical patent/JPH0675008A/en
Publication of JPH0675008A publication Critical patent/JPH0675008A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To provide a test jig for obtaining correct test results without employing an IC socket accompanying inter-pin parasitic capacitance or inductance of lead having adverse effect on the test results while facilitating maintenance and operation. CONSTITUTION:The test jig for integrated circuit comprises a second board 5 formed with an electrode pattern 6 matching with pin configulation of an integrated circuit to be tested on the surface and a POGO pin contact pattern 7 conducting through the board with the electrode pattern 6 on the rear surface thereof, and a first board 1 mounting external components or circuits for operating the integrated circuit to be tested and having POGO pins 2 coming into contact with the POGO pin contact pattern 7 on the second board 5. The POGO pins 2 on the first board 1 are brought detachably into contact with the POGO pin contact pattern 7 on the second board 5.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は高周波リニア信号を扱う
集積回路を試験するための試験用治具に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a test jig for testing an integrated circuit handling a high frequency linear signal.

【0002】[0002]

【従来の技術】リニア信号を扱う集積回路を試験する場
合、この集積回路を機能させる外付け部品などを搭載し
た基板と、この基板に被試験集積回路を装着する手段と
を備えた試験用治具を用いるのが一般的である。集積回
路の外付け部品には種々のものがあり、例えば、集積回
路の発振を防止するコンデンサ、フィルタの時定数を決
めるコンデンサおよび抵抗、集積回路内部の定電圧回路
用の抵抗、発振器の発振周波数を決めるコンデンサなど
である。また、試験用治具には必要に応じて電源回路
や、増幅器や、バッファ回路、あるいはリレーなどが設
けられている。
2. Description of the Related Art When testing an integrated circuit that handles a linear signal, a test jig including a board on which external components for operating the integrated circuit are mounted and a means for mounting the integrated circuit under test on the board. It is common to use ingredients. There are various external parts for integrated circuits. For example, capacitors that prevent oscillation of integrated circuits, capacitors and resistors that determine the time constant of filters, resistors for constant voltage circuits inside integrated circuits, oscillator oscillation frequencies. It is a capacitor that decides. In addition, the test jig is provided with a power supply circuit, an amplifier, a buffer circuit, a relay, and the like as needed.

【0003】しかして、図3の斜視図に示すように、上
記の外付け部品など3を搭載した基板11には、被試験
集積回路の脱着が容易に行えるようにICソケット13
を設けることが広く行われている。
As shown in the perspective view of FIG. 3, however, the IC socket 13 is mounted on the substrate 11 on which the above-mentioned external parts 3 are mounted so that the integrated circuit under test can be easily attached and detached.
Is widely used.

【0004】[0004]

【発明が解決しようとする課題】上記のように被試験集
積回路の脱着容易のためにICソケットを用いた場合、
ICソケットにはピン間に通常数pFの寄生分布容量が
存在する。また、リードやパターン長によるインダクタ
ンス成分も寄生する。そのためこれらの容量、インダク
タンスにより、ICソケットを用いた従来の試験用治具
による高周波用集積回路の試験では電気的特性に大きな
影響を受け、正しい試験結果を得ることが困難であると
いう問題がある。
When the IC socket is used to facilitate the attachment and detachment of the integrated circuit under test as described above,
In an IC socket, a parasitic distributed capacitance of several pF usually exists between pins. In addition, the inductance component due to the lead and the pattern length is also parasitic. Therefore, due to the capacitance and the inductance, in the test of the high-frequency integrated circuit by the conventional test jig using the IC socket, the electrical characteristics are greatly affected, and it is difficult to obtain a correct test result. .

【0005】そのため、図4の斜視図に示すような試験
用治具が考えられる。図4において、抵抗、コンデンサ
や、バッファや、電源回路などの外付け部品、必要回路
など3が搭載された基板12上に被試験集積回路の端子
配置に合わせて電極パターン6を設け、被試験集積回路
の端子を電極パターン6に直接接触させることにより、
ICソケット寄生容量やリード長インダクタンスによる
悪影響を無くしている。
Therefore, a test jig as shown in the perspective view of FIG. 4 can be considered. In FIG. 4, an electrode pattern 6 is provided on a substrate 12 on which resistors, capacitors, buffers, external parts such as a power supply circuit, and necessary circuits 3 are mounted in accordance with the terminal arrangement of the integrated circuit under test, By directly contacting the terminals of the integrated circuit with the electrode pattern 6,
The adverse effects of IC socket parasitic capacitance and lead length inductance are eliminated.

【0006】しかしながら、図4に示す試験用治具で
は、基板12上の電極パターン6と被試験集積回路の端
子との接触回数が、例えば数万回程度と多くなると、電
極パターン6が摩耗、あるいは汚損し、ついには接触不
良を引き起し、正常な試験が行なえなくなる。しかして
この場合は新たな試験用治具と交換しなければならな
い。しかし、集積回路の外付け部品にはばらつきがあ
り、例えば抵抗では±1%、セラミックコンデンサでは
±20%が許容誤差として容認されている。したがっ
て、新たに試験用治具を作成し交換するには、治具作成
の工数は勿論のこと、外付け部品のばらつきを補正した
り、新規の治具と元の治具との間の相関を確認する工数
が必要となり、試験用治具の運用上多大な工数増となっ
て原価高を招く欠点がある。
However, in the test jig shown in FIG. 4, when the number of contact between the electrode pattern 6 on the substrate 12 and the terminal of the integrated circuit under test becomes large, for example, about tens of thousands of times, the electrode pattern 6 becomes worn. Alternatively, it may become soiled and eventually cause poor contact, making it impossible to carry out a normal test. However, in this case, the test jig must be replaced with a new one. However, there are variations in the external parts of the integrated circuit. For example, ± 1% for resistors and ± 20% for ceramic capacitors are accepted as allowable errors. Therefore, in order to create and replace a new test jig, not only the number of man-hours required to create the jig but also the variation in external parts can be corrected and the correlation between the new jig and the original jig can be corrected. The number of man-hours required for confirmation is required, and there is a drawback that the man-hours for the operation of the test jig increase enormously and the cost increases.

【0007】[0007]

【課題を解決するための手段】上記課題に対して本発明
では、被試験集積回路の端子を直接接触させる電極パタ
ーンを設けた第2基板を、外付け部品などの取り付けら
れている第1基板と脱着自在に組み合わせて、多数回の
試験による電極パターン摩耗などによる接触不良が発生
しても、外付け部品、回路の再調整不要の第2基板の交
換だけで試験機能を元に戻すようにしている。
In order to solve the above-mentioned problems, according to the present invention, the second substrate provided with the electrode pattern for directly contacting the terminals of the integrated circuit under test is replaced with the first substrate to which external parts are attached. Even if a contact failure occurs due to electrode pattern wear due to multiple tests, the test function can be restored by simply replacing the second board without the need for readjustment of external parts and circuits. ing.

【0008】[0008]

【実施例】つぎに本発明について図面を参照して説明す
る。図1(A)は本発明の一実施例の分解斜視図であ
る。図1(A)において、第1基板1には接触導電体と
してのポゴピン2および抵抗、コンデンサなどの外付け
部品の大部分、および、試験に伴ない必要な電源回路、
バッファなど3が取り付けられている。また、第2の基
板5の表面には、被試験集積回路の端子配置に合わせた
電極パターン6が形成されている。電極パターン6は基
板を貫通して、図1(B)の裏面図に示すような、ポゴ
ピン接触パターン7に導通し、ポゴピン接触パターン7
には、寄生容量やリード長インダクタンスの悪影響を避
けるために、被試験集積回路の端子の近傍に取り付ける
必要のある外付け部品、例えば、発振防止用コンデン
サ、発振周波数を決めるコンデンサ4などが直接取り付
けられている。それから、第2基板5の表面電極パター
ン6と導通している第2基板裏面のポゴピン接触パター
ン7を第1の基板1のポゴピン2に接触させ、ねじ穴8
を通した固定用ねじなどにより、第1の基板1に第2基
板5を脱着容易に固定する。
The present invention will be described below with reference to the drawings. FIG. 1A is an exploded perspective view of an embodiment of the present invention. In FIG. 1A, the first substrate 1 has a pogo pin 2 as a contact conductor and most of external parts such as a resistor and a capacitor, and a power supply circuit necessary for the test,
A buffer etc. 3 is attached. An electrode pattern 6 is formed on the surface of the second substrate 5 according to the terminal arrangement of the integrated circuit under test. The electrode pattern 6 penetrates through the substrate and is electrically connected to the pogo pin contact pattern 7 as shown in the back view of FIG.
In order to avoid the adverse effects of parasitic capacitance and lead length inductance, external components that need to be installed near the terminals of the integrated circuit under test, such as an oscillation prevention capacitor and a capacitor 4 that determines the oscillation frequency, are directly attached. Has been. Then, the pogo pin contact pattern 7 on the back surface of the second substrate, which is electrically connected to the front surface electrode pattern 6 of the second substrate 5, is brought into contact with the pogo pin 2 of the first substrate 1, and the screw hole 8 is formed.
The second substrate 5 is easily fixed to the first substrate 1 with a fixing screw or the like that has been passed through.

【0009】被試験集積回路の端子を第2基板の電極パ
ターン6と接触させ、被試験集積回路に対する必要な試
験を行うのであるが、多数回の接触の結果電極パターン
6が摩耗し接触不良となった場合は第2の基板を第1の
基板から取り外し、新しい第2の基板と交換する。この
交換においては、第1の基板1はそのままであるから外
付け部品もそのままであり、交換による調整は不要であ
る。また、新しい第2の基板も元々寄生分布容量、イン
ダクタンス共に小さい値なので、それらに対する変化が
あったとしても、試験機能に格別の影響を与えるほどの
ものではない。
The terminals of the integrated circuit to be tested are brought into contact with the electrode patterns 6 on the second substrate to carry out a necessary test on the integrated circuit to be tested. If it happens, the second substrate is removed from the first substrate and replaced with a new second substrate. In this replacement, since the first substrate 1 is left as it is, the external parts are left as it is, and adjustment by replacement is unnecessary. In addition, since the parasitic capacitance and inductance of the new second substrate are originally small, even if there are changes to them, the test function is not significantly affected.

【0010】なお、図2の斜視図に示すように、第2基
板5の電極パターン6の外側に被試験集積回路の外形に
合った位置決めガイド9を設ければ能率よく被試験集積
回路の位置合わせができ、一層スムースに試験を行うこ
とができる。
As shown in the perspective view of FIG. 2, it is possible to efficiently position the integrated circuit under test by providing a positioning guide 9 on the outside of the electrode pattern 6 on the second substrate 5 so as to match the outer shape of the integrated circuit under test. The test can be performed more smoothly, because it can be matched.

【0011】[0011]

【発明の効果】以上説明したように本発明の試験治具で
は、被試験集積回路の端子配置に合わせて第2基板に電
極パターンを設け、この電極パターンと直結して基板裏
面にポゴピン接触パターンを設け、外付け部品などが搭
載され、かつ、前記第2基板ポゴピン接触パターンに対
応して接触導電体としてのポゴピンが設けられている第
1基板のポゴピンを前記第2基板のポゴピン接触パター
ンに接触接続させているので、前記第2基板の電極パタ
ーンに被試験集積回路の端子を接触させて行う試験にお
いて、多数回の接触で接触不良が発生しても、試験機能
に悪影響を及ぼすことなしに、速やかに新しい第2基板
と交換できるので、接触不良の場合に外付け部品の取り
付けられた基板をそのまま交換するのに比べ、外付け部
品の再調整などが不要であり、治具保守運用工数の大幅
な節減ができる。
As described above, in the test jig of the present invention, the electrode pattern is provided on the second substrate according to the terminal arrangement of the integrated circuit under test, and the electrode pattern is directly connected to the pogo pin contact pattern on the back surface of the substrate. Is provided with external parts and pogo pins as a contact conductor corresponding to the second board pogo pin contact pattern are provided on the first board as the pogo pin contact pattern on the second board. Since the connection is made by contact, in the test conducted by bringing the terminal of the integrated circuit under test into contact with the electrode pattern of the second substrate, even if a contact failure occurs by a large number of contacts, the test function is not adversely affected. In addition, since it can be quickly replaced with a new second board, in the case of poor contact, readjustment of external parts can be performed compared to replacing the board with external parts attached as it is. A principal, it is significant savings of jig operation and maintenance man-hours.

【図面の簡単な説明】[Brief description of drawings]

【図1】分図(A)は本発明の一実施例の分解斜視図、
分図(B)は分図(A)の第2基板の裏面図である。
FIG. 1A is an exploded perspective view of an embodiment of the present invention,
Diagram (B) is a rear view of the second substrate of diagram (A).

【図2】位置決めガイドを有する本発明に係る第2基板
の斜視図である。
FIG. 2 is a perspective view of a second substrate according to the present invention having a positioning guide.

【図3】従来のICソケット付きの集積回路試験用治具
の斜視図である。
FIG. 3 is a perspective view of a conventional integrated circuit test jig with an IC socket.

【図4】被試験集積回路の端子を直接接触させる電極パ
ターンを有する基板からなる集積回路試験用治具の斜視
図である。
FIG. 4 is a perspective view of an integrated circuit test jig including a substrate having an electrode pattern for directly contacting the terminals of the integrated circuit under test.

【符号の説明】[Explanation of symbols]

1 第1基板 2 ポゴピン 3 外付け部品、回路など 4 発振防止用コンデンサ 5 第2基板 6 電極パターン 7 ポゴピン接触パターン 8 取り付けねじ穴 9 位置決めガイド 1 1st board 2 Pogo pin 3 External parts, circuit, etc. 4 Oscillation prevention capacitor 5 2nd board 6 Electrode pattern 7 Pogo pin contact pattern 8 Mounting screw hole 9 Positioning guide

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 被試験集積回路の端子配置に合わせて電
極パターンが形成された第2の基板と、前記被試験集積
回路を機能させる外付け部品および測定に判う付属回路
などが搭載され、かつ、前記第2基板の電極パターン配
置に合わせて設けられた接触導電体を有する第1の基板
と、前記第2基板の電極パターンと直接つながる接触パ
ターンと前記第1基板の接触導電体とを脱着自在に接触
させ接続する手段とを備え、前記第2基板の電極パター
ンに被試験集積回路の端子を直接接触させ試験を行なう
ことを特徴とする集積回路試験用治具。
1. A second substrate on which an electrode pattern is formed according to the terminal arrangement of the integrated circuit under test, an external component for operating the integrated circuit under test, an accessory circuit known to the measurement, etc. are mounted. And a first substrate having a contact conductor provided in accordance with the electrode pattern arrangement of the second substrate, a contact pattern directly connected to the electrode pattern of the second substrate, and a contact conductor of the first substrate. A jig for integrated circuit testing, which comprises a means for removably contacting and connecting, and performing a test by directly contacting a terminal of an integrated circuit under test with an electrode pattern of the second substrate.
JP4229073A 1992-08-28 1992-08-28 Test jig for integrated circuit Pending JPH0675008A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4229073A JPH0675008A (en) 1992-08-28 1992-08-28 Test jig for integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4229073A JPH0675008A (en) 1992-08-28 1992-08-28 Test jig for integrated circuit

Publications (1)

Publication Number Publication Date
JPH0675008A true JPH0675008A (en) 1994-03-18

Family

ID=16886322

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4229073A Pending JPH0675008A (en) 1992-08-28 1992-08-28 Test jig for integrated circuit

Country Status (1)

Country Link
JP (1) JPH0675008A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0897261A (en) * 1994-09-28 1996-04-12 Nec Corp Semiconductor chip bias testing socket
JP2007298423A (en) * 2006-04-29 2007-11-15 Fujitsu Ltd Module testing device, module testing method, and module testing program
US9733273B2 (en) 2015-01-09 2017-08-15 Renesas Semiconductor Package & Test Solutions Co., Ltd. Testing method for semiconductor manufacturing equipment

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0897261A (en) * 1994-09-28 1996-04-12 Nec Corp Semiconductor chip bias testing socket
JP2007298423A (en) * 2006-04-29 2007-11-15 Fujitsu Ltd Module testing device, module testing method, and module testing program
US9733273B2 (en) 2015-01-09 2017-08-15 Renesas Semiconductor Package & Test Solutions Co., Ltd. Testing method for semiconductor manufacturing equipment

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