JPH067343U - MSK differential detection circuit - Google Patents

Abstract

(57) [Abstract] [Purpose] An excellent M that can prevent the BER of demodulated data from decreasing even when the MSK signal is affected by noise or the like.
An object is to provide an SK differential detection circuit. [Configuration] MSK signal M converted to digital component signal
(T) is delayed by this digital signal component for a predetermined time based on the carrier component signal f _s , and the MSK delay signal M (t−
a shift register 11 for obtaining t _d ) and holding this digital signal component at a predetermined timing of the MSK delay signal,
Obtain a binary holding signal, hold the holding signal at the next predetermined timing to obtain the next holding signal, and sequentially hold the holding signal held at the previous predetermined timing, at the next predetermined timing. The shift register 13 for holding a plurality of holding signals by holding at 1, and the total number of one of the binary values of each holding signal are compared with the total number of the other, and one of the binary values having the larger total number is demodulated data D.
And a majority circuit 14 for outputting as (t).

Description

[Detailed description of the device]

[0001]

[Industrial applications]

 The present invention relates to an MSK delay detection circuit that receives an MSK (Minimum Shift Keing) signal and detects it.

[0002]

[Prior art]

The MSK signal is a kind of CPFSK (continuous phase frequency shift keying) that switches two frequencies in continuous phase by binary data of "0" or "1". The frequency arrangement of the MSK signal is shown in FIG. In FIG. 3, f _c is the carrier frequency, f _H is the frequency when the data is “0”, and f _L is the frequency when the data is “1”. Further, the bit rate of the data is f _B and its reciprocal is T. In this case, the distance Δf between f _c and f _H and f _L is expressed by the following equation.

Δf = 1 / 4T = f _B / 4 In the case of demodulating an MSK signal with a digital differential detection circuit, it is necessary to first convert the MSK signal into a digital signal component. It has no information in the amplitude direction. Therefore, it is not necessary to quantize, and the waveform may be shaped by using a comparator circuit as shown in FIG.

In the circuit of FIG. 4, the MSK signal supplied to the input terminal 1 is supplied to the inverting input of the comparator 2 and a rectangular wave signal is supplied with the reference voltage 0 (V) applied to the non-inverting input as a threshold value. Is converted to. This rectangular wave signal is subjected to rectification and amplitude suppression by the circuit composed of the resistor 3 and the Zener diode 4, and becomes a rectangular wave signal of 0 (V) or 5 (V). Further, this rectangular wave signal is shaped by the Schmitt trigger 5 and becomes a digital signal component M (t), which is sent out from the output terminal 6.

FIG. 5 shows a conventional detection circuit that detects this M (t) to obtain a demodulation signal D (t), and is composed of a shift register 11 and a D-flip-flop 12. In FIG. 5, M (t) supplied to the input terminal 10 is input to the shift register 11 and delayed by the clock signal of the frequency f _s by t _d which is the reciprocal time of the carrier frequency f _c. And is output as M (t−t _d ). In this case, the number of stages N of the shift register 1 1 is expressed by the following equation.

[0006] _{N = f s / f c =} f s · t d M output from the shift register 11 (t-t _d) is input as a clock signal of D- flip-flop 12, the D- flip-flops 12 The demodulated data D (t) is output from the output terminal 20. This situation will be described with reference to the timing chart shown in FIG.

For example, M (t) when the transmission data is “0” is M _H (t), and M (t) when the transmission data is “1” is M _L (t). . When the signal supplied to the data input D of the D-flip-flop 12 is M _H (t), the rising edge of M _H (t-t _d ) supplied to the clock input is as shown in FIGS. As shown in FIG. 5, the "0" portion of M _H (t) is sampled, and the demodulated data becomes "0". On the other hand, when the signal supplied to the data input D is M _L (t), the rising of M _L (t−t _d ) supplied to the clock input is as shown in FIGS. 6 (c) and 6 (d). , M _L (t) of “1” is sampled, and the demodulated data becomes “1”.

Normally, the MSK signal contains several wavelengths of M (t) in one data length T. Therefore, in the operation of the D-flip-flop 12 of FIG. 5, M (t−t _d ) will sample M (t) several times during the time T. When S _H a sampling number grayed when the M _H (t), the sampling number when the M _L (t) and S _L, the difference in nature S _H and S _L of the MSK signal is 1 or less. For example, if certain data is “0”, samples of S _H times “0” follow, and when data of “1”, samples of S _L times “1” continue.

[0009]

However, in the above-mentioned conventional MSK differential detection circuit, when a certain signal is transmitted, noise is mixed in the transmission system and the waveform is often disturbed. In the vicinity of the signal at the point A of _M'H in FIG. 7 (a) (t), in the normal case rising rising waveform of B portion shown by a dotted line, the rising of the C portion shown by the solid line by the influence of noise or the like If a rise of a clock signal _M'H (t-t _d) is the place to be sampled "0" if there is no waveform disturbance, samples the "1" by mistake because of the waveform disturbance Resulting in. Therefore, such a phenomenon causes a decrease in BER (Bit Error Rate), which is a problem.

The present invention solves the above-mentioned conventional problems, and an object of the present invention is to provide an excellent MSK differential detection circuit capable of preventing a decrease in BER even when affected by noise or the like.

[0011]

[Means for Solving the Problems]

 The present invention solves the above-mentioned conventional problems, and an MSK signal obtained by delaying an MSK signal converted into a digital component signal by a predetermined time based on a carrier component signal to obtain an MSK delay signal. The delay means and the digital signal component are held at a predetermined timing of the MSK delay signal to obtain a binary holding signal, and the holding signal is held at the next predetermined timing to obtain the next holding signal. A holding signal generating means for sequentially holding a holding signal held at a previous predetermined timing at a next predetermined timing to obtain a plurality of holding signals; and a total number of one of two binary values of each holding signal and the other. And a majority decision demodulation means for outputting one of the binary numbers having a large total number as demodulation data.

[0012]

[Action]

 Therefore, according to the present invention, the MSK signal as the digital signal component is sequentially held at a predetermined timing of the MSK delay signal given in time series in a certain period, and many of the obtained binary hold signals are obtained. Since the other value is output as demodulated data, even if the waveform is disturbed by the influence of noise or the like, it is possible to prevent the BER from decreasing.

[0013]

【Example】

 Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of an MSK differential detection circuit according to the present invention. In FIG. 1, the same components as those of the conventional example of FIG. 5 are represented by the same reference numerals. In this embodiment, instead of the D-flip-flop 12 in FIG. 5, a shift register 13 as a holding signal generating means and a majority decision circuit 14 as a majority decision operation demodulating means are used. 2 shows the configuration of the internal circuit of the shift register 13. That is, the shift register 13 is composed of n-stage D-flip-flops.

In FIG. 2, M (t) is supplied to the data input of the first stage D-flip-flop of the shift register 13, and M (t-t _d ) is supplied to the clock input of each D-flip-flop. . Therefore, M (t) is held at the rising edge which is the predetermined timing of the clock M (t-t _d ), and the held signal is supplied to the data input of the D-flip flop of the next stage, and the clock M (t) is supplied. It is sequentially shifted, that is, held by (t−t _d ).

M (t) and n holding signals k which are outputs of each D-flip-flop₀~ K_{n- 1} Are sent to the majority circuit 14 of FIG. 1 each time. The majority circuit 14 is k₀ ~ K_n-1The number of "0" s in "1" is compared with the number of "1" s. If there are many "0" s, "0" is output, and if there are many "1" s, "1" is output.

As shown in the timing charts of FIGS. 7A and 7B, when the waveform of M (t) is disturbed by noise or the like, the number n of the D-flip-flops of the shift register 13 becomes The operation of FIG. 1 when n = 3 is shown in FIGS. 7C and 7D. D '(t) in FIG. 7C shows signals sent from the shift register 13 to the majority circuit 14, that is, k ₀ , k ₁ , and k ₂ . In D ′ (t), k ₁ is “1” because it should be “0” because the waveform of M (t) is disturbed. At this time, the output D (t) of the majority decision circuit 14 shown in FIG. 7D is determined from the three values of k ₀ , k ₁ and k ₂ . In this case, since k ₀ and k ₂ are “0”, k ₁ is “1”, there are two “0” s, and one “1”, there are more “0” s. Therefore, the data d _s0 of D (t) becomes "0", and as a result, the error k ₁ is corrected.

[0018]

[Effect of device]

 As described above, the MSK differential detection circuit according to the present invention has the following effects.

1) In communication using MSK, reception with few errors can be performed.

2) It can also be applied to L-MSK used as a mobile reception modulation method for FM multiplex broadcasting, and demodulation with few errors is possible.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of an MSK differential detection circuit of the present invention.

FIG. 2 is an internal circuit diagram of the shift register in FIG.

FIG. 3 is a diagram showing a frequency arrangement of MSK signals.

FIG. 4 is a diagram showing a comparator circuit for converting an MSK signal into a digital signal.

FIG. 5 is a block diagram of a conventional MSK differential detection circuit.

FIG. 6 is a timing chart when demodulating a normal MSK signal.

FIG. 7 is a timing chart when demodulating an MSK signal having a waveform disturbance.

[Explanation of symbols]

 11 shift register 12 D-flip-flop 13 shift register 14 majority circuit

Claims (1)

[Scope of utility model registration request] 1. An MSK delay detection circuit for converting an MSK signal in which a carrier component signal is modulated by a binary transmission data signal into a digital component signal, and delay-detecting the digital signal component to obtain demodulated data. MSK signal delay means for delaying the digital signal component for a predetermined time based on a carrier component signal to obtain an MSK delay signal; and a binary holding signal for holding the digital signal component at a predetermined timing of the MSK delay signal. Then, the holding signal is held at a predetermined timing next to the MSK delay signal to obtain a next holding signal, and the holding signal held at a predetermined timing before the MSK delay signal is successively stored. Holding signal generating means for holding a plurality of holding signals at a predetermined timing, and comparing the total number of one of the two binary values of each holding signal with the total number of the other, and An MSK delay detection circuit, comprising: a majority decision operation demodulation means for outputting one of two values of the total number as the demodulation data.