JPH0669406A - Integrated circuit device - Google Patents

Abstract

PURPOSE:When setting a test mode in an external test signal input scheme to carry out an efficient operation test, to eliminate the need for consideration for a test signal input terminal to which a test signal is input after the completion of the operation test. CONSTITUTION:A DRAM chip 9 is fixed to a die pad 1 of a lead frame, and after sealing with a molding resin 10 for encapsulation, a test signal is input to a free pin (lead terminal) 5 other than normal lead terminals 4 with the outer frame being attached, a test mode is set by a test circuit in the chip 9, and a test signal is applied to perform an operation test, and thereafter the test signal input terminal 5 is cut off in the interface section of the molding resin 10.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electric operation test after a lead frame is assembled by using a lead frame, and more particularly to a test signal input terminal for inputting a test signal for setting a test mode when starting the operation test.

[0002]

2. Description of the Related Art When performing an operation test of a conventional integrated circuit device of this type, in order to efficiently perform this operation test, a test circuit provided in a chip is operated to set a test mode, Then, a formal test signal is applied to the corresponding input terminal to perform an operation test. In this case, to activate the test circuit, provide a dedicated external lead terminal,
There are an external input method in which a test signal for setting the test mode is input to this terminal, and an internal generation method in which a test circuit is activated by setting a specific condition for a normal external lead terminal.

FIG. 5 shows a 20-pin thin small outline package (Th) to which the above-mentioned external input method is applied.
in Small Outline Package
1M word x 1 assembled into TSOP)
Bit-structured dynamic random access memory (D
acoustic Random Access Memo
FIG. 4 is a plan view showing a sealing resin (a region surrounded by a double-dashed line) before the outer frame of the lead frame is cut off after the operation test of ry (hereinafter, abbreviated as DRAM) is transparent. In the figure, an integrated circuit chip 9 is fixed to a die pad 1 of a lead frame, and an electrode pad of the chip 9 and a lead of the lead frame are connected by a wire and then sealed with a resin 10.

The pin (lead terminal) 5 is an ordinary D of this kind.
It is an empty pin in the RAM configuration, and is set to the test mode by inputting "H" level during the operation test after the package is assembled. The die pad 1 to which the integrated circuit chip 9 is fixed is supported by the outer frame 3 by suspension leads 2. The outer frame 3 is provided with a guide hole 3a for facilitating the positioning when the outer frame 3 is inserted into the test socket, and the outer frame 3 does not cut off after the resin sealing and operates with the outer frame attached. The test is conducted. After the operation test process, the outer frame 3 is cut and removed at the interface of the sealing resin 10 of the hanging pin 2. Therefore, the test signal input terminal 5 is not disconnected even after the operation test process is completed, and the regular lead terminal 4 is not disconnected.
It is left as it is and must be fixed to "L" level or left open at all times. When open, the test signal input terminal 5 is fixed at "L" level by the pull-down circuit as shown in FIG. 6, and the test circuit is inactivated.

[0005]

In the conventional test mode setting method based on the external input method, the test signal input terminal is left as it is after the operation test, so that an unexpected voltage is not applied to this terminal. There is a problem that must be taken into consideration. In addition, there is a problem that this external input method can be applied only to a package having an empty pin.

[0006]

To solve the above problems, the present invention provides a test mode setting circuit for efficiently performing the operation test after the operation test with the outer frame of the lead frame attached after the package is assembled. The test signal input terminal for inputting the test signal for setting the test mode is cut off and removed so that the test signal input terminal has nothing to do with the subsequent operation. Further, by providing the test signal input terminal on the outer frame of the lead frame, it is possible to set the test mode of the external input method even when there are no vacant pins on the lead frame.

[0007]

The present invention will be described below with reference to the drawings. FIG. 1 is a plan view showing a sealing resin of Example 1 of the present invention as seen through. In the figure, comparing this figure with the conventional example of FIG. 5, in FIG. 5, the test signal input terminal remains unchanged after the operation test with the outer frame attached, whereas in the present invention, the outer frame and the test The difference is that the signal input terminal is cut and removed at the interface of the sealing resin 10. Therefore, the used test signal input terminal is not exposed to the outside,
There is no need to worry about unexpected voltage application.

FIG. 2 is a sectional view showing an example in which a means for easily cutting the test signal input terminal at the interface of the sealing resin is provided. In this example, as shown in FIG. 2 (A), half-etching 8 is locally preliminarily applied at the interface of the sealing resin 10 of the test signal input terminal 5 to a thickness of about 1/2. By arranging in this way, after the operation test is completed, the half etching section 8 can be cut very easily as shown in FIG. 2 (B).

Although the above half-etching is performed in the thickness direction for ease of cutting, it goes without saying that the same effect can be obtained even if the width is reduced in the width direction.

FIG. 3 is a plan view showing an example of a countermeasure when the external input method test mode cannot be set as it is because the lead frame has no empty pins. In the figure, a test signal input terminal 6 is newly provided in an empty lead portion between five and five lead rows on one side. If this is done, the number of terminals will increase by one as a standard product, and it will be necessary to fix it to the “L” level or leave it open in general use, so after the inspection process of the operation test is completed, The test signal input terminal 6 is naturally cut and removed at the sealing resin interface. The cut portion may be previously subjected to processing such as local half etching to give easy cutting.

FIG. 4 shows an example of applying the present invention to an integrated circuit device having no vacant pins and vacant lead portions, such as a 256K static RAM assembled in a 25-pin TSOP package, before sealing test signal input terminals. It is the top view which looked through resin and was shown.

In FIG. 4, a test signal input terminal 7 is provided on the outer frame 3 of the lead frame in this example. The suspension leads 2 that connect the outer frame 3 and the die pad 1 correspond to the internal leads hidden in the sealing resin 10. Then, the electrode pad on the chip 9 and the suspension lead 2 are connected by a bonding wire. The back surface of the chip 9 and the die pad 1 are bonded with a non-conductive adhesive.

After the test signal input terminal 7 is set to the test mode by applying an "H" level signal, an operation test is carried out. After this test is completed, the test signal input terminal 7 together with the outer frame 3 and the suspension leads 2 Is cut and removed at the interface of the sealing resin 10. Also in this example, it goes without saying that the cutting can be easily performed by subjecting the interface of the sealing resin 10 of the suspension lead 2 to processing such as local half etching for facilitating the cutting.

In any of the above examples, FIG.
By forming the pull-down circuit as shown in (1) in the chip, the test circuit can be stably maintained in the inactive state after the test signal input terminal is disconnected.

[0015]

As described above, according to the present invention, by cutting and removing the test signal input terminal after the inspection process,
In the product state, the user can use it without being aware of the presence of the test signal input terminal. However, if the cutting portion is locally thinly or thinly processed beforehand, there is an effect that it can be easily cut without adversely affecting other leads. Even if the lead frame has no vacant pins or vacant lead parts, a test signal input terminal is newly provided on the outer frame to set the test mode with an external input method that allows easy input, for efficient operation. Testing is possible.

[Brief description of drawings]

FIG. 1 is a plan view showing a sealing resin according to an embodiment of the present invention as seen through.

FIG. 2A is a partial cross-sectional view before cutting the test signal input terminal according to the second embodiment of the present invention, and FIG. 2B is a partial cross-sectional view after cutting.

FIG. 3 is a plan view showing an example of installation of test signal input terminals in the case of a package including a lead frame having no empty pins.

FIG. 4 is a plan view showing an example of installation of test signal input terminals in the case of a package with a lead frame having no vacant pins and vacant lead portions.

FIG. 5 is a plan view transparently showing a sealing resin before cutting an outer frame of a conventional integrated circuit device.

FIG. 6 is a circuit diagram of a pull-down circuit.

[Explanation of symbols]

 1 Die pad 2 Suspended lead 3 Outer frame 4 Regular lead terminal 5 Empty pin test signal input terminal 6 Empty lead test signal input terminal 7 Outer frame test signal input terminal 8 Half etching section 9 Integrated circuit chip 10 Sealing resin

Claims (5)

[Claims] 1. An integrated circuit device in which leads are attached to an integrated circuit chip by using a lead frame, an operation test is performed after resin-sealing with the outer frame of the lead frame attached, and the outer frame is cut off after the test is completed. 2. An integrated circuit device according to claim 1, wherein a test signal input terminal to which a test signal is input during the operation test is separated at an interface of the sealing resin after the operation test is completed. 2. The integrated circuit device according to claim 1, wherein the test signal input terminal is locally processed in advance at the interface portion of the sealing resin so as to be easily cut. 3. The integrated circuit device according to claim 1, wherein the test signal input terminal is originally assigned to a lead terminal which is an empty pin. 4. The integrated circuit device according to claim 1, wherein the test signal input terminal is newly formed on an empty lead portion of a lead frame. 5. The integrated circuit device according to claim 1, wherein the test signal input terminal is provided on an outer frame of the lead frame.