JPH0669357A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH0669357A JPH0669357A JP24589592A JP24589592A JPH0669357A JP H0669357 A JPH0669357 A JP H0669357A JP 24589592 A JP24589592 A JP 24589592A JP 24589592 A JP24589592 A JP 24589592A JP H0669357 A JPH0669357 A JP H0669357A
- Authority
- JP
- Japan
- Prior art keywords
- photoresist
- hole
- insulating film
- interlayer insulating
- exposure
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は半導体装置の製造方法に
関し、特に上層配線と下層配線を電気的に接続するため
のテーパー付きスルーホールの製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a tapered through hole for electrically connecting an upper wiring and a lower wiring.
【0002】[0002]
【従来の技術】従来の半導体装置では、上層配線と下層
配線を電気的に接続するために層間絶縁膜にテーパー付
きスルーホールを設けている。このようなテーパー付き
スルーホールの従来の製造方法の一例を図2に示す。ま
ず、図2(a)のように、下層配線1の上に層間絶縁膜
2を一回または2回のCVD法により8000Å程度デポジ
ションし、その後パターニングのためのフォトレジスト
3を塗布する。次いで、図2(b)のように、フォトリ
ソグラフィ技術により、スルーホール形成部のフォトレ
ジスト3を開孔する。2. Description of the Related Art In a conventional semiconductor device, a tapered through hole is provided in an interlayer insulating film for electrically connecting an upper wiring and a lower wiring. An example of a conventional manufacturing method of such a tapered through hole is shown in FIG. First, as shown in FIG. 2A, an interlayer insulating film 2 is deposited on the lower wiring 1 by the CVD method once or twice to about 8000 Å, and then a photoresist 3 for patterning is applied. Next, as shown in FIG. 2B, the photoresist 3 in the through-hole forming portion is opened by the photolithography technique.
【0003】そして、図2(c)のように、このフォト
レジスト3をマスクにして層間絶縁膜2にウェットエッ
チング又は等方性のドライエッチングにより、すり鉢状
のテーパー部を形成する。ついで、図2(d)のよう
に、前記フォトレジスト3をそのままマスクに用いたド
ライエッチングにより、層間絶縁膜2にスルーホール部
の開孔を行う。その後、図示は省略するが、上層配線を
スパッタし、フォトリソグラフィ技術により上層配線の
パターニングを行う。Then, as shown in FIG. 2C, a mortar-shaped tapered portion is formed on the interlayer insulating film 2 by wet etching or isotropic dry etching using the photoresist 3 as a mask. Then, as shown in FIG. 2D, the through holes are formed in the interlayer insulating film 2 by dry etching using the photoresist 3 as a mask as it is. Thereafter, although not shown, the upper wiring is sputtered and the upper wiring is patterned by the photolithography technique.
【0004】[0004]
【発明が解決しようとする課題】このような従来の半導
体装置の製造方法では、テーパー付きスルーホール形成
の際、ウェットエッチング(又は等方性のドライエッチ
ング)を用いるので、エッチングレートのばらつきにテ
ーパー部の形状,大きさが影響されやすく、これらの形
状、寸法を設計通りに制御することは困難であった。ま
た、ウェットエッチングとドライエッチングの2ステッ
プのエッチングなので、工期が長くなるという問題点が
あった。本発明の目的は、スルーホールの形状、寸法の
制御を容易に行い、かつ工期の短縮を可能にした半導体
装置の製造方法を提供することにある。In such a conventional method of manufacturing a semiconductor device, wet etching (or isotropic dry etching) is used when forming a tapered through hole, so that the variation in etching rate is reduced. The shape and size of the parts were easily affected, and it was difficult to control these shapes and dimensions as designed. In addition, there is a problem that the construction period becomes long because it is a two-step etching process of wet etching and dry etching. An object of the present invention is to provide a method of manufacturing a semiconductor device in which the shape and size of a through hole can be easily controlled and the construction period can be shortened.
【0005】[0005]
【課題を解決するための手段】本発明は、下層配線上に
設けた層間絶縁膜上にフォトレジストを塗布する工程
と、スルーホールの開孔箇所において前記フォトレジス
トに焦点及び光量を調整した第1の露光を行う工程と、
同箇所に通常の条件で第2の露光を行う工程と、そのフ
ォトレジストを現像して前記第1及び第2の露光で露光
された領域を除去する工程と、このフォトレジストをマ
スクにして前記層間絶縁膜を異方性エッチングし、テー
パー付きスルーホールを開孔する工程を含んでいる。According to the present invention, there is provided a step of applying a photoresist on an interlayer insulating film provided on a lower layer wiring, and a step of adjusting a focus and a light amount to the photoresist at an opening portion of a through hole. The step of performing the exposure of 1;
A step of performing a second exposure on the same portion under normal conditions, a step of developing the photoresist to remove the regions exposed by the first and second exposures, and a step of using the photoresist as a mask The method includes anisotropically etching the interlayer insulating film and forming a tapered through hole.
【0006】[0006]
【実施例】次に、本発明について図面を参照して説明す
る。図1は本発明の一実施例を工程順に示す断面図であ
る。先ず、図1(a)のように下層配線1上に膜厚8000
Å程度の酸化膜の層間絶縁膜2をCVD法により成長さ
せ、その後フォトレジスト3を塗布する。次に、露光装
置によりフォトレジスト3を露光するが、第1の露光工
程として、通常の露光条件の時より焦点をずらし、或い
は光量を減らす等の技術を使うことにより、図1(b)
のようにフォトレジスト3に対してすり鉢状の領域に露
光を行う、その後、スルーホールの設計値に応じた通常
条件の第2の露光工程を行う。しかる上で、フォトレジ
スト3を現像処理すると、図1(c)のように、表面側
では第1の露光工程によって浅いすり鉢状の部分が除去
され、また全厚さにわたっては第2の露光工程によって
スルーホールの設計値通りの部分が除去されたテーパー
付き開孔窓3aが開設される。DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1 is a sectional view showing an embodiment of the present invention in the order of steps. First, as shown in FIG. 1A, a film thickness of 8000 is formed on the lower layer wiring 1.
An interlayer insulating film 2 of about Å oxide film is grown by the CVD method, and then a photoresist 3 is applied. Next, the photoresist 3 is exposed by an exposure device. As a first exposure step, by using a technique such as defocusing or reducing the light amount as compared with the case of the normal exposure condition, the process shown in FIG.
As described above, the mortar-shaped region is exposed to the photoresist 3, and then the second exposure step is performed under normal conditions according to the design value of the through hole. Then, when the photoresist 3 is developed, as shown in FIG. 1C, the shallow mortar-shaped portion is removed by the first exposure step on the surface side, and the second exposure step is performed over the entire thickness. The tapered aperture window 3a is opened by removing the portion of the through hole as designed.
【0007】そして、このフォトレジスト3をマスクに
して、異方性のドライエッチングのエッチング形状がフ
ォトレジスト形状に依存し、エッチングレート比を1:
1にして層間絶縁膜2をエッチングすることにより、図
1(d)のように、フォトレジスト形状と同等に、表面
側にすり鉢部4aが開孔され、全厚さにわたって等径部
4bが開孔されたテーパー付きスルーホール4が形成さ
れる。その後、図示を省略するが、このスルーホール4
を含む領域に上層配線をスパッタ形成し、フォトリソグ
ラフィ技術によりパターニングを行う。このように、フ
ォトレジスト3の形状を露光,現像工程において制御す
ることにより、テーパー付きスルーホールを1回のドラ
イエッチングで形成することが可能となる。Then, using this photoresist 3 as a mask, the etching shape of anisotropic dry etching depends on the photoresist shape, and the etching rate ratio is 1 :.
By etching the inter-layer insulation film 2 to 1 as shown in FIG. 1 (d), the mortar portion 4a is opened on the front surface side and the equal-diameter portion 4b is opened over the entire thickness in the same manner as the photoresist shape. A perforated tapered through hole 4 is formed. After that, though not shown, this through hole 4
An upper layer wiring is sputtered in a region including a and patterned by a photolithography technique. As described above, by controlling the shape of the photoresist 3 in the exposure and development steps, it becomes possible to form the tapered through hole by one dry etching.
【0008】なお、図1(c)のフォトレジスト3の現
像工程の後に、 140℃程度の高温でフォトレジスト3を
焼きしめる工程を追加することにより、テーパー部やス
ルーホール部の側面をより滑らかにすることができる。It should be noted that, by adding a step of baking the photoresist 3 at a high temperature of about 140 ° C. after the developing step of the photoresist 3 of FIG. 1C, the side surfaces of the tapered portion and the through hole portion are made smoother. Can be
【0009】[0009]
【発明の効果】以上説明したように本発明は、フォトレ
ジストに対して第1及び第2の露光を行なうことで、表
面側にすり鉢状で全厚さにわたって等径の開孔を形成
し、このフォトレジストをマスクにして層間絶縁膜を異
方性エッチングしているので、テーパー付きスルーホー
ルを精度よく制御することができる。また、1回のエッ
チングでテーパー付きスルーホールを形成でき、工期の
短縮を図ることができる効果がある。As described above, according to the present invention, by performing the first and second exposures on the photoresist, a mortar-shaped opening having a uniform diameter is formed over the entire surface, Since the interlayer insulating film is anisotropically etched using this photoresist as a mask, the tapered through hole can be controlled accurately. In addition, a tapered through hole can be formed by one-time etching, which has the effect of shortening the construction period.
【図1】本発明の製造方法を工程順に示す断面図であ
る。FIG. 1 is a cross-sectional view showing the manufacturing method of the present invention in the order of steps.
【図2】従来の製造方法を工程順に示す断面図である。FIG. 2 is a cross-sectional view showing a conventional manufacturing method in process order.
1 下層配線 2 層間絶縁膜 3 フォトレジスト 4 テーパー付きスルーホール 4a すり鉢部 4b 等径部 1 Lower layer wiring 2 Interlayer insulating film 3 Photoresist 4 Tapered through hole 4a Mortar part 4b Equal diameter part
Claims (1)
孔したスルーホールを通して相互に電気接続する多層配
線構造を有する半導体装置において、前記層間絶縁膜を
形成した後にこの上にフォトレジストを塗布する工程
と、スルーホールの開孔箇所において前記フォトレジス
トに焦点及び光量を調整した第1の露光を行う工程と、
同箇所に通常の条件で第2の露光を行う工程と、そのフ
ォトレジストを現像して前記第1及び第2の露光で露光
された領域を除去する工程と、このフォトレジストをマ
スクにして前記層間絶縁膜を異方性エッチングし、テー
パー付きスルーホールを開孔する工程を含むことを特徴
とする半導体装置の製造方法1. A semiconductor device having a multilayer wiring structure in which a lower wiring and an upper wiring are electrically connected to each other through through holes formed in an interlayer insulating film, and a photoresist is formed on the interlayer insulating film after forming the interlayer insulating film. A step of applying, and a step of performing a first exposure in which the focus and the amount of light are adjusted on the photoresist at the opening portion of the through hole,
A step of performing a second exposure on the same portion under normal conditions, a step of developing the photoresist to remove the regions exposed by the first and second exposures, and a step of using the photoresist as a mask A method of manufacturing a semiconductor device, comprising a step of anisotropically etching an interlayer insulating film and forming a tapered through hole.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP04245895A JP3104425B2 (en) | 1992-08-22 | 1992-08-22 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP04245895A JP3104425B2 (en) | 1992-08-22 | 1992-08-22 | Method for manufacturing semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH0669357A true JPH0669357A (en) | 1994-03-11 |
JP3104425B2 JP3104425B2 (en) | 2000-10-30 |
Family
ID=17140418
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP04245895A Expired - Fee Related JP3104425B2 (en) | 1992-08-22 | 1992-08-22 | Method for manufacturing semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP3104425B2 (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007514201A (en) * | 2003-12-12 | 2007-05-31 | ヒューレット−パッカード デベロップメント カンパニー エル.ピー. | Method for forming a depression in the surface of a photoresist layer |
JP2012250388A (en) * | 2011-06-01 | 2012-12-20 | Canon Inc | Liquid ejection head and method of production thereof |
CN113140448A (en) * | 2020-01-16 | 2021-07-20 | 芯恩(青岛)集成电路有限公司 | Semiconductor structure and manufacturing method thereof |
-
1992
- 1992-08-22 JP JP04245895A patent/JP3104425B2/en not_active Expired - Fee Related
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007514201A (en) * | 2003-12-12 | 2007-05-31 | ヒューレット−パッカード デベロップメント カンパニー エル.ピー. | Method for forming a depression in the surface of a photoresist layer |
JP2012250388A (en) * | 2011-06-01 | 2012-12-20 | Canon Inc | Liquid ejection head and method of production thereof |
CN113140448A (en) * | 2020-01-16 | 2021-07-20 | 芯恩(青岛)集成电路有限公司 | Semiconductor structure and manufacturing method thereof |
CN113140448B (en) * | 2020-01-16 | 2022-10-28 | 芯恩(青岛)集成电路有限公司 | Semiconductor structure and manufacturing method thereof |
Also Published As
Publication number | Publication date |
---|---|
JP3104425B2 (en) | 2000-10-30 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP3271094B2 (en) | Laminated wiring board and method of manufacturing the same | |
US5922516A (en) | Bi-layer silylation process | |
JPH0669357A (en) | Manufacture of semiconductor device | |
JP2720023B2 (en) | Method for manufacturing semiconductor device | |
KR100197538B1 (en) | Forming method for metal wiring in semiconductor device | |
JPH0467333B2 (en) | ||
JP2808674B2 (en) | Method for manufacturing semiconductor device | |
JPH0435048A (en) | Forming method for multilayer wiring of semiconductor device | |
JPH0237707A (en) | Manufacture of semiconductor device | |
JPS5955015A (en) | Manufacture of semiconductor device | |
JPH0348424A (en) | Manufacture of semiconductor device | |
JPH0590220A (en) | Manufacture of semiconductor device | |
JPS583244A (en) | Manufacture of semiconductor device | |
KR100396689B1 (en) | Method for manufacturing gate of semiconductor device | |
KR100372657B1 (en) | Method for forming contact of semiconductor device | |
KR950014268B1 (en) | Forming method of contact | |
JP2912002B2 (en) | Method for manufacturing semiconductor device | |
JPH03257822A (en) | Manufacture of semiconductor device | |
JPH0358531B2 (en) | ||
JPS5843540A (en) | Wiring formation in semiconductor device | |
JPH0212827A (en) | Manufacture of semiconductor device | |
JPH0594975A (en) | Manufacture of semiconductor device | |
JPH02231711A (en) | Manufacture of semiconductor device | |
JPH0936101A (en) | Manufacture of semiconductor device | |
JPH06295878A (en) | Fabrication of semiconductor device |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
LAPS | Cancellation because of no payment of annual fees |