JPH0669283A - Method for mounting semiconductor device with protruding electrodes - Google Patents

Method for mounting semiconductor device with protruding electrodes

Info

Publication number
JPH0669283A
JPH0669283A JP5134406A JP13440693A JPH0669283A JP H0669283 A JPH0669283 A JP H0669283A JP 5134406 A JP5134406 A JP 5134406A JP 13440693 A JP13440693 A JP 13440693A JP H0669283 A JPH0669283 A JP H0669283A
Authority
JP
Japan
Prior art keywords
metal
metal projection
semiconductor element
substrate
circuit board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP5134406A
Other languages
Japanese (ja)
Other versions
JP2797900B2 (en
Inventor
Hiroaki Fujimoto
博昭 藤本
Tetsuhiro Yamamoto
哲浩 山本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP13440693A priority Critical patent/JP2797900B2/en
Publication of JPH0669283A publication Critical patent/JPH0669283A/en
Application granted granted Critical
Publication of JP2797900B2 publication Critical patent/JP2797900B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector

Landscapes

  • Wire Bonding (AREA)

Abstract

PURPOSE:To reduce the number of correcting steps for positional diviation of bumps from a circuit board by image recognition and to prevent adherence of dust to a metal protrusion after transferring, deformation of the protrusion by using a metal protrusion board for transferring as a chip containing vessel as it is after transferring. CONSTITUTION:The method for mounting a semiconductor element with protruding electrodes comprises the steps of mounting semiconductor devices 9 on a metal protruding board 4 having a plurality of metal protrusions 5 fixedly connected, fixedly connecting electrodes 7 of the devices 9 to the protrusions 5 at least by pressurizing, and increasing connecting strength of the protrusions 5 to the electrodes 7 of the device 9 larger than that of the protrusions 5 to the board 4. Then, the method comprises the steps of conveying the board 4 in which a plurality of the device 9 are fixedly connected through the protrusions 5, separating the devices 9 in which the protrusions 5 are connected from the board 4, and transferring the protrusions 5 to the devices 9. Then, the method comprises the steps of mounting the devices 9 in which the protrusions 5 are transferred on a circuit board 15, and connecting the devices 9 to the board 15.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、半導体実装に関する半
導体素子の電極上へのバンプ形成に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to bump formation on electrodes of a semiconductor element for mounting semiconductors.

【0002】[0002]

【従来の技術】近年、多ピン・狭ピッチLSIの実装方
式として、TAB方式やフリップチップ方式が実用化さ
れている。これらの方式は、いずれも半導体素子の電極
上にバンプ(金属突起)を必要とし、バンプの形成方法
が重要な技術となっている。バンプ形成方法としては、
ウエハー段階でめっき法により形成する方法が一般的で
あるが、蒸着装置やエッチング装置など、各々の工程に
合わせて装置が必要となり、設備費等の点でコストが高
い。この方法に対して、バンプを別基板に形成し、その
バンプを半導体素子の電極上に転写する方法がある。
2. Description of the Related Art In recent years, a TAB method and a flip chip method have been put into practical use as a mounting method for a multi-pin, narrow-pitch LSI. All of these methods require bumps (metal projections) on the electrodes of the semiconductor element, and the method of forming bumps is an important technique. As a bump forming method,
A method of forming by a plating method at the wafer stage is generally used, but an apparatus such as a vapor deposition apparatus or an etching apparatus is required for each process, and the cost is high in terms of equipment cost and the like. In contrast to this method, there is a method of forming bumps on another substrate and transferring the bumps onto the electrodes of the semiconductor element.

【0003】材質が半田であるバンプを別基板に形成
し、半導体素子の電極上に転写する方法が、USP36
21564号公報に開示されている。しかしながら、半
田をバンプとして転写により形成された半導体素子を拡
散により回路基板に接合すると、温度が上昇した場合、
半導体素子と回路基板の膨張係数の相違によりバンプに
ストレスが生じ、信頼性が低下するという問題があっ
た。そこで、温度上昇に対しても信頼性を高く保つこと
が可能である、拡散による接合ではなく接触式の接合が
開発された。この接触式の接合で半導体素子と回路基板
を接合する際に用いるバンプの材質としては、化学的に
安定で、かつ酸化膜が形成されにくいものが求められ、
現在はバンプの材質としてはAuが主に用いられてい
る。
A method of forming bumps made of solder on another substrate and transferring the bumps onto the electrodes of a semiconductor element is USP36.
It is disclosed in Japanese Patent Publication No. 21564. However, when a semiconductor element formed by transfer using solder as a bump is bonded to a circuit board by diffusion, if the temperature rises,
There is a problem that stress is generated in the bumps due to the difference in expansion coefficient between the semiconductor element and the circuit board, and the reliability is reduced. Therefore, contact-type joining was developed instead of diffusion-based joining, which can maintain high reliability against temperature rise. The material of the bump used when joining the semiconductor element and the circuit board by this contact-type joining is required to be chemically stable and to prevent an oxide film from being formed,
Currently, Au is mainly used as the material for the bumps.

【0004】以下に、従来の転写によるバンプ形成方法
とバンプが形成された半導体素子の実装方法について図
面を参照しながら説明する。
A conventional bump forming method by transfer and a semiconductor element mounting method in which bumps are formed will be described below with reference to the drawings.

【0005】図7は、金属突起基板以外に別個にLSI
チップを収納するチップトレーを用いて、LSIチップ
を搬送する従来の突起電極を有する半導体素子の実装方
法の概略を示したものである。
FIG. 7 shows an LSI separately from the metal projection substrate.
1 is a schematic view of a conventional method of mounting a semiconductor element having a protruding electrode that carries an LSI chip by using a chip tray that houses a chip.

【0006】まず図7(a)は、LSIチップの電極と
金属突起基板上のAuバンプとの位置合わせを行い、L
SIチップを金属突起基板に設置する工程を示したもの
である。金属突起基板4はガラス等の基板の片面にIT
O等の導電膜2が形成されており、Auバンプ5は、フ
ォトレジストをマスクにして、電解めっきにより金属突
起基板4上に形成されている。金属突起基板4のAuバ
ンプ5と真空コレット6に支持されたLSIチップ9の
チップ電極7を位置合わせをし、LSIチップ9を金属
突起基板4上に設置する。
First, in FIG. 7A, the electrodes of the LSI chip are aligned with the Au bumps on the metal projection substrate, and L
It shows a process of installing the SI chip on the metal projection substrate. The metal projection substrate 4 is an IT on one side of the substrate such as glass.
A conductive film 2 such as O is formed, and the Au bumps 5 are formed on the metal projection substrate 4 by electrolytic plating using a photoresist as a mask. The Au bumps 5 of the metal projection substrate 4 and the chip electrodes 7 of the LSI chip 9 supported by the vacuum collet 6 are aligned, and the LSI chip 9 is placed on the metal projection substrate 4.

【0007】次に図7(b)は、LSIチップの電極へ
の金属突起基板上のAuバンプの転写を行うための接合
工程を示したものである。加圧ツール8によりLSIチ
ップ9を加圧、加熱し、LSIチップ9のチップ電極と
Auバンプ5との合金を形成し、チップ電極とAuバン
プ5を接合する。図8はこのLSIチップ9の電極と金
属突起基板4上のAuバンプ5との接合工程の断面図を
示したものである。この時Auバンプ5とLSIチップ
9のチップ電極7の接合強度はAuバンプ5と金属突起
基板4の接合強度よりも大きくなるようにする。
Next, FIG. 7B shows a bonding step for transferring the Au bumps on the metal projection substrate to the electrodes of the LSI chip. The pressure tool 8 pressurizes and heats the LSI chip 9 to form an alloy between the chip electrode of the LSI chip 9 and the Au bump 5, and the chip electrode and the Au bump 5 are bonded. FIG. 8 is a sectional view showing a step of joining the electrodes of the LSI chip 9 and the Au bumps 5 on the metal projection substrate 4. At this time, the bonding strength between the Au bump 5 and the chip electrode 7 of the LSI chip 9 is set to be higher than the bonding strength between the Au bump 5 and the metal projection substrate 4.

【0008】次に図7(c)は、真空コレットにより金
属突起基板上のLSIチップを吸着し、AuバンプをL
SIチップへ転写させる転写工程と、LSIチップのチ
ップトレーへの収納工程とを示したものである。金属突
起基板4上のLSIチップ9を真空コレット6で吸着し
て引き上げることにより、Auバンプ5を金属突起基板
4からLSIチップ9のチップ電極7に転写する。次に
そのままLSIチップ9をチップトレー12まで搬送
し、ポケット13に収納する。
Next, as shown in FIG. 7 (c), the LSI chip on the metal projection substrate is sucked by the vacuum collet and the Au bump is set to L level.
The transfer process of transferring to the SI chip and the storing process of the LSI chip in the chip tray are shown. By sucking the LSI chip 9 on the metal projection substrate 4 with the vacuum collet 6 and pulling it up, the Au bumps 5 are transferred from the metal projection substrate 4 to the chip electrodes 7 of the LSI chip 9. Next, the LSI chip 9 is conveyed as it is to the chip tray 12 and stored in the pocket 13.

【0009】上記図7のLSIチップの電極と金属突起
基板上のAuバンプとの位置合わせをし、LSIチップ
を金属突起基板に設置する工程(a)、LSIチップの
電極への金属突起基板上のAuバンプの転写を行うため
の接合工程(b)、真空コレットにより金属突起基板上
のLSIチップを吸着し、AuバンプをLSIチップへ
転写させる転写工程及びLSIチップのチップトレーへ
の収納工程(c)の各々の工程を1個1個のLSIチッ
プ毎に繰り返すことにより、複数個のAuバンプが転写
されたLSIチップ9をチップトレー12に収納する。
次に、この複数個のAuバンプが転写されたLSIチッ
プが収納されたチップトレーを搬送する。
The step of aligning the electrodes of the LSI chip with the Au bumps on the metal projection substrate of FIG. 7 and placing the LSI chip on the metal projection substrate (a), on the metal projection substrate to the electrodes of the LSI chip Bonding step (b) for transferring the Au bumps, a transfer step of adsorbing the LSI chip on the metal projection substrate with a vacuum collet and transferring the Au bumps to the LSI chip, and a step of storing the LSI chip in a chip tray ( By repeating the steps c) for each LSI chip, the LSI chip 9 to which the plurality of Au bumps are transferred is housed in the chip tray 12.
Next, the chip tray in which the LSI chips to which the plurality of Au bumps have been transferred are stored is transported.

【0010】図7(d)は、上記のように形成され、チ
ップトレーに収納されたLSIチップを真空コレットに
より吸着する吸着工程と、Auバンプが転写されたLS
Iチップの回路基板への設置工程と、LSIチップの回
路基板への接合工程を示したものである。LSIチップ
9を収納したチップトレー12は搬送され、チップトレ
ー12を設置するX−Yテーブル14上に設置される。
次に、Auバンプ5を有したLSIチップ9を真空コレ
ット11により吸着し、チップトレー12のポケット1
3からとりだし、回路基板15の導体配線16上に設置
し、LSIチップ9のAuバンプ5と導体配線16を接
続し、LSIチップ9を回路基板15に接合する。
FIG. 7D shows a suction step of suctioning the LSI chip, which is formed as described above and stored in the chip tray, by the vacuum collet, and the LS to which the Au bump is transferred.
The process of installing the I chip on the circuit board and the process of joining the LSI chip to the circuit board are shown. The chip tray 12 accommodating the LSI chip 9 is conveyed and set on the XY table 14 on which the chip tray 12 is set.
Next, the LSI chip 9 having the Au bumps 5 is sucked by the vacuum collet 11 and the pocket 1 of the chip tray 12 is
3 is placed on the conductor wiring 16 of the circuit board 15, the Au bumps 5 of the LSI chip 9 and the conductor wiring 16 are connected, and the LSI chip 9 is bonded to the circuit board 15.

【0011】図9は、図7中の金属突起基板4の製造方
法を示したものである。図9(a)に示すように、ガラ
ス等の絶縁性基板1の全面に蒸着法などにより導電膜2
を形成し、さらにその導電膜2上に絶縁膜3を形成し、
転写させる半導体素子の電極に対応する位置に開口部1
7を設ける。この時、絶縁性基板1としてはガラスある
いは石英を、導電膜2としてはTi/PtあるいはIT
Oを、絶縁膜3としてはレジスト等を用いる。
FIG. 9 shows a method for manufacturing the metal projection substrate 4 shown in FIG. As shown in FIG. 9A, the conductive film 2 is formed on the entire surface of the insulating substrate 1 such as glass by a vapor deposition method or the like.
And an insulating film 3 is further formed on the conductive film 2.
The opening 1 is provided at a position corresponding to the electrode of the semiconductor element to be transferred.
7 is provided. At this time, glass or quartz is used as the insulating substrate 1, and Ti / Pt or IT is used as the conductive film 2.
O is used, and a resist or the like is used as the insulating film 3.

【0012】次に、図9(b)に示すように導電膜2を
電極として、電解めっき法により金属突起基板4の開口
部17にAuバンプ5を密着させる。本発明ではAuバ
ンプの金属突起基板4への接合と呼ぶ。この電解めっき
の際の電流密度や温度等を制御することにより、Auバ
ンプ5に内部応力を持たせてやる。これは、後のLSI
チップ9の電極への金属突起基板上のAuバンプの転写
を行うための接合工程(図7(b))の際に、Auバン
プ5とLSIチップ9のチップ電極7の接合強度がAu
バンプ5と金属突起基板4の接合強度よりも大きくなる
ように、Auバンプ5と金属突起基板4の接合強度を小
さくしておく必要があるためである。
Next, as shown in FIG. 9B, the Au bumps 5 are brought into close contact with the openings 17 of the metal projection substrate 4 by electrolytic plating using the conductive film 2 as an electrode. In the present invention, this is called joining of Au bumps to the metal projection substrate 4. The Au bumps 5 are given internal stress by controlling the current density, temperature, etc. during this electrolytic plating. This is the later LSI
During the bonding process (FIG. 7B) for transferring the Au bumps on the metal projection substrate to the electrodes of the chip 9, the bonding strength between the Au bumps 5 and the chip electrodes 7 of the LSI chip 9 is Au.
This is because it is necessary to reduce the bonding strength between the Au bumps 5 and the metal projection substrate 4 so as to be higher than the bonding strength between the bumps 5 and the metal projection substrate 4.

【0013】更に、図9(c)に示すように絶縁膜3を
除去し、Auバンプ5を有した金属突起基板4を得る。
Further, as shown in FIG. 9C, the insulating film 3 is removed to obtain a metal projection substrate 4 having Au bumps 5.

【0014】図10は、Auバンプが転写されたLSI
チップの回路基板への接合工程の断面図を示したもので
ある。図10(a)に示す方法は、回路基板15とLS
Iチップ9の間に形成した光硬化性樹脂18の硬化収縮
力によりAuバンプ5と導体配線16を圧接したもので
ある。また図10(b)に示した方法はAuバンプ5と
導体配線16を熱圧着により接合する方法である。また
LSIチップ9の回路基板への接合方法はこれらの方式
に限らずTAB方式などを適用してもよい。
FIG. 10 shows an LSI having Au bumps transferred thereon.
It is a sectional view showing a step of joining the chip to the circuit board. The method shown in FIG. 10A is applied to the circuit board 15 and the LS.
The Au bumps 5 and the conductor wirings 16 are pressed against each other by the curing shrinkage force of the photocurable resin 18 formed between the I chips 9. The method shown in FIG. 10B is a method of joining the Au bump 5 and the conductor wiring 16 by thermocompression bonding. The method of joining the LSI chip 9 to the circuit board is not limited to these methods, and the TAB method or the like may be applied.

【0015】[0015]

【発明が解決しようとする課題】しかしながら、上記従
来の突起電極を有する半導体素子の実装方法では、LS
Iチップ9の回路基板14への設置工程の際に、LSI
チップ9の電極7と回路基板15との位置ずれ補正を1
個1個のLSIチップに対して、画像認識をして行う必
要がある。図11は、このLSIチップと回路基板との
位置ずれ補正を行い、LSIチップを回路基板に設置す
る工程の断面図である。
However, in the conventional method for mounting a semiconductor element having a bump electrode, the LS is not used.
During the process of installing the I-chip 9 on the circuit board 14, the LSI
The positional deviation between the electrode 7 of the chip 9 and the circuit board 15 is corrected to 1
It is necessary to perform image recognition for each LSI chip. FIG. 11 is a cross-sectional view of a process of correcting the positional deviation between the LSI chip and the circuit board and installing the LSI chip on the circuit board.

【0016】チップトレー12を設置するX−Yテーブ
ル14上に設置されたチップトレー12のポケット13
に収納されたLSIチップ9は真空コレット11により
吸着され、回路基板を設置するX−Yテ−ブル19上に
設置された回路基板15上まで移動される。この時、搬
送されてきたLSIチップ9と、このLSIチップ9を
接合する回路基板15との位置関係はチップトレー搬送
中にLSIチップがポケット内で移動し、正確には把握
できないため、LSIチップ9と回路基板15のセンタ
ーには、ずれ(L)が生じる。ここで、ずれ(L)を補
正するために、LSIチップ9と回路基板15との間に
アライメントカメラ20を挿入し、各々の位置を画像認
識を行う。この画像認識の結果を基に行った、LSIチ
ップ9と回路基板15とのずれの補正が終了した後、L
SIチップ9を回路基板15へ設置する。
The pocket 13 of the chip tray 12 installed on the XY table 14 on which the chip tray 12 is installed.
The LSI chip 9 housed in the substrate is sucked by the vacuum collet 11 and moved to the circuit board 15 placed on the XY table 19 on which the circuit board is placed. At this time, the positional relationship between the conveyed LSI chip 9 and the circuit board 15 to which the LSI chip 9 is bonded cannot be accurately grasped because the LSI chip moves in the pocket during the conveyance of the chip tray, and therefore the LSI chip cannot be accurately grasped. A deviation (L) occurs between the center of 9 and the center of the circuit board 15. Here, in order to correct the deviation (L), the alignment camera 20 is inserted between the LSI chip 9 and the circuit board 15, and each position is subjected to image recognition. After the correction of the deviation between the LSI chip 9 and the circuit board 15 based on the result of this image recognition is completed, L
The SI chip 9 is installed on the circuit board 15.

【0017】上記のアライメントカメラ20を用いた画
像認識を利用したLSIチップ9と回路基板15のセン
ターの位置ずれ補正工程は、図11に示すように、1個
1個のLSIチップ9がチップトレー12のポケット1
3内でチップトレー12の搬送中にランダムに移動する
ため、LSIチップ9各々に対して行わなければならな
い。この画像認識による位置ずれ補正工程には、1個の
LSIチップ当り2〜10秒の時間を要し、トータルで
は相当の時間をこの画像認識による位置ずれ補正工程に
費やさなければならない。
In the process of correcting the positional deviation between the centers of the LSI chip 9 and the circuit board 15 using the image recognition using the alignment camera 20 as described above, as shown in FIG. 12 pockets 1
Since it moves randomly within the chip tray 12 during the transportation of the chip tray 12, it must be performed for each LSI chip 9. This misregistration correction process by image recognition requires a time of 2 to 10 seconds for one LSI chip, and a considerable amount of time must be spent in the misalignment correction process by image recognition in total.

【0018】また、特にAuバンプ5転写後のLSIチ
ップ9のチップトレー12への収納時に、Auバンプ5
にダストが付着したり、あるいは、LSIチップ9を載
置したチップトレー12の搬送時に、振動等によりLS
Iチップ9が移動し、その際特定のAuバンプ5に応力
がかかり、Auバンプ5が変形することがある。
Further, particularly when the LSI chip 9 is transferred to the chip tray 12 after the Au bump 5 is transferred, the Au bump 5
Dust is attached to the LS, or when the chip tray 12 on which the LSI chip 9 is mounted is conveyed, vibrations or the like cause LS.
When the I-chip 9 moves, the specific Au bump 5 is stressed at that time, and the Au bump 5 may be deformed.

【0019】図12(a)及び(b)は、Auバンプに
ダストが付着したLSIチップ及びAuバンプが変形し
たLSIチップを回路基板に実装した断面図を示したも
のである。この図から明らかなように、Auバンプ5に
ダスト21が付着したり(図12(a))、Auバンプ
5が変形したり(図12(b))すると、回路基板15
への接合の際に、接続不良や断線が生じる。
FIGS. 12A and 12B are cross-sectional views showing an LSI chip in which dust is attached to the Au bump and an LSI chip in which the Au bump is deformed, which are mounted on a circuit board. As is clear from this figure, when the dust 21 is attached to the Au bumps 5 (FIG. 12A) or the Au bumps 5 are deformed (FIG. 12B), the circuit board 15
Poor connection or disconnection occurs when joining to.

【0020】本発明は上記問題点を解決するもので、回
路基板15への設置の際の各々のLSIチップ9の電極
7と回路基板15の位置ずれ補正をするための画像認識
工程の短縮等の工程短縮、及びLSIチップ9搬送によ
る転写後のAuバンプ5へのダスト21付着等の汚れ、
あるいはAuバンプ5の変形に基づく回路基板への接合
の際の接続不良や断線を防止する突起電極を有する半導
体素子の実装方法を提供することを目的とする。
The present invention solves the above problems and shortens the image recognition process for correcting the positional deviation between the electrode 7 of each LSI chip 9 and the circuit board 15 when the circuit board 15 is installed on the circuit board 15. And shortening the process, and dirt such as adhesion of dust 21 on the Au bumps 5 after transfer due to transfer of the LSI chip 9,
Another object of the present invention is to provide a method for mounting a semiconductor element having a protruding electrode that prevents a connection failure or disconnection at the time of joining to a circuit board due to deformation of the Au bump 5.

【0021】[0021]

【課題を解決するための手段】上記目的を達成するため
に、本発明の金属突起を有した半導体素子の実装方法
は、複数個の金属突起が接合固定された金属突起基板に
半導体素子を設置する第1の設置工程と、少なくとも加
圧を行って前記半導体素子の電極と前記金属突起を接合
固定し、前記金属突起と前記半導体素子の電極との接合
強度を前記金属突起と前記金属突起基板との接合強度よ
りも大きくする第1の接合工程と、前記第1の接合工程
で複数個の前記半導体素子が前記金属突起を介して接合
固定された前記金属突起基板を搬送する金属突起基板搬
送工程と、前記金属突起基板搬送工程により搬送された
前記金属突起基板から前記金属突起が接合された前記半
導体素子を剥離させ、前記突起電極を前記半導体素子に
転写する金属突起転写工程と、前記突起電極が転写され
た前記半導体素子を回路基板上に設置する第2の設置工
程と、前記突起電極が転写された前記半導体素子を回路
基板上に接合する第2の接合工程とを備えてなる突起電
極を有する半導体素子の実装方法を用いる。
In order to achieve the above object, a method for mounting a semiconductor device having metal protrusions according to the present invention is a semiconductor device mounted on a metal protrusion substrate to which a plurality of metal protrusions are bonded and fixed. And the metal protrusion is bonded to and fixed to the electrode of the semiconductor element by bonding the electrode of the semiconductor element and the electrode of the semiconductor element with each other. And a metal protrusion substrate transfer for conveying the metal protrusion substrate on which a plurality of the semiconductor elements are bonded and fixed via the metal protrusion in the first bonding process. And a step of removing the semiconductor element to which the metal projection is bonded from the metal projection substrate transported in the step of transporting the metal projection substrate, and transferring the projection electrode to the semiconductor element. A second mounting step of mounting the semiconductor element having the protruding electrodes transferred thereon on a circuit board, and a second bonding step of bonding the semiconductor element having the transferred protruding electrodes onto the circuit board. A method of mounting a semiconductor element having a protruding electrode including the above is used.

【0022】[0022]

【作用】上記構成により、金属突起を半導体素子に形成
した後、半導体素子をそのまま金属突起基板上に残し、
転写するための接合工程をすべて完了後その基板をチッ
プトレーとして用いることができるため、チップトレー
収納工程と半導体素子の回路基板への設置の際の金属突
起と導体配線との位置ずれ補正の工程を省略することが
でき、さらに素子搬送やチップトレーへの収納による金
属突起の汚れや変形を防ぐことができる。
With the above structure, after the metal projection is formed on the semiconductor element, the semiconductor element is left on the metal projection substrate as it is,
Since the board can be used as a chip tray after completing all the joining steps for transferring, the step of accommodating the misalignment between the metal projection and the conductor wiring when the chip tray is housed and the semiconductor element is installed on the circuit board. Can be omitted, and the metal protrusions can be prevented from being contaminated or deformed due to element transport or storage in the chip tray.

【0023】[0023]

【実施例】以下に、本発明の実施例における突起電極を
有する半導体素子の実装方法を図面を参照しながら説明
する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A method of mounting a semiconductor device having a bump electrode according to an embodiment of the present invention will be described below with reference to the drawings.

【0024】(実施例1)図1は、金属突起基板上のA
uバンプをLSIチップに転写するために接合をし、L
SIチップを金属突起基板4上に設置したまま次工程に
搬送する本発明第1の実施例の突起電極を有する半導体
素子の実装方法の概略を示したものである。
(Embodiment 1) FIG. 1 shows A on a metal projection substrate.
L is bonded to transfer the u bump to the LSI chip.
1 shows an outline of a method of mounting a semiconductor element having a protruding electrode according to a first embodiment of the present invention in which an SI chip is placed on a metal protruding substrate 4 and conveyed to the next step.

【0025】まず、図1(a)は、LSIチップの電極
と金属突起基板上のAuバンプとの位置合わせを行い、
LSIチップを金属突起基板に設置する第1の設置工程
を示したものである。金属突起基板4上のAuバンプ5
と真空コレット6に支持されたLSIチップ9のアルミ
電極7とを位置合わせをし、LSIチップ9を金属突起
基板4上に設置する。なお、金属突起基板4は図9に示
した従来の製造方法により製造されており、1個1個の
LSIチップに対応するAuバンプ群の相対的な位置関
係は精度よく制御されている。
First, as shown in FIG. 1A, the electrodes of the LSI chip and the Au bumps on the metal projection substrate are aligned,
6 shows a first installation step of installing an LSI chip on a metal projection substrate. Au bump 5 on metal projection substrate 4
The aluminum electrode 7 of the LSI chip 9 supported by the vacuum collet 6 is aligned, and the LSI chip 9 is placed on the metal projection substrate 4. The metal projection substrate 4 is manufactured by the conventional manufacturing method shown in FIG. 9, and the relative positional relationship of the Au bump group corresponding to each LSI chip is accurately controlled.

【0026】次に図1(b)は、LSIチップの電極へ
のAuバンプの接合を行う第2の接合工程を示したもの
である。約400℃で加熱した加圧ツール8を用いて加
圧・加熱を行い、金属突起基板4上のAuバンプ5とL
SIチップ9のアルミ電極7との間に合金を形成して、
Auバンプ5とアルミ電極7とを接合させる。この時、
Auバンプ5とアルミ電極7との接合強度は、Auバン
プ5と金属突起基板4との接合強度よりも大きくなる。
その後、加圧ツール8による加圧を解除することによ
り、Auバンプ5を有したLSIチップ9を金属突起基
板4上に残留させる。このように、金属突起基板4上に
LSIチップ9をそのまま残留させることができるの
は、転写用接合工程の際に、溶融してしまう半田ではな
く、Auをバンプの材料として用いているためである。
Next, FIG. 1B shows a second joining step for joining the Au bumps to the electrodes of the LSI chip. Pressurization / heating is performed using the pressing tool 8 heated at about 400 ° C., and the Au bumps 5 and L on the metal projection substrate 4 are
An alloy is formed between the SI chip 9 and the aluminum electrode 7,
The Au bump 5 and the aluminum electrode 7 are joined. At this time,
The bonding strength between the Au bump 5 and the aluminum electrode 7 is larger than the bonding strength between the Au bump 5 and the metal projection substrate 4.
After that, the pressure applied by the pressure tool 8 is released to leave the LSI chip 9 having the Au bumps 5 on the metal projection substrate 4. As described above, the reason why the LSI chip 9 can be left as it is on the metal projection substrate 4 is that Au is used as the material of the bump instead of the solder that melts during the transfer bonding process. is there.

【0027】上記図1のLSIチップの電極と金属突起
基板上のAuバンプとの位置合わせをし、LSIチップ
を金属突起基板に設置する第1の設置工程(a)及びL
SIチップの電極とAuバンプとの接合を行う第1の接
合工程(b)を複数回繰り返すことにより、複数個のL
SIチップ9を金属突起基板4上に設置する。複数個の
LSIチップ9が設置された金属突起基板4は、そのま
ま次工程に搬送され、これによりLSIチップ9を搬送
する。すなわち、電極7とAuバンプ5との接合を行う
第1の接合工程が終了したLSIチップ9は、従来の突
起電極を有する半導体素子の実装方法のようにチップト
レーへ収納せず、金属突起基板4上に設置されたまま搬
送される。
The first installation step (a) and L in which the electrodes of the LSI chip of FIG. 1 and the Au bumps on the metal projection substrate are aligned and the LSI chip is installed on the metal projection substrate.
By repeating the first bonding step (b) for bonding the electrodes of the SI chip and the Au bumps a plurality of times, a plurality of L
The SI chip 9 is placed on the metal projection substrate 4. The metal projection substrate 4 on which the plurality of LSI chips 9 are installed is directly transported to the next step, and thus the LSI chip 9 is transported. That is, the LSI chip 9 for which the first bonding step of bonding the electrode 7 and the Au bump 5 is completed is not housed in the chip tray unlike the conventional mounting method of a semiconductor element having a protruding electrode, and the metal protruding substrate is used. 4 is transported as it is installed.

【0028】次に図1(c)は、AuバンプのLSIチ
ップへの転写工程と、Auバンプを有するLSIチップ
を回路基板へ設置する第2の設置工程と、Auバンプを
有するLSIチップを回路基板へ接合する第2の接合工
程を示したものである。複数個のLSIチップ9を載置
した金属突起基板4は、搬送され、金属突起基板4を設
置するX−Yテーブル22上に設置される。次に金属突
起基板4上に設置されたLSIチップ9を真空コレット
11で吸着し、金属突起基板4上から持ち上げる。この
時Auバンプ5は、金属突起基板4から剥離し、LSI
チップ9のアルミ電極7に転写される。更に真空コレッ
ト11で吸着されたLSIチップ9を、回路基板15上
に設置し、接合する。
Next, FIG. 1C shows a step of transferring the Au bumps to the LSI chip, a second setting step of setting the LSI chip having the Au bumps on the circuit board, and a circuit of the LSI chip having the Au bumps. It shows a second joining step of joining to a substrate. The metal protruding substrate 4 on which the plurality of LSI chips 9 are mounted is transported and placed on the XY table 22 on which the metal protruding substrate 4 is placed. Next, the LSI chip 9 placed on the metal projection substrate 4 is sucked by the vacuum collet 11 and lifted from the metal projection substrate 4. At this time, the Au bump 5 is peeled off from the metal projection substrate 4,
It is transferred to the aluminum electrode 7 of the chip 9. Further, the LSI chip 9 adsorbed by the vacuum collet 11 is placed on the circuit board 15 and bonded.

【0029】図2は、図1(c)のAuバンプのLSI
チップへの転写工程と、Auバンプを有するLSIチッ
プを回路基板へ設置する第2の設置工程と、Auバンプ
を有するLSIチップを回路基板へ接合する第2の接合
工程の断面図であり、(a)及び(b)は、それぞれ搬
送されてきた金属突起基板4上の複数個のLSIチップ
のうち、1個目と2個目のLSIチップへのAuバンプ
の転写工程と、Auバンプを有するLSIチップを回路
基板へ設置する第2の設置工程を示したものである。
FIG. 2 is a schematic diagram of the Au bump LSI of FIG.
FIG. 6 is a cross-sectional view of a transfer step to a chip, a second installation step of installing an LSI chip having Au bumps on a circuit board, and a second bonding step of bonding an LSI chip having Au bumps to a circuit board, (a) and (b) have Au bump transfer process of transferring Au bumps to the first and second LSI chips of the plurality of LSI chips transferred on the metal protrusion substrate 4, respectively. 9 illustrates a second installation step of installing an LSI chip on a circuit board.

【0030】図2(a)において、搬送されてきた金属
突起基板4上の最初の1個目のLSIチップ23は、図
11に示した従来の突起電極を有する半導体素子の実装
方法と同様に、アライメントカメラ20によりLSIチ
ップ23と回路基板15との位置の画像認識により、L
SIチップ23と回路基板15との位置ずれ補正を行
い、その後回路基板15に設置される。なお、本実施例
ではアライメントカメラを用いて画像認識を行なってい
るが、画像によりLSIチップ23と回路基板15との
位置関係が把握できればよい。
In FIG. 2A, the first LSI chip 23 on the metal projection substrate 4 that has been transported is the same as the conventional mounting method for a semiconductor element having a projection electrode shown in FIG. , By the image recognition of the position of the LSI chip 23 and the circuit board 15 by the alignment camera 20
The positional deviation between the SI chip 23 and the circuit board 15 is corrected, and then the SI chip 23 and the circuit board 15 are mounted on the circuit board 15. Although image recognition is performed using an alignment camera in the present embodiment, it is sufficient if the positional relationship between the LSI chip 23 and the circuit board 15 can be grasped from the image.

【0031】次に図2(b)において、搬送されてきた
金属突起基板4上の2個目のLSIチップ24へのAu
バンプの転写工程と、Auバンプを有するLSIチップ
を回路基板へ設置する第2の設置工程について説明す
る。
Next, as shown in FIG. 2B, Au is transferred to the second LSI chip 24 on the metal projection substrate 4 that has been conveyed.
A bump transfer process and a second installation process for installing an LSI chip having Au bumps on a circuit board will be described.

【0032】LSIチップをチップトレーに収納せず、
第1の接合を行った後、金属突起基板上にLSIチップ
を載置したまま搬送しているため、LSIチップの位置
ずれは生じていない。従って、金属突起基板4上のAu
バンプ群の相対的な位置関係は金属突起基板製造時に精
度よく制御されていることに伴ってAuバンプ上のLS
Iチップの相対的な位置関係も精度よく制御されてい
る。そこで、1個目のLSIチップの回路基板上への設
置後の接合が終了すると、2個目のLSIチップ24
は、真空コレットP1の距離の移動、X−Yテーブル2
2は距離P2の移動、X−Yテーブル19は距離P3の
移動のみで、LSIチップを正確に回路基板上に設置す
ることができ、アラインメントカメラを用いた画像認識
による位置ずれ補正の工程は省略できる。また、3個目
以降のLSIチップについても、2個目のLSIチップ
24と同様にアライメントカメラ20を用いた画像認識
による位置ずれ補正工程を省略して回路基板15へ設置
することができる。
Without storing the LSI chip in the chip tray,
After the first bonding is performed, the LSI chip is conveyed while being mounted on the metal projection substrate, and therefore the LSI chip is not displaced. Therefore, Au on the metal projection substrate 4
The relative positional relationship of the bump groups is accurately controlled during the manufacture of the metal projection substrate, so that the LS on the Au bumps is controlled.
The relative positional relationship of the I chips is also controlled accurately. Therefore, when the joining after the installation of the first LSI chip on the circuit board is completed, the second LSI chip 24
Moves the distance of the vacuum collet P1, the XY table 2
2 is the movement of the distance P2, and the XY table 19 is only the movement of the distance P3, so that the LSI chip can be accurately installed on the circuit board, and the step of correcting the positional deviation by the image recognition using the alignment camera is omitted. it can. Further, with respect to the third and subsequent LSI chips, like the second LSI chip 24, the positional deviation correction process by image recognition using the alignment camera 20 can be omitted and installed on the circuit board 15.

【0033】以上述べてきた本発明第1の実施例におけ
る金属突起基板へのLSIチップの設置からLSIチッ
プの回路基板への接合までの工程を図3に示す。図3に
おいて、(a)は本発明第1の実施例の突起電極を有す
る半導体素子の実装方法における工程図、(b)は従来
の突起電極を有する半導体素子の実装方法における工程
図を示したものである。図3から明らかなように、従来
の工程では、金属突起基板へのLSIチップの設置から
LSIチップの回路基板への配線接合まで9工程必要で
あるが、本発明第1の実施例の突起電極を有する半導体
素子の実装方法によれば、2個目以降のLSIチップで
は6工程で済み、従来の工程に比べ3工程削減すること
ができる。
FIG. 3 shows the steps from the installation of the LSI chip on the metal projection substrate to the bonding of the LSI chip to the circuit board in the first embodiment of the present invention described above. In FIG. 3, (a) is a process chart of a method for mounting a semiconductor element having a protruding electrode according to the first embodiment of the present invention, and (b) is a process chart of a conventional method for mounting a semiconductor element having a protruding electrode. It is a thing. As is apparent from FIG. 3, in the conventional process, nine steps are required from installation of the LSI chip on the metal projection substrate to wiring connection of the LSI chip to the circuit board. However, the projection electrode of the first embodiment of the present invention is required. According to the method of mounting a semiconductor element having the above-mentioned method, 6 steps are required for the second and subsequent LSI chips, and 3 steps can be reduced as compared with the conventional steps.

【0034】具体的には、金属突起基板上の複数個のL
SIチップのうちの2個目以降のLSIチップに関し
て、本発明第1の実施例の突起電極を有する半導体素子
の実装方法では、従来の方法に比べ、真空コレットによ
り金属突起基板上のLSIチップを吸着し、Auバンプ
をLSIチップに転写させる転写工程(3)と、LSI
チップのトレーへの収納工程(4)の削減により、1個
のLSIチップ当たり約2秒、LSIチップのバンプと
回路基板の電極のアライメントカメラを用いた画像認識
による位置ずれ補正工程(7)の削減により、1個のL
SIチップ当たり約2〜10秒の時間の短縮ができ、転
写方式でバンプを形成した半導体素子の実装の大量生産
を考えた場合、著しい時間の短縮を達成することができ
る。
Specifically, a plurality of Ls on the metal projection substrate
With respect to the second and subsequent LSI chips of the SI chips, the semiconductor chip mounting method having the protruding electrodes of the first embodiment of the present invention uses an LSI chip on a metal protruding substrate by a vacuum collet as compared with the conventional method. A transfer process (3) of adsorbing and transferring Au bumps to an LSI chip, and
Due to the reduction of the step (4) of storing the chips in the tray, it takes about 2 seconds per LSI chip and the step (7) of correcting the positional deviation by the image recognition using the alignment camera of the bumps of the LSI chip and the electrodes of the circuit board. One L due to reduction
The time can be reduced to about 2 to 10 seconds per SI chip, and when considering mass production of mounting of semiconductor elements having bumps formed by the transfer method, a significant reduction in time can be achieved.

【0035】図4は、仮に1枚の金属突起基板に150
個のLSIチップを設置できるとした場合、この150
個のLSIチップを金属突起基板に設置してから回路基
板に接合するまでに要する時間を概算したものである。
図中工程の欄の数字は図3における工程の番号と一致し
ている。図4から明らかなように、従来では3610秒
要していたものが、2265秒でLSIチップを回路基
板に実装することができる。
FIG. 4 shows that one metal projection substrate has 150
If one LSI chip can be installed, this 150
This is an approximate calculation of the time required from the mounting of the individual LSI chips on the metal projection substrate to the bonding to the circuit board.
The numbers in the step column in the figure match the step numbers in FIG. As is clear from FIG. 4, the LSI chip can be mounted on the circuit board in 2265 seconds, which conventionally took 3610 seconds.

【0036】また、Auバンプ5との第1の接合工程が
終了したLSIチップ9をチップトレーに収納して搬送
していないため、特にLSIチップ9のチップトレー1
2への収納時に発生する図12に示すようなLSIチッ
プ9へのダスト付着などがなく、またAuバンプ5の変
形なども発生しなくなり、LSIチップ9を回路基板1
5に接合する際の接続不良や断線等の問題が発生しにく
くなる。したがって、非常に歩留まりの高い実装を行う
ことができる。
Further, since the LSI chip 9 which has undergone the first bonding step with the Au bumps 5 is not stored in the chip tray and is not transported, the chip tray 1 of the LSI chip 9 is particularly used.
The dust does not adhere to the LSI chip 9 as shown in FIG. 12 which occurs when the LSI chip 9 is housed in the circuit board 2, and the Au bumps 5 are not deformed.
Problems such as connection failure and disconnection at the time of joining to No. 5 are less likely to occur. Therefore, mounting with a very high yield can be performed.

【0037】しかしながら、上記第1の実施例の場合、
複数個のLSIチップ9が設置された金属突起基板4
は、そのまま次工程に搬送され、これによりLSIチッ
プ9を搬送するため、LSIチップ9が非常に大きい場
合にLSIチップ9の自重により、その搬送中に位置ず
れを起こす可能性が、従来の突起電極を有する半導体素
子の製造方法よりは、はるかに少ないものの、多少あ
り、位置ずれを起こしたLSIチップが隣接するLSI
チップに接触し、位置ずれを起こすLSIチップの数が
増加する恐れがある。
However, in the case of the first embodiment,
Metal protrusion board 4 on which a plurality of LSI chips 9 are installed
Is conveyed to the next step as it is, and the LSI chip 9 is conveyed thereby. Therefore, when the LSI chip 9 is very large, the weight of the LSI chip 9 may cause a positional deviation during the conveyance, which is a problem with the conventional projection. Although the number is much smaller than that of the method for manufacturing a semiconductor device having electrodes, some LSI chips are adjacent to each other and are misaligned.
There is a risk that the number of LSI chips that come into contact with the chips and cause a positional shift will increase.

【0038】(実施例2)以下、上記の金属突起基板搬
送中の位置ずれの防止を考慮した第2の実施例の突起電
極を有する半導体素子の実装方法について説明する。
(Embodiment 2) A method for mounting a semiconductor element having a protruding electrode according to a second embodiment of the present invention will be described below in consideration of prevention of displacement during the transportation of the metal protruding substrate.

【0039】図5は、金属突起基板と枠体の固定方法、
図6は、枠体を有する金属突起基板を用いた本発明第2
の実施例の突起電極を有する半導体素子の実装方法の概
略を示したものである。
FIG. 5 shows a method of fixing the metal projection substrate and the frame body,
FIG. 6 shows the second embodiment of the present invention using a metal projection substrate having a frame body.
3 is a schematic view showing a method of mounting a semiconductor element having a protruding electrode according to the embodiment of FIG.

【0040】図5(a)に示すように金属突起基板4の
Auバンプ5の形成領域に開口部25を有した枠体26
を準備する。枠体26は50μmから200μm程度の
厚みの金属あるいはプラスチックのシートをエッチング
や打ち抜きにより開口部25を形成し、作成する。
As shown in FIG. 5A, a frame 26 having an opening 25 in the Au bump 5 forming region of the metal projection substrate 4.
To prepare. The frame 26 is formed by etching or punching a metal or plastic sheet having a thickness of about 50 μm to 200 μm to form the opening 25.

【0041】次に図5(b)に示すように枠体26を開
口部25とAuバンプ5の形成領域が一致するように金
属突起基板4上に設置し固定する。固定の方法は枠体2
6の周辺を接着剤27で固定する。
Next, as shown in FIG. 5B, the frame 26 is placed and fixed on the metal projection substrate 4 so that the openings 25 and the formation regions of the Au bumps 5 coincide with each other. Frame 2 is fixed
The periphery of 6 is fixed with an adhesive 27.

【0042】以上のように形成した金属突起基板のAu
バンプ5をLSIチップ9に転写し、LSIチップ9を
金属突起基板4上に設置したまま次工程に搬送し、回路
基板14に接合する方法(図6)については、図1に示
した第1の実施例と同様である。
Au of the metal projection substrate formed as described above
Regarding the method (FIG. 6) of transferring the bumps 5 to the LSI chip 9 and carrying the LSI chip 9 to the next step with the LSI chip 9 installed on the metal projection substrate 4 and joining it to the circuit board 14, the first method shown in FIG. It is similar to the embodiment of.

【0043】金属突起基板4搬送の際、あらかじめ形成
した枠体26によりAuバンプ5を有するLSIチップ
9の金属突起基板4上での移動が制限されるため、もし
1個のLSIチップが位置ずれを起こしても、隣接する
LSIチップへの影響を最小限に押さえることができ
る。
When the metal projection substrate 4 is transported, the movement of the LSI chip 9 having the Au bumps 5 on the metal projection substrate 4 is restricted by the frame 26 formed in advance, so that if one LSI chip is displaced, Even if this occurs, the influence on the adjacent LSI chip can be suppressed to a minimum.

【0044】[0044]

【発明の効果】以上の説明から明らかなように、本発明
によれば、転写用の金属突起基板を転写後そのままチッ
プ収納容器として用いることにより、画像認識によるA
uバンプ5と回路基板15との位置ずれ補正工程の回数
を少なくできるなどの工程短縮ができ、転写後の金属突
起へのダスト付着や金属突起の変形を防止による生産性
の高い半導体素子への金属突起の形成を行うことができ
る。
As is apparent from the above description, according to the present invention, by using the metal projection substrate for transfer as a chip storage container as it is after transfer, the image recognition A
The steps such as reducing the number of steps for correcting the displacement between the u-bump 5 and the circuit board 15 can be shortened, and dust adhesion to the metal projections after transfer and deformation of the metal projections can be prevented, thereby improving the productivity of the semiconductor element. The metal protrusion can be formed.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明第1の実施例におけるLSIチップの金
属突起基板への設置工程からLSIチップの回路基板へ
の配線接続工程までの工程を示す斜視図
FIG. 1 is a perspective view showing a process from an installation process of an LSI chip to a metal protrusion substrate to a wiring connection process of an LSI chip to a circuit board in a first embodiment of the present invention.

【図2】本発明第1の実施例におけるLSIチップへの
バンプの転写工程及び、LSIチップの回路基板への配
線接合工程の断面図
FIG. 2 is a cross-sectional view of a bump transfer process to an LSI chip and a wiring bonding process of the LSI chip to a circuit board according to the first embodiment of the present invention.

【図3】本発明第1の実施例及び従来例の工程図FIG. 3 is a process diagram of the first embodiment of the present invention and a conventional example.

【図4】本発明及び従来例の工程に要する時間の比較図FIG. 4 is a comparison diagram of the time required for the steps of the present invention and the conventional example.

【図5】本発明第2の実施例における金属突起基板への
枠体の固定方法を示す斜視図
FIG. 5 is a perspective view showing a method of fixing a frame body to a metal projection substrate according to the second embodiment of the present invention.

【図6】本発明第2のの実施例におけるLSIチップの
金属突起基板への設置工程からLSIチップの回路基板
への配線接続工程までの工程を示す斜視図
FIG. 6 is a perspective view showing a process from a process of installing an LSI chip on a metal projection substrate to a process of connecting a wiring of an LSI chip to a circuit board in a second embodiment of the present invention.

【図7】従来例におけるのLSIチップの金属突起基板
への設置工程からLSIチップの回路基板への配線接続
工程までの工程を示す斜視図
FIG. 7 is a perspective view showing a process from a process of installing an LSI chip on a metal projection substrate to a process of connecting a wiring of an LSI chip to a circuit board in a conventional example.

【図8】バンプ転写用接合工程の断面図FIG. 8 is a sectional view of a bump transfer bonding process.

【図9】金属突起基板の形成工程を示す断面図FIG. 9 is a sectional view showing a process for forming a metal projection substrate.

【図10】本発明のLSIチップの回路基板への配線接
合工程の断面図
FIG. 10 is a sectional view of a wiring joining process of the LSI chip of the present invention to a circuit board.

【図11】従来例におけるLSIチップへのバンプの転
写工程及び、LSIチップの回路基板への配線接合工程
の断面図
FIG. 11 is a cross-sectional view of a bump transfer process to an LSI chip and a wiring bonding process of the LSI chip to a circuit board in a conventional example.

【図12】従来例の配線接合工程における不良発生を示
す図
FIG. 12 is a view showing a defect occurrence in a wiring joining process of a conventional example.

【符号の説明】[Explanation of symbols]

1 絶縁性基板 2 導電膜 3 絶縁膜 4 金属突起基板 5 Auバンプ 6 真空コレット 7 LSIチップの電極 8 加圧ツール 9 LSIチップ 10 保護膜 11 真空コレット 12 チップトレー 13 ポケット 14 チップトレーを設置するX−Yテーブル 15 回路基板 16 導体配線 17 絶縁膜の開口部 18 光硬化性樹脂 19 回路基板を設置するX−Yテーブル 20 アライメントカメラ 21 ダスト 22 金属突起基板を設置するX−Yテーブル 23 LSIチップ 24 LSIチップ 25 枠体の開口部 26 枠体 27 接着剤 1 Insulating Substrate 2 Conductive Film 3 Insulating Film 4 Metal Protrusion Substrate 5 Au Bump 6 Vacuum Collet 7 LSI Chip Electrode 8 Pressurizing Tool 9 LSI Chip 10 Protective Film 11 Vacuum Collet 12 Chip Tray 13 Pocket 14 Installing Chip Tray X -Y table 15 Circuit board 16 Conductor wiring 17 Insulation film opening 18 Photo-curable resin 19 XY table for installing circuit board 20 Alignment camera 21 Dust 22 XY table for installing metal projection substrate 23 LSI chip 24 LSI chip 25 Opening of frame 26 Frame 27 Adhesive

Claims (5)

【特許請求の範囲】[Claims] 【請求項1】複数個の金属突起が接合固定された金属突
起基板に半導体素子を設置する第1の設置工程と、少な
くとも加圧を行って前記半導体素子の電極と前記金属突
起を接合固定し、前記金属突起と前記半導体素子の電極
との接合強度を前記金属突起と前記金属突起基板との接
合強度よりも大きくする第1の接合工程と、前記第1の
接合工程で複数個の前記半導体素子が前記金属突起を介
して接合固定された前記金属突起基板を搬送する金属突
起基板搬送工程と、前記金属突起基板搬送工程により搬
送された前記金属突起基板から前記金属突起が接合され
た前記半導体素子を剥離させ、前記金属突起を前記半導
体素子に転写する金属突起転写工程と、前記金属突起が
転写された前記半導体素子を回路基板上に設置する第2
の設置工程と、前記金属突起が転写された前記半導体素
子を回路基板上に接合する第2の接合工程とを備えてな
る突起電極を有する半導体素子の実装方法。
1. A first installation step of installing a semiconductor element on a metal projection substrate having a plurality of metal projections bonded and fixed, and at least applying pressure to bond and fix the electrodes of the semiconductor element and the metal projections. A first bonding step of making the bonding strength between the metal projection and the electrode of the semiconductor element larger than the bonding strength between the metal projection and the metal projection substrate; and a plurality of the semiconductors in the first bonding step. A metal projection substrate carrying step of carrying the metal projection substrate on which an element is joined and fixed via the metal projection, and the semiconductor having the metal projection joined from the metal projection substrate carried by the metal projection substrate carrying step A metal projection transferring step of peeling the element and transferring the metal projection to the semiconductor element; and a step of placing the semiconductor element having the metal projection transferred thereon on a circuit board.
And a second bonding step of bonding the semiconductor element on which the metal projection is transferred onto a circuit board, the method for mounting a semiconductor element having a protruding electrode.
【請求項2】複数個の金属突起が接合固定された金属突
起基板に半導体素子を設置する第1の設置工程と、少な
くとも加圧を行って前記半導体素子の電極と前記金属突
起を接合固定し、前記金属突起と前記半導体素子の電極
との接合強度を前記金属突起と前記金属突起基板との接
合強度よりも大きくする第1の接合工程と、前記第1の
接合工程で複数個の前記半導体素子が前記金属突起を介
して接合固定された前記金属突起基板を搬送する金属突
起基板搬送工程と、前記金属突起基板搬送工程により搬
送された前記金属突起基板から前記金属突起が接合され
た前記半導体素子を剥離させ、前記金属突起を前記半導
体素子に転写する金属突起転写工程と、前記金属突起が
転写された前記半導体素子を回路基板上に設置する第2
の設置工程と、前記金属突起が転写された前記半導体素
子を回路基板上に接合する第2の接合工程とを備え、前
記金属突起基板搬送工程により搬送された前記金属突起
基板に接合固定されている複数個の前記半導体素子のう
ちの特定の1個の半導体素子は、前記第2の設置工程の
際に、設置されるべき回路基板との位置ずれ補正を画像
認識により行い、前記金属突起基板搬送工程により搬送
された前記金属突起基板に接合固定されている複数個の
前記半導体素子のうちの前記特定の1個の半導体素子以
外の半導体素子は、前記第2の設置工程を前記金属突起
基板上の複数個の前記半導体素子の正確な相対的位置関
係を基に行うことを特徴とする突起電極を有する半導体
素子の実装方法。
2. A first installation step of installing a semiconductor element on a metal projection substrate having a plurality of metal projections bonded and fixed, and at least applying pressure to bond and fix the electrodes of the semiconductor element and the metal projections. A first bonding step of making the bonding strength between the metal projection and the electrode of the semiconductor element larger than the bonding strength between the metal projection and the metal projection substrate; and a plurality of the semiconductors in the first bonding step. A metal projection substrate carrying step of carrying the metal projection substrate on which an element is joined and fixed via the metal projection, and the semiconductor having the metal projection joined from the metal projection substrate carried by the metal projection substrate carrying step A metal projection transferring step of peeling the element and transferring the metal projection to the semiconductor element; and a step of placing the semiconductor element having the metal projection transferred thereon on a circuit board.
And a second joining step of joining the semiconductor element on which the metal protrusions are transferred onto a circuit board, wherein the semiconductor element is joined and fixed to the metal protrusion substrate conveyed by the metal protrusion substrate conveying step. A specific one semiconductor element of the plurality of semiconductor elements is subjected to positional deviation correction with the circuit board to be installed by image recognition in the second installation step, and the metal projection substrate A semiconductor device other than the specific one semiconductor device among the plurality of semiconductor devices bonded and fixed to the metal protrusion substrate transferred in the transfer process is subjected to the second installation process in the metal protrusion substrate. A method of mounting a semiconductor device having a protruding electrode, which is performed based on an accurate relative positional relationship of the plurality of semiconductor devices.
【請求項3】金属突起基板が、1個の半導体素子の電極
に対応する金属突起群を各々囲む枠体を有することを特
徴とする請求項1又は2記載の突起電極を有する半導体
素子の実装方法。
3. The mounting of a semiconductor element having a bump electrode according to claim 1, wherein the metal bump substrate has a frame body surrounding each metal bump group corresponding to an electrode of one semiconductor element. Method.
【請求項4】金属突起の材質が、第1の接合工程の際に
溶融しない金属であることを特徴とする請求項1、2又
は3記載の突起電極を有する半導体素子の実装方法。
4. The method for mounting a semiconductor element having a bump electrode according to claim 1, 2 or 3, wherein the material of the metal projection is a metal that does not melt during the first bonding step.
【請求項5】金属突起の材質が、Auであることを特徴
とする請求項1、2又は3記載の突起電極を有する半導
体素子の実装方法。
5. The method of mounting a semiconductor element having a bump electrode according to claim 1, 2 or 3, wherein the material of the metal bump is Au.
JP13440693A 1992-06-18 1993-06-04 Method of mounting semiconductor element having bump electrode Expired - Fee Related JP2797900B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13440693A JP2797900B2 (en) 1992-06-18 1993-06-04 Method of mounting semiconductor element having bump electrode

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP15916692 1992-06-18
JP4-159166 1992-06-18
JP13440693A JP2797900B2 (en) 1992-06-18 1993-06-04 Method of mounting semiconductor element having bump electrode

Publications (2)

Publication Number Publication Date
JPH0669283A true JPH0669283A (en) 1994-03-11
JP2797900B2 JP2797900B2 (en) 1998-09-17

Family

ID=26468533

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13440693A Expired - Fee Related JP2797900B2 (en) 1992-06-18 1993-06-04 Method of mounting semiconductor element having bump electrode

Country Status (1)

Country Link
JP (1) JP2797900B2 (en)

Also Published As

Publication number Publication date
JP2797900B2 (en) 1998-09-17

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