JPH0668859B2 - Synchronous control device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a synchronous control device applied to synchronously operate a VTR and a PCM tape recorder during editing.

[Outline of Invention]

The present invention, in a synchronization control device for synchronizing a PCM tape recorder and a VTR, forms a word clock that synchronizes with a reference signal and corrects a synchronization error between the two, and this word clock is applied to the PCM tape recorder. By supplying the master clock as the master clock, it is possible to prevent the reproduced sound of the PCM tape recorder from disappearing or the noise from being generated in the transient state until the synchronization state is reached.

[Prior Art] As one method of creating a video and audio program, a video signal and an audio signal recorded by a VTR are separately recorded on another VTR and a PCM tape recorder together with a time code. There is one that edits the sound (addition of sound effects, BGM, etc.) and records it again on the VTR. The VTR and PCM tape recorder were operating synchronously when editing this audio.

Conventionally, VTR and PCM tape recorder are synchronized with each other by synchronizing them with a reference signal (frame frequency synchronizing signal, etc.),
The synchronization error at this time is detected from the reproduction time code of both, and the capstan servo of the PCM tape recorder is controlled so as to correct the synchronization error. As another synchronization method, as described in Japanese Patent Application No. 60-187727 proposed previously, a word clock is modulated by a detected synchronization error, and this modulated word clock is used. By supplying the PCM tape recorder to the PCM tape recorder, the master clock of the PCM tape recorder is changed, and therefore the reproduction speed and the sampling frequency for data processing are changed to reproduce the reproduction data correctly.

[Problems to be solved by the invention]

In the conventional synchronous control system that controls the capstan servo circuit, the tape speed deviates from the normal one in the transient state until the synchronous state is reached, so the sampling frequency of the reproduced data deviates, and the reproduced data Becomes error data, and the reproduced sound is temporarily muted.
The fact that no sound is produced during editing causes a problem in that the editing work is difficult in terms of lip sync.

Even when the word clock modulated by the synchronization error is supplied to the PCM tape recorder, noise may occur when the playback speed of the PCM tape recorder is restored to the normal one after reaching the synchronization state, or the synchronization state may be out of sync. However, it has the same drawbacks as described above.

Therefore, the object of the present invention is to reproduce a reproduced sound in a transient state in which a synchronization deviation between an information signal reproducing device such as a VTR and a PCM tape recorder which are synchronously operated by a word clock of a sampling frequency and an asynchronous reference signal is corrected. It is an object of the present invention to provide a synchronous control device that solves the problems of disappearance and noise generation.

[Means for solving problems]

The present invention has a synchronizer 10 for detecting an error signal from reproduction address information of a PCM tape recorder 3 and reproduction address information of an information signal reproducing device, for example, a VTR 12, and a PCM tape recorder having an external input terminal of a clock defining a sampling frequency. In the synchronization control device for synchronizing both the clock 3 having the sampling frequency and the information signal reproducing device 12 synchronized with the asynchronous reference signal, a first control for forming a clock having a predetermined frequency synchronized with the reference signal. An external input terminal of the PCM tape recorder 3 forms a word clock whose frequency is controlled by an error signal, which is synchronized with the first PLL circuit 23 and a clock of a predetermined frequency from the first PLL circuit 23. And a second PLL circuit 28 for outputting to the synchronous control device.

[Action]

The first PLL circuit 23 forms a word clock having a predetermined frequency, for example, a sampling frequency, which is synchronized with the reference signal. The word clock and the synchronization error voltage are supplied to the second PLL circuit 28, and the second PLL circuit 28
A word clock having a variable frequency is formed by the synchronization error voltage. The word clock that corrects the synchronization error between the VTR 12 and the PCM tape recorder 3 is the second PLL circuit 28.
Generated by. Since the PCM tape recorder 3 operates in synchronization with the word clock, the reproduced data can be reproduced correctly. When the synchronization error is corrected, the tape speed of the PCM tape recorder 3 is returned to the steady speed. In this case, since the word clock at the time of correction is synchronized with the reference signal, it is possible to prevent noise from occurring and the loss of the synchronization state when returning to the steady speed.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of a synchronous control device to which the present invention is applied, and FIG. 2 shows the configuration of the entire system of this embodiment. However, in FIG. 2, the system of the video signal and the audio signal is omitted, and only the control signal system is shown.

In FIG. 2, 1 is one of standard bus systems.
A bus line using an IEEE-488 bus (also called GP-IB or HP-IB) is shown. The bus line 1 is composed of 8 data lines, 3 handshake lines, and 5 control lines.

A remote controller 2 on the master side and a remote controller 5 on the slave side are coupled to the bus line 1. The remote controller 2 is a fixed head type multi-channel PC (48 channels, for example) on the master side.
The M tape recorder 3 is connected via the remote signal cable 4. A PCM tape recorder 6 on the slave side is connected to the remote controller 5 via a remote signal cable 7.

In addition, the microcomputer system 8 is the bus line 1
It is connected to the. The microcomputer system 8 is provided for displaying the current remote status and programming the control by the remote controllers 2 and 5. Further, the interface device 9 is coupled to the bus line 1. The interface device 9 is a device for mutually converting the parallel remote control interface and the bus line 1. The interface device 9 and the synchronizer 10 are connected, and a remote control signal is supplied via a remote signal cable 11.

Reference numeral 12 denotes a rotary head type VTR, and address information reproduced by the VTR 12, for example, SMPTE time code, is supplied to the synchronizer 10 via a cable 13. Synchronizer
Remote control signals from 10 are provided via cable 14. The synchronizer 10 has a PC on the master side.
The time code reproduced by the M tape recorder 3 is supplied through the cable 15.

The PCM tape recorder 3 and the VTR 12 are supplied with a reference signal, for example, a composite synchronizing signal, from the terminal 16, and both devices are synchronized with the reference signal. The synchronizer 10 detects a synchronization deviation between the PCM tape recorder 3 and the VTR 12 based on the reproduction time code, and generates a synchronization error voltage proportional to this deviation. This sync error voltage is supplied to the sync control device 18 to which the present invention is applied via the cable 17.

A reference signal from the terminal 16 is supplied to the synchronization control device 18. The synchronization control device 18 generates a word clock which is synchronized with the reference signal and whose frequency is controlled by the synchronization error voltage as described later. This word clock is supplied to the clock input terminal of the PCM tape recorder 3 via the cable 19. The word clock output from the master side PCM tape recorder 3 is supplied to the slave side PCM tape recorder 6 by the remote controllers 2 and 5.
Is supplied via. Therefore, the PCM tape recorders 3 and 5 are both synchronized with the VTR 12.

The remote control system shown in FIG. 2 transmits and receives control signals between the remote controllers 2 and 5 and other devices via the bus line 1 and requires real-time transmission of time codes, reference signals, etc. Are transmitted on a dedicated line other than the bus line 1. Devices such as the remote controllers 2 and 3 connected to the bus line 1 are connected to the GP in order to configure a network system conforming to the standard.
It has a network system control consisting of an IB driver, a network node circuit, and a network circuit.

The synchronization control device 18 will be described with reference to FIG. The reference signal from the terminal 16 is supplied to the sync extraction circuit 21. This reference signal is a composite synchronizing signal of the NTSC color television system, and the reference signal (pulse waveform) of 29.97 Hz which is equal to the frame frequency by the sync extraction circuit 21.
Is extracted. This reference signal is passed through the switch circuit 22
It is supplied to the PLL circuit 23. As reference signal, 30Hz (frame frequency of monochrome television signal), 25Hz (CCIR
It is also possible to synchronize using the frame frequency of the system.

As the other input of the switch circuit 22, a reference signal other than the video signal system, that is, 24 Hz (synchronization signal during film reproduction), 50 Hz,
60Hz (power frequency), 96Hz (external sprocket frequency)
Etc. pulse signals are supplied. The output signal of the switch circuit 22 is supplied to the PLL circuit 23. The PLL circuit 23 generates a word clock having a sampling frequency synchronized with the reference signal. Either 44.1 kHz or 48 kHz can be used as the sampling frequency. The detection signal from the sampling frequency detection circuit 45 is supplied to the PLL circuit 23 from the terminal 25, and which sampling frequency of the word clock is generated is specified.

The word clock from the PLL circuit 23 is supplied to the PLL circuit 28 via the switch circuit 26. The external word clock from the terminal 27 is supplied as the other input of the switch circuit 26. Pitch information is supplied to the PLL circuit 28 from a terminal 29. The PLL circuit 28 forms a word clock whose frequency is controlled by the pitch information in synchronization with the word clock and outputs the word clock to the output terminal 30. This word clock is sent to the clock input terminal of the PCM tape recorder 3 on the master side as described above.

The pitch information is formed based on the synchronization error voltage formed by the synchronizer 10. The synchronization error voltage is supplied to the terminal indicated by 31, and the synchronization error voltage is supplied to the low-pass filter 34 via the switch circuit 32. The other input voltage of the switch circuit 32 is supplied from the terminal 33. The level of the other voltage changes in response to, for example, manual operation.

Since the conversion of the sync error voltage into the pitch information is performed by software control, the sync error voltage is converted into a digital signal by the A / D converter 35. In FIG. 1, the part surrounded by the one-dot chain line represents the part under software control. This software control is performed by the network system controller 40. The network system controller 40 is connected to the bus line 1.

The digital error signal from the A / D converter 35 is supplied to the digital filter 41, and unnecessary signals are removed. The output signal of the digital filter 41 is supplied to the conversion circuit 42. The conversion circuit 42 is a circuit for converting the voltage into pitch information, and determines the maximum value of the pitch information by the limiter action. A sampling clock of, for example, 1 kHz is supplied from the terminal 36 to the A / D converter 35, the digital filter 41, and the conversion circuit 42. The pitch information indicates what percentage the sampling frequency is changed with respect to the reference value, and its maximum value is limited to ± 12.5%, for example.

The pitch information output from the conversion circuit 42 is supplied to the filter circuit 44 via the output controller 43. The filter circuit 44 controls the rising characteristic or the falling characteristic when the pitch information changes. That is, this is to limit the rate of change of pitch information to a predetermined value or less. When the unit of recorded data of the PCM tape recorder is called one sector, the rate of change of pitch information is suppressed within 0.1% per sector.

The output controller 43 controls the output of pitch information according to the output enable signal from the network system control 40. After the synchronization error is corrected,
When the stop operation is performed, the output of pitch information is turned off. The filter circuit 44 can be supplied with digital synchronization error information from the network system control 40, in addition to the pitch information formed from the synchronization error voltage. The pitch information output from the filter circuit 44 is supplied from the terminal 29 to the PLL circuit 28.

Further, the sampling frequency detection circuit 45 detects whether the sampling frequency is 44.1 kHz or 48 kHz when the power is turned on, and the detection result is supplied from the terminal 25 to the PLL circuit 23.

FIG. 3 shows an example of the configuration of the PLL circuit 28. PLL circuit 28
Is composed of a phase comparison circuit 52, a low pass filter 53, a VCO 54, a variable frequency dividing circuit 55 and a frequency dividing circuit 56. The word clock synchronized with the reference signal and the output signal of the variable frequency dividing circuit 55 are supplied from the terminal 51 to the phase comparison circuit 52 by the PLL circuit 23 in the preceding stage. The frequency dividing ratio (1 / N) of the variable frequency dividing circuit 55 is
Controlled by pitch information from terminal 29. For example (N
= 250), a word clock equal to the sampling frequency is obtained at the output terminal 57 of the frequency dividing circuit 56. Divide ratio N
When it is larger than 250, the frequency of the output word clock becomes high, and conversely, when the frequency division ratio N is smaller than 250, the frequency of the outputted word clock becomes low.

As shown in FIG. 4, the frequency of the word clock formed by the PLL circuit 28 changes within a range of ± 12.5% (F _{sh to} F _st ) around the normal sampling frequency Fs.
In case of (Fs = 48kHz), it becomes (F _sh = 54kHz),
(F _st = 42 kHz). In case of (Fs = 44.1kHz),
(F _sh = 49.6125 kHz) and (F _st = 38.5875 kHz). The PCM tape recorder 3 operates using this word clock as a master clock, and the tape speed changes in proportion to the word clock. The sampling frequency for data processing in the PCM tape recorder 3 also changes at the same rate, the reproduced data is processed as error data, and the muting operation is not performed.

In the above-described embodiment of the present invention, when the PCM tape recorder 3 and the VTR 12 are synchronized with the reference signal from the terminal 16, the word clock modulated according to the synchronization error voltage causes
When the synchronization error is corrected and the synchronization error is corrected, the PCM
The tape speed of the tape recorder is returned to the steady speed.

In the above-described embodiment, the PLL circuit 23 forms the word clock. However, in this PLL circuit 23,
A signal synchronized with a reference signal having a predetermined frequency other than the sampling frequency may be formed. In addition, this invention is a VTR
It can also be applied to a case where an information signal reproducing device such as an analog multi-track tape recorder or a film reproducing device other than the above is synchronized with a PCM tape recorder.

〔The invention's effect〕

According to this invention, by supplying to the PCM tape recorder a word clock that is synchronized with an information signal reproducing device such as a VTR, and the frequency of which is varied by the synchronization error voltage,
It is possible to prevent the reproduced voice from disappearing or noise from being generated in a transient state. Therefore, it is possible to avoid inconvenience such as difficulty in lip-sync during editing.

[Brief description of drawings]

1 is a block diagram of an embodiment of the present invention, FIG. 2 is a block diagram of an example of a remote control system to which the present invention is applicable, FIG. 3 is a block diagram of an example of a PLL circuit, and FIG. 4 is a word clock. 6 is a schematic diagram for explaining the frequency control of FIG. Description of main symbols in the drawings 1: Bus line, 2, 5: Remote controller, 3, 6: PCM tape recorder, 10: Synchronizer, 12: VTR, 18: Synchronous controller, 23, 28: PLL circuit.

Claims (1)

[Claims] 1. An external input terminal of a clock having means for detecting an error signal from reproduction address information of a PCM tape recorder and reproduction address information of an information signal reproducing device, and defining a tape speed and a sampling frequency for data processing. In a synchronization control device for synchronizing both the PCM tape recorder having the above and the information signal reproducing device synchronized by the reference signal asynchronous with the clock, a clock of a predetermined frequency synchronized with the reference signal is formed. To generate a word clock synchronized with the clock having the predetermined frequency from the first clock generating means and having a frequency controlled by the error signal. A second clock generating means for outputting to the external input terminal of the PCM tape recorder, and Synchronous control apparatus according to claim.