JPS61114657A - Device for generating time code synchronously with television signal - Google Patents

Abstract

PURPOSE:To obtain a time code with other standard system synchronously with a time code used for a television signal of a different standard system by generating the 2nd time code corresponding to the 1st time code when frames are coincident at a period being a common multiple of the period of the 1st and 2nd frame signals. CONSTITUTION:Through the utilization of the facts that frame signals of the PAL and NTSC systems are coincident at each frame of 5:6, an SMPTE frame signal at each 6th frame is detected at an SMPTE time code generator 6 by using a switch signal. Then an EBU time code data as soon as the said signal is read is read by the SMPTE time code generator 6, from which an SMPTE time code corresponding to the data is generated. Simultaneously, the periods of the EBU time code and the SMPTE time code are obtained by using a signal synchronously with a synchronizing signal generator 3.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) This invention relates to a synchronized time code generator used in a synchronizer for synchronizing recording and reproduction of VTRs using different television standard systems, such as PAL and NTSC systems. .

(Prior art) NTSC system and PA as television standard systems
There is an L/SECAM system, but there are NTSC system VTRs.
There are cases where it is desired to synchronize recording or playback between a PAL/SECAM VTR and a PAL/SECAM VTR.

For example, a digital audio system uses a VTR to record audio signals on magnetic tape in a digital format.The digital audio system converts the digitized signal into a video signal-compliant format and records and plays it back using an existing VTR. Specifications are set taking into consideration standard methods.

The digital audio systems that use VTRs that are now available in the world were developed in countries that use the NTSC system, so these systems use VTRs that use the NTSC system. If you are trying to record or play back on a VTR, the video will be recorded on the VTR. 11 television standards.

In this case, in areas where the NTSC system is used, the digital audio system and the VTR used for video are of the same system, so it is easy to operate them in synchronization with each other using time codes.

However, in areas where the PAL/SECAM system is used, the VTRs used for video recording and playback are naturally of the PAL/SECAM system, and there is a difference between the NTSC system VTRs used in digital audio systems and the PAL/SECAM system VTRs. Since the time codes were different, synchronized operation was not possible as it was, but the applicant first proposed a device that would make this possible in a patent application dated October 25, 1980 [Television signal synchronization device]. However, the previously proposed device requires a synchronized time code generator to obtain time code of one standard format that is synchronized with the time code used for one of the television signals of different standard formats. Ta.

(Purpose of the Invention) The present invention is for obtaining a time code of a standard format that is synchronized with the time code used for one of the television signals of different standard formats used in the above-mentioned television signal synchronization device. be.

(Means for Solving the Problems) In order to achieve the above object, the present invention provides a first time code used in a VTR of a first television standard system and a second time code that is different from the first television standard system. In a television signal synchronized time code generation device that generates a second time code used in a VTR of a television standard system, a first frame signal of the first television standard system and a second frame signal of the second television standard system are provided. A second time code corresponding to the first time code is generated at a time when the frames coincide with each other with a period that is a common multiple of the period of the first frame signal and the period of the second frame signal. Television signal characterized by generating time code □Provides a synchronous time code generator.

(Function) The NTSC frame signal input to the SMPTE time code generator 6 and the time code data and switch signal output from the EBLI time code reader 5 are all synchronized with the synchronization signal output from the synchronization signal generator 3. There is.

In the SMPTE time code generator 6, the SMPTE
The NTSC frame signal input to the time code generator 6 is detected by a switch signal every six frames of the SMPTE frame signal.

And, the SMPTE time code generator 6 is SMPTE
The EBU time code data at the moment when every six frames of the frame signal is detected is read, and the corresponding SMPTE time code is generated.

(Embodiment) An embodiment of the television signal synchronized time code generator according to the present invention, which is a television signal synchronized time code for synchronously operating VTRs of different systems such as the PAL system and the NTSC system. The generator will be explained below.

FIG. 1 is a block system diagram of an embodiment of the television signal synchronized time code generator of the present invention, FIG. 2 is a timing chart, and (A) is a waveform diagram showing the SMPTE time code and frame signal a. (B) is a waveform diagram showing the EBU time code and frame signal, (C) is a waveform diagram showing switch signal C that controls switch 7, and (D) is a waveform diagram showing signal d passing through switch 7. FIG.

The EBU time code used in PAL VTRs and the SMPTE time code used in NTSC VTRs have the same address up to 8 minutes and 1 second.
Since the number of frames is 25 frames per second in the PAL system and 30 frames per second in the NTSC system, the frame address is EBU.
Time code (PAL system) numbers 0 to 24, SMPT
E time code (NTSC system) has numbers 0 to 29, and both systems are different.

However, EBU frame address number 0 and SMPTE
The time coincides with frame address number 0, and it is also 5.
The times of numbers 6 and 6, 10 and 12, 15 and 18, and 20 and 24 also match, respectively, and the frames of both types match at a ratio of 5:6.

The situation is shown in Fig. 2 (A) and (B).

The present invention was made by paying attention to the fact that there is a time when both types of frames coincide.

In FIG. 1, 1 is a PAL type VTR.

2 is an NTSC system VTR, and each VTR has a PAL address code used for tape editing, etc.
The system VTR1 is a model that can use EBU time code, and the NTSC system VTR2 is a model that can use SMPTE time code.

The synchronizing signal generator 3 outputs a 50H2 video signal, and the output signal is synchronously coupled to the VTR 1 and the signal generator 4. The VTRI outputs an EBU time code synchronously combined with the output signal of the synchronization signal generator 3, and the output signal is supplied to the EBU time code reader 5.

The time code reader 5 detects the time code data such as hour 1 minute 2 seconds and frames from the EBU timed, and the frame signals of numbers 4, 9, 14, 19, and 24 in the PAL system, and reads the next frame 5, 10.゜15.20. The time code data and the switch signal are outputted to the SMP T'E time code generator 6, and the time code data and the switch signal are output to the switch circuit 7. are each supplied with a switch signal.

On the other hand, the signal generator 4 outputs two signals: a pulse signal of 25H2 synchronously combined with the synchronization signal generator 3, and a pulse signal of 3,087 MHz, which is a multiplication frequency of the 25H2 pulse signal and a multiplication frequency of 30H2, 25) The 1A pulse signal is supplied to the switch circuit 7, and the 3.087 MHz pulse signal is supplied to the NTSC frame signal generator 8 as a clock signal.

The switch circuit 7 receives a 25Hz pulse signal 911, which is supplied from the signal generator 4 under the control of the switch signal.
91 directions. . , 5.10.15, yo. a
Pass the pulse at the same time as the frame signal of ゛ (
The waveform d) in FIG. 2(D) is supplied to the NTSC frame signal generator 8 to obtain synchronization between the PAL frame signal and the NTSC frame signal at this moment.

The NTSC frame signal generator 8 generates a pulse signal (PAL) output from the switch circuit 7 from eight 3.087M signals.
An NTSC frame signal is generated which is synchronously combined every 6 frame signals (every 5 frame signals), and the frame signal is supplied to the SMPTE time code generator 6.

This is the timing chart diagram (A) in FIG.

As shown in (B), PAL frame signal and NT
This method takes advantage of the fact that the frame signals of the SC system match every 526 frames.

In the SMPTE time code generator 6, signals of every six frames of the SMPTE frame signal are detected by the switch signal.

Then, the SMPTE time code generator 6 reads the EBU time code data at the moment when the signal is detected and generates an SMPTE time code corresponding to the EBU time code data.

At the same time, thereafter, synchronization between the ECU time code and the SMPTE time code is obtained by a signal synchronized with the synchronization signal generator 3.

As a specific example, in FIG. 2, if the 5th frame signal of the EBU time code is detected by the switch signal, the EBLI time code at that time is 811M.
If the minutes are 8 seconds and 5 frames, the corresponding SMPTE
The time code starts as H hours minutes S seconds 6 frames.

The starting frame of SMPTE time code is E.
0°5, 12. which matches the BU timecode frame.
The same thing applies to any number 18 and 24, and if synchronization is achieved at one point, the NTSC frame signal, EBU time code data, and switch signal input to the SMPTE time code generator 6 all generate synchronized signals. Since the time code is synchronized with the synchronization signal output from the device 3, the SMPTE time code and the EBU time code can be synchronized from now on.

Note that the signal generator 9 is an SMPTE time code generator 6.
This is a signal source for modulation.

SMPTE output from SMPTE time code generator 6
The time code is supplied to an output terminal 10 and a synchronizer 11.

The output terminal 10 is used when it is desired to synchronously control other NTSC system equipment, and the synchronizer 11 is a device for operating the VTR 2 in the same manner as the SMPTE time code.

12 is a PCM processor, and is an adapter for recording or reproducing digital audio using the VTR 2.

In this example, SMPTE synchronized with EBU time code
Although the description has been made regarding a device that generates a time code, it is also possible to use a device that obtains a reverse synchronized time code.

FIG. 3 shows a more specific block system diagram of the main part of FIG. 1, which is an embodiment of the present invention.

In the figure, the same block numbers as those in FIG. 1 correspond to those in FIG. 1, and descriptions of their effects will be omitted.

Reference numerals 13, 13' and 14 are input terminals, and the output signals of the signal generator 4 are supplied to the input terminals 13 and 13', and the EBU time code from the VTR 1 is supplied to the input terminal 14, respectively. 15 to 11 are output terminals, and 15 is a PCM
The processor 12 is the synchronizer 11, and the synchronizer 11 is the 16 processor.
A synchronizer 11 and a device to be operated synchronously are connected to 7, respectively.

18 is a CPU that controls this embodiment; 19;
is a timing circuit for the operation of the CPU 18, 2o is a ROM in which the program is written, and 21 is a timing circuit for the operation of the CPU 18.
22 is an input buffer circuit; 23 is an input buffer circuit;
is a synchronization latch, 24 is a timing signal generator, 25~
28 is an output buffer circuit, 29 is a monitoring circuit that monitors the synchronization of PAL and NTSC frames, 30G, tsMPT
E time code signal modulation circuit; 31 indicates a display circuit for displaying time code;

FIG. 4 shows a flowchart of the operation of CPU 18 that controls SMPTE time code generator 68.

When the television signal synchronized time code generator starts operating, the CPU 18 initializes the CPU (step 21), reads data from the E8U time code reader 5 (step 22), and determines that the data is, for example, 3.
It is determined whether frames are consecutive and correct data is input (step 23).

This is to check whether the VTR1 (PAL system) is operating or not, and if 3 consecutive frames of data are input, it is assumed that the VTR1 is operating (Y in step 23). Reads the EBU time code data (step 24), and if the frame number of the EBU time code is 4.9, 14°19 or 24 (Y in step 25), the CPU 18 reads the EBtJ frame input to the switch circuit 7. 5, 10, which is the next frame in the signal. Figure 2 (corresponding to number Is or 0)
The signal of waveform d in D) is allowed to pass (step 26).

5fvlPT corresponding to the E8LI time code at that time
The CPU 18 calculates the E time code data, stores it internally, and loads it into the external boat (step 21).
Since frame synchronization has been achieved at that point, the frame signal input to the switch circuit 7 is no longer allowed to pass (step 28).

Next, an OK flag is supplied to the synchronizer 11 as an indicator that the EBU time code is continuous and normal and that a synchronized SMPTE time code has been obtained (step 29).

Then, it is determined whether an interrupt load signal for the next SMPTE frame has arrived (step 30).

If the next interrupt load signal comes, add one frame to the SMPTE time code data and send CPU 1
8 reads the data and loads it into the SMPTE time code signal modulation circuit (step 31).

At the same time, it is determined whether the EBU time code data is, for example, seven consecutive frames (step 32).

If they are continuous, add the number of frames one after another, and
If the PTE time code is continuously generated and the EBLJ time code is interrupted after seven consecutive frames (N in step 32), the OK flag to the synchronizer 11 is released (step 33), and the process returns to the initial state at the same time.

(Effects of the Invention) According to the present invention, in two different television standard systems, the time code of the other standard can be synchronized more quickly and reliably than the television signal and time code of one standard. It is possible to obtain

[Brief explanation of drawings]

Fig. 1 is a block system diagram of an embodiment of the television signal synchronized time code generator of the present invention, and Fig. 2 is a timing chart, in which (A) shows the SMPTE time code and frame signal waveform a, and (B) shows the EBU. Time code and frame signal waveforms b and (C) show a switch signal 2 waveform C1 that controls the switch 7. (D) shows a PAL frame signal waveform d that passes through the switch 7, respectively. FIG. 3 shows a more specific block system diagram of FIG. 1, and FIG. 4 shows a flowchart of the operation of the CPU in FIG. 3. 1.2...VTR13...Synchronization signal generator, 4.9
...Signal generator, 5...EBLJ time code reader, 6...SMP
TE time code generator, 7... Switch circuit, 8... NTSC frame signal generator, 1o... Output terminal, 11... Synchronizer, 12... PGM processor.

Claims (1)

[Claims] Television signal synchronization for generating a first time code used in a VTR of a first television standard system and a second time code used for a VTR of a second television standard system different from the first television standard system. In the time code generator, the first frame signal of the first television standard system and the second frame signal of the second television standard system are synchronously combined by the same synchronization signal generator, A television signal synchronized time code generating device, characterized in that a second time code corresponding to the first time code is generated at a time when frames coincide with a period that is a common multiple of the period and the period of the second frame signal.