JPH0668027A - Microcomputer - Google Patents

Abstract

PURPOSE:To secure the recovery time even in the case that the speed of an operation clock is increased without changing the internal circuit constitution. CONSTITUTION:An incrementer 4 which can designate permission of operation at the time of transfer of the numerical value of a constant generator 3 to a bus interface device 2 is provided besides an execution device 1, the bus interface device 2 for information transfer, and the constant generator 3. In response to an interrupt INT signal 10, the execution device 1 indicates issue of acknowledge after the end of an instruction executed then. The bus interface device 2 uses a bus cycle start BCYST signal 5, an ST signal 6 indicating the classification of the bus cycle, an FAS signal 7, and a READY signal 8 to execute the interrupt by the indication of acknowledge. When a TIREQ signal 9 generated by a peripheral circuit is made active at this time, the value outputted from the constant generator 3 is incremented in the incrementer 4 by one. Thus, the number of idle cycles Ti to be inserted at the time of interrupt is increased equivalently, and the recovery time is secured.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an execution unit, a bus interface unit, and an idle unit executed by the bus interface unit when an input / output (I / O) unit is accessed.
The present invention relates to a microcomputer equipped with a constant generator for designating the number of cycles, and more particularly to a microcomputer equipped with a recovery time securing control function required when an I / O device is accessed.

[0002]

2. Description of the Related Art FIG. 7 is a block diagram of a conventional microcomputer. As shown in FIG. 7, the conventional microcomputer 24 is the microcomputer 2
4 has an execution unit 1 for executing the instructions, a bus interface unit 2 and a constant generator 3. The execution unit 1 has a function of requesting the bus interface unit 2 to generate a bus cycle to the outside, and in particular, when it recognizes that an interrupt request is generated by the INT signal 10 from the outside, an interrupt acknowledge is issued.・ Request a cycle. Further, the bus interface device 2 has a function of generating a bus cycle to the outside in response to a request from the execution device 1. Especially, when the execution device 1 requests an interrupt acknowledge cycle,
The BCYST signal 5, the ST signal 6, and the FAS signal 7 are output, the READY signal 8 is received, and the interrupt acknowledge cycle including a fixed Ti cycle period is executed. The BCYST signal 5 in the bus interface device 2 is a signal indicating the start (start) of the bus cycle (BCY) and is an active low signal output during the T1 cycle. The ST signal 6 is a signal indicating the type of bus cycle, and is output during two T1 and T2 cycles and the Ti cycle following the first T1 and T2 cycles when the interrupt acknowledge cycle is executed. There are multiple signals. Further, the FAS signal 7 is an active low signal indicating the first bus cycle in the interrupt acknowledge cycle. On the other hand, the received READY signal 8 is a signal indicating the end of the bus cycle, and is an active low signal for synchronizing the peripheral circuit and the microcomputer 24. The constant generator 3 described above generates a constant that specifies the number of Ti cycles to be executed, which is required when the bus interface device 2 executes an interrupt acknowledge cycle.

FIG. 8 is a system configuration diagram to which the microcomputer shown in FIG. 7 is applied. As shown in FIG. 8, this system includes a status decoder 12 connected to a microcomputer 24, a delay device 25 and a READ.
In addition to having the Y signal generator 14, the RS flip-flop 13 and the interrupt control device 15 are provided. Of these, the status decoder 12 that receives the ST signal 6 output from the microcomputer 24 is
And has the function of outputting the SDEC signal 17 of active low when it is decoded that it is an interrupt acknowledge cycle. Further, the delay device 25 for inputting the BCYST signal 5 has a function of outputting the DBCY signal 26 delayed by 2 clocks. The RS flip-flop 13 is a set / resettable flip-flop that uses the DBCY signal 26 as a set signal and the READY signal 8 as a reset signal,
The set / reset operation is controlled by designation from the outside. On the other hand, the READY generator 14 has a function of receiving the BCYST signal 5 and generating the waist number necessary for the external circuit. Further, the interrupt control device 15 has a function of generating an interrupt (INT) signal 10 to the microcomputer 24 when it recognizes the occurrence of an external interrupt by the interrupt request (IRQ) signal 19. In such a system, the fact that the INT signal 10 has been accepted by the microcomputer 24 means that the INT signal of active low that requires a recovery time of a certain period.
It is recognized by the AK signal 18.

FIG. 9 is a timing chart of various signals when an interrupt acknowledge cycle is executed in the microcomputer shown in FIGS. 7 and 8. As shown in FIG. 9, when an interrupt request is transmitted to the interrupt controller 15 by the IRQ signal 19, the interrupt controller 15 issues the INT signal 10 to the microcomputer 24.
When the microcomputer 24 receives the INT signal 10, it is internally input to the execution unit 1 and requests the bus interface unit 2 to execute the interrupt acknowledge cycle after the end of the instruction currently being executed. This allows
When the bus interface device 2 receives the execution of the interrupt acknowledge cycle from the execution device 1, the bus interface device 2 executes the interrupt acknowledge cycle using the BCYST signal 5, the ST signal 6, the FAS signal 7 and the READY signal 8. At this time, a Ti cycle is inserted between two T1 and T2 cycles. How many times this Ti cycle is inserted depends on the bus interface device 2 receiving the Ti cycle number from the constant generator 3. I have decided.

In this way, the microcomputer 2
When the interrupt acknowledge cycle is executed by No. 4, first the BCYST signal 5, ST signal 6 and FAS
The signal 7 is output. The BCYST signal 5 is delayed by 2 clocks in the delay device 25 and is given to the set input of the RS flip-flop 13 as the DBCY signal 26. Therefore, the INTAK signal 18 to the interrupt controller 15 is activated. Further, the READY signal 8 from the READY generator 14 is the RS flip-flop 1
3 applied to the reset input of pin 3 to inactivate the INTAK signal 18. The BCYST signal 5 is REA
Also provided to the DY generator 14, the READY generator 14 produces the READY signal 8 to terminate the bus cycle. Further, the ST signal 6 is the status decoder 1
2 and the bus cycle issued by the microcomputer 24 is recognized as the interrupt acknowledge cycle, the row active SDEC signal 17
To activate. As a result, the operation output of the RS flip-flop 13 becomes possible, and the interrupt controller 15
A predetermined INTAK signal 18 is output.

Originally, BCYS output at the time of the interrupt acknowledge cycle of the microcomputer 24
INT signal 1 by T signal 5, ST signal 6 and READY signal 8 output by READY generator 14.
8 should be generated. However, due to the speeding up of the operation clock CLK of the microcomputer 24, the interrupt control device 1 can be operated only in the Ti cycle period of the interrupt acknowledge cycle generated by the microcomputer 24.
In some cases, the INTAK signal 18 required by No. 5 cannot be generated. At this time, it is necessary to extend the period of the T2 cycle and generate the INTAK signal 18 by the means as described above.

[0007]

The above-mentioned conventional microcomputer fixedly executes the number of idle cycles obtained from the constant generator when accessing an I / O device requiring a recovery time. There is. Therefore,
If the operating clock is speeded up without changing the internal circuit of the microcomputer, there is a drawback that the recovery time required at the interrupt acknowledge cycle cannot be secured. Further, the conventional microcomputer has a plurality of I / Os used in the system.
There is a drawback that an optimal system cannot be configured due to variations in the recovery time of the device.

An object of the present invention is to provide a microcomputer which can cope with speeding up of an operation clock and secure a recovery time without changing the internal circuit and can make an optimum system. .

[0009]

The microcomputer of the present invention is required for a bus interface device having a function of generating a bus cycle to the outside, a function of executing instructions, and the bus interface device. An execution unit having the function of requesting a bus cycle that becomes
A constant generator that specifies the number of idle cycles to be executed to secure a recovery time when the bus cycle specified by the execution unit is an access to an I / O device, and the idle from the constant generator An incrementer for varying the number of idle cycles executed by the bus interface device according to the number of cycles and external designation.

[0010]

Embodiments of the present invention will now be described with reference to the drawings. FIG. 1 is a block diagram of a microcomputer showing an embodiment of the present invention. As shown in FIG. 1, the microcomputer 11 of this embodiment has an execution unit 1, a bus interface unit 2 and a constant generator 3, which are the same as those in the conventional microcomputer 24 shown in FIG. is there. The difference is that an incrementer 4 is provided which receives a TIREQ 9 from the outside, increments the value generated by the constant generator 3 and sends the incremented value to the bus interface device 2.
That is, the incrementer 4 has a function of outputting a constant obtained by adding 1 to the constant output by the constant generator 3 to the bus interface device 2 when the TIREQ signal 9 is input.

FIG. 2 is a system configuration diagram to which the microcomputer shown in FIG. 1 is applied. As shown in FIG. 2, such a system status decoder 12, READY
The generator 14, RS flip-flop 13 and interrupt controller 15 are also the same as those used in the conventional microcomputer system of FIG. The difference is that a negative logic AND gate 16 is provided and the output thereof is used as the TIREQ signal 9 to the incrementer 4.

First, in FIG. 1 and FIG. 2, when an interrupt request is transmitted to the execution unit 1 by the INT signal 10,
Similar to the conventional microcomputer 24 described above, the execution device 1 requests the bus interface device 2 to issue an interrupt acknowledge cycle. As a result, the bus interface device 2 receives the BCYST signal 5 and the FAS signal 7
And the ST signal 6 is activated to start execution of the interrupt acknowledge cycle. Next, when this interrupt acknowledge cycle is started, the RS flip
The INTAK signal 18 output from the flop 13 is BC
It becomes active by the YST signal 5 and becomes inactive by the READY signal 8 output from the READY generator 14.

FIG. 3 is a timing chart of various signals when an interrupt acknowledge cycle is executed in the microcomputer shown in FIGS. As shown in FIG. 3, when the interrupt acknowledge cycle is started, the FAS signal 7 and R are generated during the first T1 and T2 cycles.
By inputting the TIREQ signal 9 which is the AND condition of the EADY signal 8 to the microcomputer 11, the constant output from the constant generator 3 in the incrementer 4 is incremented by +1. Therefore, the number of Ti cycles inserted in the interrupt acknowledge cycle executed by the bus interface device 2 is increased by one (Tia cycle), and the recovery of the INTAK signal 18 is recovered.
The time (for 5 clocks) can be satisfied.

Therefore, in the microcomputer 11 of this embodiment, the Ti cycle can be inserted by the terminal input from the outside, so that the recovery time can be controlled without extending the T2 cycle.

In short, since the microcomputer of the above-mentioned embodiment has the dynamic recovery time securing means, the recovery time securing control required when the I / O device is accessed is externally controlled. Can be specified by the signal.

FIG. 4 is a block diagram of a microcomputer showing another embodiment of the present invention. As shown in FIG.
The microcomputer 22 of this embodiment is similar to the above-described one embodiment in that the execution device 1 and the bus interface device 2 are used.
And a constant generator 3, and instead of the incrementer 4, a TIREQ signal 9 and a tinct signal 21 from an external constant unit are input and an adder 20 for adding to a constant value from the constant generator 3 is used. That is, when the addition is externally designated by the TIREQ signal 9, the adder 20 adds the data output from the constant generator 3 and the value given by the TICNT signal 21, and the added data is sent to the bus interface device 2. It has a function to output.

FIG. 5 is a system configuration diagram to which the microcomputer shown in FIG. 4 is applied. As shown in FIG. 5, in such a system the status decoder 12, R
It has an S flip-flop 13, a READY generator 14, an interrupt controller 15 and an AND gate 16, which are the same as those used in the microcomputer system of the above-described embodiment. In this system, a constant generator 23 is further provided, and the microcomputer 22
The number of Ti cycles to be inserted is generated between the bus cycles.

FIG. 6 is a timing chart of various signals when an interrupt acknowledge cycle is executed in the microcomputer shown in FIGS. 4 and 5. As shown in FIG. 6, when an interrupt acknowledge cycle is executed by the bus interface device 2, the bus interface device 2 determines the number of Ti cycles to be inserted during the interrupt acknowledge cycle as the first T2 during the interrupt acknowledge cycle. Attempt to read from the constant generator 3 at the end of the cycle. At this time, if the TIREQ signal 9 is active, the adder 20 gives the data obtained by adding the value given by the TICNT signal 21 and the value outputted by the constant generator 3 to the bus interface device 2, so that an interrupt acknowledge signal is generated. The number of Ti cycles inserted in the cycle is increased by a value given by the TICNT signal 21 compared with the data output from the constant generator 3, so that the recovery time can be secured.

Therefore, the microcomputer 22 of the present embodiment inserts T at the interrupt acknowledge cycle.
Since the number of i cycles can be specified externally, there is an advantage that even when the operation clock of the microcomputer 22 is speeded up, it can be dealt with only by changing the data to be added.

[0020]

As described above, the microcomputer of the present invention has a function of designating the insertion of the idle cycle from the outside to the bus interface device, thereby improving the operating clock speed. However, since the minimum number of circuit modifications such as increasing the number of idle cycle requests can be dealt with, there is an effect that the existing hardware assets can be fully utilized. Further, the microcomputer of the present invention can flexibly cope with the combination with the I / O device requiring the recovery time, and has an effect that an optimum system can be configured.

[Brief description of drawings]

FIG. 1 is a block diagram of a microcomputer showing an embodiment of the present invention.

FIG. 2 is a system configuration diagram to which the microcomputer shown in FIG. 1 is applied.

FIG. 3 is a timing chart of various signals when an interrupt acknowledge cycle is executed in the microcomputer shown in FIGS. 1 and 2.

FIG. 4 is a block diagram of a microcomputer showing another embodiment of the present invention.

5 is a system configuration diagram to which the microcomputer shown in FIG. 4 is applied.

FIG. 6 is a timing diagram of various signals when an interrupt acknowledge cycle is executed in the microcomputer shown in FIGS. 4 and 5.

FIG. 7 is a block diagram of a microcomputer showing a conventional example.

8 is a system configuration diagram to which the microcomputer shown in FIG. 7 is applied.

9 is a timing diagram of various signals when an interrupt acknowledge cycle is executed in the microcomputer shown in FIGS. 7 and 8. FIG.

[Explanation of symbols]

 1 Execution Device 2 Bus Interface Device 3 Constant Generator 4 Incrementer 11,22 Microcomputer 20 Adder

Claims (2)

[Claims] 1. A bus interface device having a function of generating a bus cycle to the outside, a function of executing instructions, and a function of requesting a required bus cycle to the bus interface device. An execution unit, a constant generator for specifying the number of idle cycles executed to secure a recovery time when a bus cycle specified by the execution unit is an access to an I / O device, and the constant generator And an incrementer for varying the number of idle cycles executed by the bus interface device according to the number of idle cycles from the computer and designation from the outside. 2. The microcomputer according to claim 1, wherein an adder is used as the incrementer.