JPH0667992A - Backup memory inspection device - Google Patents

Abstract

PURPOSE:To provide a backup memory inspection device inspecting the power save operation, etc., of a backup memory corresponding to by each CPU in a system provided with plural CPU. CONSTITUTION:An IGF signal is stopped and IGF error information is transferred/stored to each backup RAM by a step 401. After a main power source is turned off and a power save operation is executed, the main power source is turned on again by a step 402. A specific input signal is added and the operation is plunged into a n inspecting mode by a step 403. Data is read from the prescribed output terminal of each CPU by a step 404 and the output data and logical value data are compared by a step 405. Then, the display of either OK or NG of the inspection result are displayed based on the result of the comparison by a step 406 or 407.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to, for example, a plurality of CPs.
In a vehicle electronic control unit including U, a backup RA set for each CPU thereof
The present invention relates to a back-up memory inspection device that inspects M and the like.

[0002]

2. Description of the Related Art An electronic control unit mounted on an automobile has a CPU corresponding to each of a plurality of devices mounted on the automobile. For example, engine air-fuel ratio control, electronic control transmission control, failure diagnosis control Etc. are shared by each CPU.

CP which constitutes such an electronic control unit
In U, each has a backup memory (backup RAM) for storing various data,
In this backup RAM, the control data is surely stored and held even when the main power supply is cut off. Therefore, in the back-up RAM corresponding to each CPU, it is an important requirement that the stored data is surely retained by the power save operation even when the main power supply is cut off.
In order to confirm the normal operation of the electronic control unit, it is necessary to check the power saving operation of these backup RAMs.

In order to inspect the power saving operation of such a back-up RAM, for example, information such as a diagnostic code is stored in the backup RAM respectively, and in this state, the main power source is temporarily shut off and the standby power source is set to the power saving state. To do. After being set in such a state, the main power supply is turned on again, information is output from the backup RAM set in the power save state, and the output information is checked to check the power save operation of the backup RAM. .

This backup RAM is inspected by the CPU
Each of them is independently executed. Therefore, as the number of CPUs and the number of backup RAMs increase, the inspection procedure becomes complicated and the time required for the inspection increases.

[0006]

SUMMARY OF THE INVENTION The present invention has been made in view of the above points, and in an electronic control unit including a plurality of CPUs, a power saving operation of a backup memory set for each of the CPUs. It is an object of the present invention to provide an inspection device for a backup memory that can be simply executed collectively and the inspection time can be surely shortened while simplifying the inspection procedure.

[0007]

A backup memory inspection apparatus according to the present invention comprises an electronic control unit having a plurality of CPUs each having a backup memory, and data being transferred to each of the CPUs. , The input diagnostic data to the plurality of CPUs
Data storage means for storing and setting the diagnostic data in the backup memory set in each of the CPUs, and the main power supply is turned off in the state where the data is stored so that the backup memory of each CPU is set. After setting the power save state, the main power supply is turned on again. After that, the inspection mode setting means sets the plurality of CPs.
Input a specific signal to each U to set the inspection mode,
The pass / fail judgment means checks the output from each of the plurality of CPUs.

[0008]

In the backup memory inspection device having such a configuration, the diagnostic information is collectively written to the backup memories set respectively for the plurality of CPUs via the data transfer path. Then, in this state, the main power is turned off and the power save operation is performed, and after the main power is turned on again, the diagnostic information stored in each backup memory is inspected. By inspecting the diagnostic information stored in the backup memory, it is possible to surely check whether the data transfer has been performed without malfunction and whether the power saving operation has failed.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows the overall configuration. The electronic control unit (ECU) 11 is provided with an operating means for checking the power saving operation of the backup RAM corresponding to the CPU constituting the electronic control unit 11. There is.

The electronic control unit 11 is mounted on, for example, an automobile and is used for engine control, transmission control,
Further, it performs failure diagnosis (diagnosis) control and the like, and an inspection machine 12 for operation check is provided for such an electronic control unit 11. This inspection machine 12 is provided with an input data giving means 13 for generating diagnostic data for operation check in a CPU etc. in the electronic control unit 11, and an output data reading means 14, and the input data giving means 13 and the output data are given. A comparison / determination means 15 for comparing input data with output data is set between the reading means 14 and the reading means 14.

FIG. 2 shows the configuration of an electronic control unit 11 mounted on a vehicle, for example, which electronically controls an engine, and includes first to third CPUs 21 to 22, for example. Here, the first CPU 21 controls the fuel injection amount (E
In charge of engine control such as FI) and the second CP
U22 is in charge of failure diagnosis (diagnosis), and the third C
The PU 23 is in charge of electronic transmission control (ETC), and the first to third CPUs 21 to 23 are individually in charge of controlling independent electronic control devices.

Although the three CPUs 21 to 23 are shown in the figure, there are more control target devices in the electronic control unit actually mounted in the automobile, and these control target devices correspond to the respective control target devices. Then, the CPU is set, and these CPUs 21 to 23 are connected to the input / output interface 24, respectively.

When the electronic control unit 11 is mounted on the vehicle as described above, the input side of the input / output interface 24 is the engine speed data Ne corresponding to the signal from the crank angle sensor of the engine, the air flow meter output (the intake air amount). ) Q, cooling water temperature sensor output THW, vehicle speed sensor output S
A PD, an igniter, various switches, etc. are connected.
Further, control signals for the fuel injection valve, the igniter, the check engine lamp, the solenoid valve of the transmission, etc. are taken out from the output side of the interface 24.

Then, according to the control program, the first
Or, the third CPUs 21 to 23 are selectively controlled. For example, calculation is performed based on input data such as engine speed Ne, and the output of the output side device is controlled by the control output from the input / output interface 24. Control.

The CPUs 21 to 23, which are respectively assigned roles,
Sequential DMA (Direct Memory Access) communication line 25
And 26, and the communication lines 25 and 26 enable data exchange.

For example, the engine speed Ne, the intake air amount Q, the cooling water temperature THW, the ignition abnormality signal IGF, etc. are input to the first CPU 21 for performing EFI control via the input / output interface 24, and the ignition signal IGT is input. , Fuel injection amount #
10 and # 20 are output. At the time of output for such engine control, the second CPU 22 for diagnostic control and the third C for ECT control are performed using the DMA communication lines 25 and 26.
Information such as the ignition abnormality signal IGF can be transmitted to the PU 23 and the like.

FIG. 3 shows the configuration of one CPU 30 (21 to 23) portion which constitutes one electronic control unit 11.
/ O interface 31 and communication interface 32
A ROM 36 in which a normal RAM 34 and a backup (B / U = standby) RAM 35 are set together with the CPU 30 for the data bus 33 set between the two, and a control program and an inspection program including a power saving operation check of the backup RAM 34 are stored. Equipped with. The communication interface 32 has a built-in DMA controller and is connected to the DMA communication lines 25 and 26. The I / O interface 31 is connected to communication lines 27 and 28 with the input / output interface 24 of FIG.

Here, the DMA (Direct Memory Access) is a direct normal RAM without the CPU 30.
34, which is a function that can be accessed by the CPU 30, by including this DMA in the communication interface 32.
It becomes possible to perform regular data communication without being affected by the calculation time in.

A procedure for inspecting the backup memory (RAM) in the device thus constructed will be described. FIG. 4 shows the basic flow of the inspection procedure by the inspection machine 12, and FIGS. 5 and 6 show the flow of inspection control in the steady mode state and the inspection mode state, respectively. Hereinafter, this inspection procedure will be described step by step.

[Inspection Step 1] First, in the steady mode at step 401 in FIG. 4, the ignition abnormality signal IGF given from the inspection machine 12 is stopped, and the first CPU
21 causes the abnormal ignition signal to be determined in a simulated manner.

In this steady mode, the main power source + B is turned on by the switch S in this state, and the standby power source from the battery is constantly supplied. FIG. 5A
As shown in FIG. 1, the first CPU 21 uses the normal self-diagnosis (diagnosis) logic to output the error information (diagnosis data) of the ignition abnormality signal to the backup RAM 35 of the first CPU 21.
In memory (shown in FIG. 7A).

FIG. 5A shows the flow of self-diagnosis processing executed by the first CPU 21. CPU
21 determines in step 501 whether there is an IGF signal,
If it is determined that there is no IGF signal, then in step 502, I
Remember the GF error. Then, in step 503, the first CPU 21 transfers this IGF error to the second CPU 22.

When the IGF error information is transferred to the second CPU 22 as described above, this IGF error information is stored in a predetermined backup RAM of the second CPU 22. FIG. 5B is a diagram showing a flow of error information reception / transmission processing executed by the CPU 22. CPU22
First, in step 511, the IGF error information transferred from the CPU 21 is stored in the backup RAM. Then, in step 512, the second CPU 22 sends the next CP
Transfer the IGF error information to U23. Then, the transfer of the error information is sequentially performed to the plurality of CPUs.

The third CPU 23 performs a process of storing the transferred IGF error information in a predetermined backup RAM of this CPU 23.

In this way, the error information determined by the CPU 21 of the first stage is passed through the CPU 22 of the middle stage to the third stage of the final stage.
The inspection step 1 shown as step 401 in FIG. 4 is completed with the data transferred to the CPU 23.

[Inspection Step 2] In Step 402 of FIG. 4, the switch S is opened to turn off the main power source + B as shown in FIG. 7B. In this case, the standby power from the battery is supplied as it is, and the power saving operation can be executed in the backup RAM.
In step 402, switch S is opened and CP
The switch RA is turned on again after the main power supply to U is turned off. When the switch S is turned off, the backup RA
If the power save operation is normally performed on M,
When the main power is turned on again, each CPU 21-
23 The IGF error information should be normally stored in each backup RAM.

[Inspection Step 3] In step 403, the inspection machine 12 adds a specific input signal to the first CPU 21.
CPU 21 is put into the inspection mode shown in FIG. If the inspection mode is entered in this way, the CPU 21
Determines in step 601 whether there is IGF error information, and I
When it is determined that the GF error information is present, the process proceeds to step 602 to set a predetermined output terminal to ON. In step 601, I
If it is determined that there is no GF error information, step 503.
The predetermined output is set to OFF (state of FIG. 8A).
Similarly, the CPUs 22 and 23 perform the processing as in steps 611 to 613 of FIG. 6B, and the inspection step 3 is ended.

[Inspection Step 4] In Step 404, the inspection machine 12 causes the output data reading means 14 to operate the CPUs.
21 to 23 Read the data from the respective predetermined output terminals. In the following step 405, in the comparison and determination means 15, the CPU
The data output from each of 21 to 23 and the theoretical value data are compared. Then, the output data and the theoretical value data correspond to all CPUs 21 corresponding to the judgment result of step 405.
23 to 23, the OK display is performed in step 406, and if there is a mismatch in any of the CPUs, the NG display is performed in step 407 for the CPU having the mismatch (see (B) of FIG. 8). Status). And
With the display of OK or NG, the power saving check of the backup RAM of each of the CPUs 21 to 23 is completed.

Although the embodiment has shown the example in which three CPUs are used, the present invention is not limited to the number of CPUs, and even if more CPUs are used, the backup memory ( RAM) can be checked. The same check can be performed even in the electronic control unit in which the ROM and the RAM are set externally. The data transfer means is not limited to the DMA communication in particular, and can be checked in a system configuration in which information is transmitted between the CPUs by using a dual port RAM or the like. Furthermore, if the rushes of the inspection modes of the plurality of CPUs are made to coincide with each other, the inspection time can be further shortened.

[0030]

As described above, according to the backup memory inspection apparatus of the present invention, particularly in an electronic control unit including a large number of CPUs, power saving of a large number of backup memories can be achieved by a simplified structure. The operation can be checked, and the check time can be shortened sufficiently. In particular, when it is difficult to store data in the backup memory in a normal control program, the effect is remarkable.

[Brief description of drawings]

FIG. 1 is a configuration diagram for explaining an inspection device according to an embodiment of the present invention.

FIG. 2 is a configuration diagram illustrating an electronic control unit section.

FIG. 3 is a diagram illustrating a configuration of a portion corresponding to one CPU.

FIG. 4 is a flowchart illustrating an inspection procedure.

5A and 5B are IGs in a normal mode.
The flowchart explaining the input of F error information.

6A and 6B are flowcharts for explaining the procedure in the inspection mode.

7A and 7B are Cs in a normal mode.
The figure explaining the state of PU.

FIG. 8A is a diagram illustrating a state of each CPU in an inspection mode, and FIG. 8B is a diagram illustrating a check output state.

[Explanation of symbols]

11 ... Electronic control unit, 12 ... Inspection machine, 13 ... Input data giving means, 14 ... Output data reading means, 15 ... Comparison determining means, 21-23 ... CPU, 24 ... Input / output interface, 30
… CPU, 34… Normal RAM, 35… Pack-up RA
M, 36 ... ROM.

Claims (1)

[Claims] 1. An electronic control unit comprising a plurality of CPUs each having a backup memory, each CPU being coupled by a data transfer path, and data input means for inputting diagnostic data, and this input. Data storage means for respectively transferring the diagnostic data to the plurality of CPUs and storing and setting the diagnostic data in the backup memory set corresponding to each of the CPUs. The backup memory of the CPU is set to the power save state, the power supply control means for turning on the main power supply again, and the specific signal is input to each of the plurality of CPUs with the main power supply turned on again by the power supply control means. An inspection mode setting means for entering the inspection mode, and PU comprises a quality determination means for checking the output from each testing device back Abbu memory, characterized in that said backup memory each quality determination of the CPU and the like is performed.