JPH0667976A - Cache memory control system by hardware control software - Google Patents

Abstract

PURPOSE:To improve the efficiency deterioration owing to the erroneous hit of an instruction word cache memory at the time of executing hardware control software and the using method of the instruction word cache memory which becomes to be inefficiently used owing to the execution of hardware control software CONSTITUTION:In the groups of hardware control software instructions 310, 320 and 330 of which efficiency importance are respectively a high-order, a middle-order and a low order, hardware control software support instructions 341, 342 and 343 updating the number of block loading times at the time of the block loading of the instruction word cache memory and LRU replacement information and changing block loading suppressing operation to the instruction word cache memory and a hardware control software support instruction 344 for leaving a hardware control software mode are arranged at proper positions so that the instruction word cache memory is controlled by changing to the operation at the time of the block loading of the instruction word cache memory in accordance with the efficiency importance of the group of hardware control software instructions by hardware control software.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cache memory control system using hardware control software, and more particularly to controlling the number of block loads that occur when a block is loaded into a cache memory and reading a cache directory when reading a command from a main memory device. And a cache memory control method by hardware control software in the control of the cache memory and the control of the block load suppression operation to the cache memory.

[0002]

2. Description of the Related Art In order to close the operation speed gap between a main processing unit and a main memory unit, it is often adopted to provide a cache memory unit composed of a high speed and small capacity memory between them. Furthermore, in the method of prefetching and executing instruction words such as pipeline processing, the cache memory is separated for instruction words and operands, and an instruction word cache memory and an operand cache memory are provided.

The main memory device is divided into blocks of a certain capacity in advance, and the data stored in some of these blocks is written in the cache memory of the cache memory device (block load). That).

Information about which of the blocks in the main memory device is written in the cache memory is written in the cache directory in the cache memory device.

In response to a data read request from the main processing unit, the cache directory and the cache memory are read. First, the read data from the cache directory determines whether or not the requested data exists in the cache memory. Can be examined. If it exists (hits), the corresponding data in the read data from the cache memory is sent to the main processing unit. When it is found that the data does not exist (miss hit), the read data from the cache memory is discarded, the corresponding address in the main memory device is read and sent to the main processing device, and the main memory containing the read data is read. A data block in the device is block-loaded to a free block of the cache memory or a block having the longest unused time (LRU replacement).
At the same time, the cache directory and LRU replacement information are also updated.

The number of block loads from the main memory device executed at the time of a mishit is a fixed value determined by the hardware configuration. The above operation is performed in the same manner in the case of the instruction word cache memory.

On the other hand, in the main processing unit, hardware control software (hereinafter referred to as HCSW) having a hardware / firmware function has been implemented in order to reduce a control storage capacity and a firmware design amount. HC
The SW is a machine language instruction group coded by a software instruction group selected from all the instructions released to general software and an HCSW support instruction group, and is stored in the hardware area of the main memory.

As the operation mode of the main processing unit, there are a software mode and an HCSW mode. In the software mode, the software manages the contents of the instruction counter, base register, general-purpose register, etc., and the main processing unit operates based on the instructions of the software. Also,
In the HCSW mode, the contents of the instruction counter, base register, general-purpose register, etc. managed by the software are saved, and the main processing unit operates based on the instructions of the HCSW.

The hardware or firmware of the HCSW is activated as necessary, and the HCSW is moved to the HCSW mode.
After the processing is completed, the software mode is entered.

Further, since the HCSW is for realizing a part of the hardware / firmware function,
It exists in the main memory in a form of a group of HCSW instructions in a certain functional unit. The main functions implemented by the HCSW are control functions such as so-called process management / stack processing / configuration control commands, and therefore the HCS.
As for the operation of W, there are few repeated processes such as loop processing,
In many cases, it is executed sequentially sequentially in the vertical direction. Therefore, the arrangement of the instruction words of the HCSW instruction group on the main memory does not have to be the local arrangement on the main memory represented by the loop processing as is said in general software, but realizes one function. Therefore, the feature is that the addresses are arranged continuously over a wide range.

As for the cache memory control method, there is no distinction between general software and HCSW.
The general software instruction group and the HCSW instruction group are written to the instruction word cache memory under the same control as they are only controlled based on the address on the main memory.

[0012]

In the above-mentioned conventional cache memory control method, when the above-mentioned HCSW is executed, the instruction word cache memory is miss-hit, and a predetermined main memory device sends the instruction word cache memory to the instruction word cache memory. The amount of read data during block load
When the execution of the HCSW instructions in the block-loaded instruction word cache memory ends because the program amount of the HCSW instruction group for realizing a certain function is much smaller and the number of block loads is fixed. , The instruction word cache memory becomes a mishit and it becomes necessary to perform block loading. After that, this state is repeated, and while realizing one function in HCSW,
There is a drawback in that the instruction word cache memory becomes a mishit many times, resulting in a significant decrease in performance.

Also in the method of using the instruction word cache memory, the general software instruction and the HCSW instruction are controlled without distinction, and both the general software instruction group and the HCSW instruction group are controlled based on the address on the main memory. Similarly, since the instruction word cache memory is collectively written, even if it is known that the HCSW instruction group has low performance importance, the instruction word cache memory is written and the instruction word cache memory is written. There is a drawback that the number of empty blocks in the memory is reduced, or the blocks in which the general software instruction group and the HCSW instruction group, which are more important in terms of performance, exist, disappear from the instruction word cache memory.

Furthermore, since the HCSW instruction group of low performance importance is written, another general software instruction group of high performance importance and HCSW which should originally be stored in the instruction word cache memory. Due to the logic that the block in which the instruction group exists is loaded into the block with the longest unused time (LRU replacement), it becomes the target block to be replaced by the next block load. Therefore, it is effectively used. There is a drawback that the instruction word cache memory to be executed is not used effectively.

[0015]

A cache memory control method using hardware control software according to the present invention uses a microprogram to execute hardware control software, which is a machine language instruction format routine stored in a hardware area of a main memory device. And a function for controlling hardware by executing the hardware control software one by one with a microprogram, and a means for storing the hardware control software instruction and the general software instruction in the same cache memory without distinguishing each other, Means for changing the number of times of block loading from the main memory device to the cache memory before starting the hardware control software, means for arbitrarily changing the number of times by the hardware control software, Triggered by the completion of Dowea control software, and means for changing the hardware predetermined block loading number, the updating operation of the LRU replacement information is executed when the block load,
A means for suppressing by the instruction before the activation of the hardware control software, a means for suppressing by the instruction of the hardware control software, and the inhibition of the update operation of the LRU replacement information triggered by the termination of the hardware control software Means for inhibiting the cache block load and reading the instruction word without going through the cache memory, and instructing the inhibition of the block load before starting the hardware control software, The hardware control software is provided with a means for instructing the inhibition of the block load, and a means for releasing the inhibition of the block load upon the termination of the hardware control software.

[0016]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a cache memory control system by the hardware control software of the present invention.

As shown in FIG. 1, an instruction word cache memory device adopting a cache memory control method by hardware control software of the present embodiment includes an instruction word including an address register 1 and block groups 3, 4, 5, and 6. The cache memory 2, the instruction word cache directory 7 including the LRU replacement information 8 and the block groups 9, 10, 11, 12 and the hit detection circuits 13, 14, 15,
16, instruction word cache memory control circuit 18, data selection circuit 19, address update circuit 20, instruction word cache memory buffer device 17, buffer device control circuit 21, instruction word cache memory write control circuit 2
2 and the LRU replacement information updating circuit 23.

In FIG. 1, in response to a data read request from a main processing unit (not shown), a command 101 and an address signal 102 are sent from the main processing unit to an instruction word cache memory device. Address signal 102
Is input to and held in the address register 1. The middle-order address signal 104 of this address signal 102 is
A column number in the instruction word cache memory 2, the instruction word cache directory 7, and the instruction word cache memory write inhibition circuit 22 is designated and becomes an access address signal.

From the block groups 9, 10, 11 and 12 of the instruction word cache directory 7, the middle level address signal 1
From the column number designated by 04, the loaded contents are read out to the hit detection circuits 13, 14, 15 and 16, respectively. Also, in the LRU replacement information 8, the column number portion designated by the middle address signal 104 is updated. At this time, the LRU replacement update inhibit signal 12 designated by the HCSW instruction group 12
If 5 is sent from the main processing unit, the operation of the LRU replacement information updating circuit 23 is stopped, the LRU replacement information 8 is not updated, and the state of the old value is maintained.

Similarly, from the block groups 3, 4, 5, 6 of the instruction word cache memory 2, the medium address signal 1 is also sent.
The load content is read from the column number designated by 04 to the data selection circuit 19.

In the hit detection circuits 13, 14, 15, and 16, when the valid bits of the block groups 9, 10, 11, and 12 indicate valid display, the data bits to be read and the address register 1 are sent. The hit signals 110, 111, 112, 113 indicating the state of hit or miss hit are compared and collated with the upper address 103.
Are sent to the instruction word cache memory control circuit 18, respectively.

In this process, the hit detection circuit 13,
Hit signals 110, 11 sent from the instruction word cache memory control circuit 18 from the reference signals 14, 15, 16 respectively
When all 1, 112, 113 indicate a mishit state, the data read from the block groups 3, 4, 5, 6 of the instruction word cache memory 2 are discarded and the instruction word cache memory control circuit 18 Is a read request signal 1 to the main memory device (not shown).
17 is sent out. At this time, a read request to the main memory device is sent by the block load request signal 126 sent from the main processing unit for the number of block loads designated by the HCSW instruction group.

In response to this read request signal 117, the data block 108 is sent from the block having a predetermined column number from the main memory device and sent to the instruction word cache memory buffer device 17.

The instruction word cache memory buffer output data block 109 is a block group indicated by the LRU replacement information 8, in the case of this example, a block having the predetermined column number in the block group 3 of the instruction word cache memory 2. At the same time, in the block group 9 of the instruction word cache memory directory 7, a predetermined data bit is loaded in a block having a predetermined column number. In addition, the block of the predetermined column number in the LRU replacement information 8 is also LR
Output signal 107 of U replacement information updating circuit 23
Is loaded. Also at this time, if the LRU replacement information update inhibit signal 125 specified by the above-mentioned HCSW instruction group is sent from the main processing unit, the operation of the LRU replacement information update circuit 23 is stopped and the LRU is updated.
The replacement information 8 is not updated and remains in the state of the old value, and the block group 3 loaded this time
Will be the replacement target block group at the next block load.

On the other hand, the instruction word cache memory buffer output data block 109 input to the data selection circuit 19 is generated via the low-order address signal 105 input from the address register 1 to the instruction word cache memory control circuit 18. Controlled by the control signal 127 input to the data selection circuit 19, only the read target word from the main processing device is selected, and the main processing device is sent as the read data 119. Needless to say, the instruction word cache memory control circuit 18 sends the read signal 119 as well as the reply signal 118 to the main processing unit.

At this time, if a plurality of block load requests are instructed by the HCSW instruction group, data blocks corresponding to the number of block load requests are held in the instruction word cache memory buffer device 17. Furthermore, HCSW
The buffer device control circuit 21 outputs a buffer control signal 124 in response to a plurality of block load request signals 123 instructed by an instruction group, and a predetermined data block is an instruction word cache memory buffer output data block 1
09, the instruction word cache memory buffer device 17
Sent by. Further, in synchronization with this, an address update signal 121 is sent from the main processing unit to the address update circuit 21, a middle address 120 indicating the address of the above-mentioned predetermined data block is generated, and the address register 1 is updated. . Hereinafter, the above operation is repeated until the block load request count is reached.

At this time, if an instruction word cache memory block load inhibition request is issued by the HCSW instruction group, the instruction word cache memory write operation inhibition request signal 122 from the main processing unit is sent to the instruction word cache memory write control circuit. 22 and the instruction word cache memory write control circuit 22 outputs a write inhibition signal 128 to inhibit writing to the instruction word cache memory 2. Needless to say, the update of the instruction word cache memory directory 7 is also suppressed. Further, the instruction word cache memory buffer output data block 109 at this time is sent to the data selection circuit 19, and a predetermined word is sent to the main processing unit as the read data 119 by the control signal 127. The instruction word cache memory control circuit 18 also sends a reply signal 1 to the main processing unit as in the above description.
18 is sent out.

FIG. 2 is a diagram showing an embodiment of the HCSW starting method for changing the operation at the time of block loading of the instruction word cache memory 2 before starting the HCSW of the present invention.

In this embodiment, the pointer of each table is traced to reach the HCSW instruction group for realizing one processing. Now, the activation address storage table pointer 200 is set to the activation address storage table 21.
It points to the beginning of 0. Boot address storage table 21
0 is formed by sequentially arranging a plurality of entries. There is one entry corresponding to one process realized by HCSW. Each entry includes a control information field 211 and an activation address information field 212. The control information field 211 stores information related to the contents to be processed prior to the transfer to the HCSW. The control information field 211 stores the number of block loads of the control information regarding the instruction word cache memory in the present invention, the update inhibition information of the LRU replacement information, and the instruction word cache. It contains block load suppression information to the memory. Activation address information field 2
12 stores the start address of the HCSW instruction group 220 to be executed.

The transfer to the HCSW is performed by hardware and firmware. The HCSW instruction group transfer routine first displays the transition to the HCSW mode as common preprocessing, saves the instruction counter, base register, general-purpose register, or switches to the HCSW dedicated register group. After that, based on the boot address storage table pointer 200, the entry corresponding to the process to be executed is read from the table 210, and the control information field 211 of the entry is checked to perform the individual process to be executed before the import, The activation address is determined from the address information field 212 of the entry.

In the case of FIG. 2, HCSW instruction groups 221 and 22
When the performance importance levels of 2 and 223 are set to high, medium, and low, respectively, the control information field 211 in the boot address storage table 210 is set as shown in the HCSW control information field setting table of Table 1, respectively. it can.

[0033]

[Table 1]

That is, HCSW of high importance in terms of performance
In the instruction group 221, block load is executed multiple times,
The LRU replacement information is updated and the block cache memory is loaded with the block. As a result, the HCSW instruction group 221 operates by fully utilizing the instruction word cache memory, and the HCSW instruction group 221
During execution, the number of instruction word cache memory mishits decreases, and performance improvement can be expected.

Further, in the HCSW instruction group 222 having a medium level of performance importance, the block load is executed a plurality of times and the block load to the instruction word cache memory is also executed, but the LRU replacement information is not updated.
Other more important general software and HCS
The W instruction group does not have to be expelled from the instruction word cache memory when the next block is loaded, and the instruction word cache memory is used efficiently.

Further, in the HCSW instruction group 223, which is of low importance in terms of performance, the block load to the instruction word cache memory is suppressed, so that the instruction word is read from the main memory device every time. There is no change in the instruction word cache memory, and other general software of higher importance in terms of performance and the HCSW instruction group remain held in the instruction word cache memory.

As described above, by changing the block load operation of the instruction word cache memory before starting the HCSW to an operation suitable for the importance of the performance of each HCSW instruction group, the instruction word cache memory Can be used effectively.

FIG. 3 is a diagram showing an embodiment of the HCSW operation when the operation at the time of block loading of the instruction word cache memory is changed by the instruction of the HCSW of the present invention.

FIG. 3 shows HCSW instruction groups 310, 320,
Each of the HCSW instruction groups has a performance importance of high, medium, or low. Also, each HC
In the SW instruction group, a branch instruction 340 and HCSW support instructions 341, 342, 343, and H for changing the operation at the time of block loading of the instruction word cache memory.
An HCSW support instruction 344 for leaving the CSW mode is arranged. HCSW support instructions 341, 342,
The change contents of the operation at the time of the block load of the instruction word cache memory executed in 343 are as shown in the execution content table of the HCSW support instruction of Table 2 as follows.

[0040]

[Table 2]

The port instruction 341 has the operation contents at the time of block loading when executing the HCSW instruction group of high performance importance, and the HCSW support instruction 342.
Then, it is the operation contents at the time of block loading when executing the HCSW instruction group of medium importance for performance.
In the SW support instruction 343, the HC of low importance in terms of performance
The operation contents are for block loading when executing the SW instruction group.

Now, assuming that the HCSW instruction group 310 is in operation, the importance of performance is high. Therefore, in the operation at the time of block load of the instruction word cache memory, the block load is executed a plurality of times, and the LRU replacement information is executed. Is also executed, block loading to the instruction word cache memory is also executed, and the instruction word cache memory is being fully used.

When the operation of the HCSW shifts from the HCSW instruction group 310 to the HCSW instruction group 320, the HCSW instruction group 3
10, the HCSW support instruction 342 is executed, the operation at the time of block loading of the instruction word cache memory is performed a plurality of times of block loading, the update operation of the LRU replacement information is suppressed, and the block loading to the instruction word cache memory is executed. The content is set to be suitable for the HCSW instruction group, which is of a medium importance in terms of performance. After that, the branch instruction 340 is executed and the operation of the HCSW shifts to the HCSW instruction group 320. At this time, a fetch of the instruction word of the HCSW instruction group 320 causes a miss hit of the instruction word cache memory, and the instruction word cache memory Block load is executed. The operation at the time of block loading executed at this time is an operation suitable for the HCSW instruction group of the medium importance of performance set by the above-mentioned HCSW support instruction 342, and thereafter the HCSW instruction group 320 operates in this state. to continue. Further, when the operation of the HCSW moves from the HCSW instruction group 320 to the HCSW instruction group 330, the HCSW support instruction 343 is executed, and when the HCSW instruction group 330 operates, the operation at the time of the block load of the instruction word cache memory is performance. The operation is suitable for the less important HCSW instruction group. Furthermore, the HCSW instruction group 33
When the operation of the HCSW shifts from 0 to the HCSW instruction group 310, the HCSW support instruction 341 is executed and the HCS
When the W instruction group 310 operates, the operation at the time of block loading of the instruction word cache memory is an operation suitable for the HCSW instruction group of high importance in terms of performance.

That is, the operation at the time of the block load of the instruction word cache memory is performed by the HCSW which is of high importance in terms of performance.
When the operation of the HCSW shifts to the instruction group, by executing the HCSW support instruction 341, the operation is changed to an operation suitable for the HCSW instruction group of high performance importance, and the HCSW of medium performance importance is executed. When the operation of the HCSW shifts to the instruction group, by executing the HCSW support instruction 342, the operation is changed to the operation suitable for the HCSW instruction group having the medium performance importance, and the HCSW having the low performance importance is executed. When the operation of the HCSW shifts to the instruction group, the HCSW support instruction 343 is executed so that the H of the lower importance level in terms of performance.
The operation is changed to suit the CSW instruction group.

Further, in order to shift from the HCSW mode to the software mode at the end of the operation of each HCSW instruction group,
The HCSW support instruction 344 for exiting the HCSW mode is executed, and the operation at the time of block loading of the instruction word cache memory is set to a predetermined hardware operation, that is, the number of times of block loading is set to 1 and the update suppression of the LRU replacement information is released. , The block load suppression to the instruction word cache memory is released.

As described above, by dynamically changing the block load operation of the instruction word cache memory by the HCSW support instruction, the instruction word cache memory can be formed in a form suitable for the importance of the performance of each HCSW instruction group. Can be controlled.

[0047]

As described above, the cache memory control method by the hardware control software of the present invention is important for performance by changing the operation at the time of block loading of the instruction word cache memory by HCSW as necessary. In the high-ranking HCSW, it is possible to reduce the number of miss hits of the instruction word cache memory by executing the block load multiple times, and the performance is improved. Also, in the case of HCSW of low importance for performance, by suppressing the update of LRU replacement information and block loading to the instruction word cache memory, general software and HCSW of higher performance importance are erased from the instruction word cache memory. Therefore, the instruction word cache memory can be used effectively.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a cache memory control system by hardware control software of the present invention.

FIG. 2 is a diagram showing an embodiment of an HCSW activation method for changing the operation at the time of block loading of the instruction word cache memory before the HCSW activation in the cache memory control method by the hardware control software of the present embodiment.

FIG. 3 is a diagram showing an example of an HCSW operation in the case of changing the operation at the time of block loading of the instruction word cache memory according to the instruction of the HCSW in the cache memory control method by the hardware control software of the present embodiment.

[Explanation of symbols]

1 address register 2 instruction word cache memory 3, 4, 5, 6, 9, 10, 11, 12 block group 7 instruction word cache directory 8 LRU replacement information 13, 14, 15, 16 hit detection circuit 17 instruction word cache memory buffer Device 18 Command word cache memory control circuit 19 Data selection circuit 20 Address update circuit 21 Buffer device control circuit 22 Command word cache memory write control circuit 23 LRU replacement information update circuit 200 Boot address storage table pointer 210 Boot address storage table 211 Control information field 212 activation address information field 220, 221, 222, 223, 310, 320, 3
30 HCSW instruction group 340 Branch instruction 341, 342, 343, 344 HCSW support instruction

Claims (3)

[Claims] 1. A hardware by calling a hardware control software, which is a routine in a machine language instruction format stored in a hardware area of a main memory device, by a microprogram and executing the hardware control software step by step by the microprogram. In a data processing device having a function of controlling the above, the hardware control software instruction and the general software instruction are stored in the same cache memory without distinction, a block load at the time of block loading from the main memory device to the cache memory A means for changing the number of times before starting the hardware control software, a means for arbitrarily changing the number by the hardware control software, and a hardware predetermined time triggered by the termination of the hardware control software. The cache memory control method according to the hardware control software, characterized in that and means for changing the block load times. 2. A hardware control software, which is a routine in the form of machine language instructions stored in a hardware area of a main memory device, is called by a microprogram, and the hardware control software is executed step by step by the microprogram. In a data processing device of a system having a function of controlling the above, and storing the hardware control software instruction and a general software instruction in the same cache memory without distinction, the data processing apparatus is executed when a block is loaded from the main memory device to the cache memory. Means for suppressing the updating operation of the LRU replacement information by an instruction before the activation of the hardware control software; means for suppressing the operation by the instruction of the hardware control software; In the wake of the completion, the LRU
A cache memory control method by hardware control software, characterized in that it comprises means for canceling suppression of replacement operation of replacement information. 3. A hardware control software routine, which is a machine language instruction format stored in a hardware area of a main memory device, is called by a microprogram, and the hardware control software is executed step by step by the microprogram. In a data processing device of a system having a function of controlling the above, and storing in the same cache memory without distinguishing between the hardware control software instruction and the general software instruction, the instruction is executed without suppressing the cache block load and passing through the cache memory. A unit configured to read a word and instructing to inhibit block loading before starting the hardware control software; and a unit instructing inhibition of block loading by the hardware control software.
A cache memory control method by hardware control software, comprising means for releasing the inhibition of the block load upon termination of the hardware control software.