JPH05158794A - Cache compartment selection controller - Google Patents

Abstract

PURPOSE:To execute a routine whose utilizing frequency is low, and whose processing speed is requested, without generating the deterioration of a performance due to a cache miss hit. CONSTITUTION:An address array 2 and a data array 3 have plural compartment 2-1-2-4, and 3-1-3-4. A block load (writing) mode for the specific compartment(for example, 2-1 and 3-1) can be necessarily obtained by controlling a selector 5 by an outside command, for example, inputting '1' to a compartment selecting means 7. Thus, the routine whose high speed processing is requested can be loaded from a main storage to the specific compartment. Then, when '0' is inputted through the selector 5 to the means 7 by the outside command, the specific compartment is turned to a block load inhibition mode, so that the written routine can be necessarily turned to the cache hit without being replaced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cache compartment selection control device, and more particularly to a cache compartment selection control device for a cache having a plurality of compartments which stores a block copy of storage data in main storage and is indexed by a part of the main storage address. It is a thing.

[0002]

2. Description of the Related Art Conventionally, a cache aims at shortening the data read time in the main memory by placing a copy of the data in the main memory that has been read in a memory that can be accessed at high speed in block units. It is what

Normally, a part of the main memory address (called a set address) is used to determine where in the cache memory a copy of the main memory data is stored, and a plurality of storage locations are provided for data having the same set address. And each is called a compartment.

When data having the same set address but different addresses other than the set address is read, the data is stored in an unused compartment.
When all the compartments for the same set address are used and the main memory data with the same set address but different addresses other than the set address is read, new data is replaced with the data in a certain compartment by a predetermined replacement algorithm. Is stored.

In the above-mentioned conventional method, when data having the same set address is used and all the compartments are read, when the data having the same set address is read, the replacement algorithm replaces the data of a certain compartment with new data. However, the data to be ejected is usually the least frequently used data, and the most recently used data is often the oldest data.

However, in a software program or a firmware program, a routine which is not frequently used but is required to have a high processing speed (a routine for controlling a peripheral device which is rarely used but operates at a very high speed) Etc.), the routine program does not hit the cache, and if it goes to the main memory for reading each time, there is a problem that the processing performance deteriorates significantly.

[0007]

SUMMARY OF THE INVENTION It is an object of the present invention to provide a cache compartment selection control device capable of executing a routine which is rarely used but requires a high processing speed, without causing performance degradation due to a cache miss. Is.

[0008]

According to the present invention, there is provided a cache compartment selection control device for a cache having a plurality of compartments which stores a block copy of stored data in a main memory and is indexed by a part of the main memory address. A cache compartment selection control device having a means for forcibly performing block data load control for a specific compartment according to a command is obtained.

[0009]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention. In this example, the cache is a 4-compartment set associative store-through method, and the cache data replacement algorithm is a method of expelling the oldest data last used at the time of block loading (LRU).
System) will be described.

The apparatus of this embodiment comprises the main memory address register 1 and the compartments 2-1 and 2-of the address array 2.
2, 2-3, 2-4 and the compartment of the data array 3
For each set address, 3-1, 3-2, 3-3, 3-4 and when the data stored in one compartment is used, and when the data stored in another compartment is used LRU bit 4, selectors 5, 6-1 to 6-4, 9 and compartment selecting means 7 for selecting from which LRU bit the data is to be stored at the time of block loading, hits of each compartment, Comparators 8-1 and 8-2 for detecting mishits
, 8-3, 8-4 and the LRU bit changing means 10.

Next, the operation of the embodiment of the present invention will be described. Normally, this cache behaves like a normal cache as follows. Although the normal operation of the cache is well known, the outline thereof will be described. When the central processing unit performs the main memory read, a part of the read address stored in the main memory address register 1 is set as the set address 101 to the address array 2-. 1 to 2-4 and data array 3-1 to 3-4
The corresponding sets are read out, and the address portions 102 other than the set address 101 of the read address and the read contents of the set of the address array 2 are compared by the comparators 8-1 to 8-4.

If there is a matching compartment,
The contents of the corresponding compartment of the data array 3 are read out to the central processing unit (not shown) through the selector 9. If there is no matching compartment, a cache miss occurs and the target main memory data does not exist in the cache. Therefore, the target data is fetched from the main memory into the cache by block load.

At this time, which compartment is to receive the data is determined by the LRU bit 4. LR
The U bit 4 exists for each set, but one of them will be described. In the case of four compartments like the cache of this example, the LRU bit 4 is composed of 6 bits. If each bit is a, b, c, d, e, f,
Each bit has the following meaning so that the most referenced compartment from these can be selected.

A: Compartments 2-1 and 3-1 are 2-2
, 3-2 newer than 0b …… Compartments 2-1 and 3-1 are 2-3, newer than 3-3 0c …… Compartments 2-1 and 3-1 are 2-4, 3-4 Newer time 0 d …… Compartments 2-2 and 3-2 are newer than 2-3 and 3-3 0 e …… Compartments 2-2 and 3-2 are newer than 2-4 and 3-4 0 f ... Compartments 2-3, 3-3 are newer than 2-4, 3-4 0 These bits are LRU each time the cache is referenced.
It is updated by the changing unit 10.

Since the selectors 6-1 to 6-4 normally select the LRU bit 4 and output it to the compartment selecting means 7, the compartment selecting means 7 outputs the LRU bit 4 to the compartment selecting means 7.
The oldest compartment is selected from and the block is loaded into that compartment.

When the central processing unit writes in the main memory,
When the corresponding data is in the cache, there is a method of rewriting the data in the cache and then the main memory, a method of invalidating the corresponding set in the cache and then rewriting the main memory, etc. Since this is not the subject of the present invention, detailed description thereof will be omitted.

The operation is as follows when the compartment in which the block load data is not always stored or the block load data is always stored is designated by the instruction of the software or the firmware. Here, the case where the compartments 2-1 and 3-1 are designated targets will be described.

(A) In a mode in which block load data is not always stored; "0" is output from the selector 5 according to an instruction from software or firmware. further,
Selector 6 according to software or firmware instructions
The output of the selector 5 is selected as 1 to 6-4 and output by the compartment selecting means 7. As a result, it appears to the compartment selecting means 7 that a, b and c of the LRU bit 4 are always "0". In other words, compartments 2-1 and 3-1 were last referenced more recently than other compartments.

Therefore, no block load data is stored in the compartments 2-1 and 3-1. The data stored in compartments 2-1 and 3-1 will always have a cache hit during this mode.

(B) In a mode in which block load data is always stored; "1" is output from the selector 5 according to an instruction from software or firmware. In addition, the selector 6-1 is activated by software or firmware instructions.
The output of the selector 5 is selected for 6-6 and output to the compartment selecting means 7. As a result, it appears to the compartment selection means 7 that a, b, and c of the LRU bit 4 are always "1". I.e. compartment
2-1 and 3-1 means that the last referenced time is earlier than other compartments.

Therefore, the block load data is always stored in the compartments 2-1 and 3-1. In this mode, specific data can be stored in compartments 2-1 and 3-1.

With the above configuration, in the software program or the firmware program, a routine that is not frequently used but is required to have a high processing speed (a peripheral device that is rarely used but operates at a very high speed is used). If a routine to be controlled exists), the routine is stored in a specific compartment by reading the routine from the main memory in the mode of (b) above, and the routine is always cached by entering the mode of (a) above. Since it exists inside, it can be executed at a place requiring high-speed processing without degrading performance.

[0024]

According to the present invention, in a software program or a firmware program stored in the main memory, a routine which is not frequently used but requires extremely high speed (is used). If there is a routine that controls a peripheral device that operates at a very low speed but operates very fast, make sure that the routine always exists in the cache to shorten the large read time to main memory and reduce performance. The effect is that it can be prevented.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

[Explanation of symbols]

 1 Address Register 2 Address Array 2-1 to 2-4 Address Compartment 3 Data Array 3-1 to 3-4 Data Compartment 4 LRU Bits 6-1 to 6-4 Selector 7 Compartment Selector 8 Comparator 9 Selector 10 LRU change means

Claims (2)

[Claims] 1. A cache compartment selection control device for a cache having a plurality of compartments configured to store a block copy of storage data in main storage and indexed by a part of the main storage address, wherein a specific compartment is designated by an external command. A cache compartment selection control device comprising means for forcibly performing load control of block data. 2. The cache compartment selection control device according to claim 1, further comprising means for forcibly performing a block data load prohibition control for a specific compartment by an external command.