JPH0666456B2 - Contact connection structure - Google Patents

Description

The present invention relates to a structure of contact connection of wiring to a semiconductor region of a semiconductor device.

[Prior Art] Integrated circuits formed on a semiconductor substrate, particularly a silicon substrate, are becoming highly integrated and large in capacity, and in integrated circuits such as memory devices, the degree of integration is increasing to 4 megabits or more. ing. With the increase in capacity, the occupied area per element must be reduced as much as possible. For example, in a dynamic random access memory (hereinafter abbreviated as DRAM), the occupied area of one memory cell that stores information is 80 to 100 μm ² in 64K DRAM, whereas about 10 μm ² is required in 4Mbit DRAM. There is. With the miniaturization of elements,
The size of the MOS transistor that constitutes the memory cell must be necessarily reduced, and not only the gate length and the gate width must be reduced, but also the width of the diffusion layer serving as the source or the drain must be reduced. Further, from the viewpoint of suppressing the short channel effect of the MOS transistor, it is necessary to make the depth of the diffusion layer shallow. Thus, if the depth of the diffusion layer is made shallow or the width of the diffusion layer is made small, the resistance of the diffusion layer increases and the resistance component contributing to the element also increases. Since the electric signal transmitted through the wiring is determined by the resistance and capacitance of the wiring, the resistance of the wiring must be minimized.

In order to solve this problem, it is considered that the diffusion layer is lined with a low resistance metal or silicide to reduce the resistance. Titanium silicide, in particular, has the lowest resistance among silicides and (SELF-ALIGNED TITANIUM S
ILICID-ATION OF SUB MICRON MOS DEVICES BY RAPID L
AMP ANEALING: IEDM Tech.Dig., Pp.130-133, 198 4)
It is very useful for device formation in that titanium silicide can be formed on the gate electrode and the diffusion layer in a self-aligned manner as reported in (1). On the other hand, the diffusion layer and the wiring are normally electrically connected by contacting the diffusion layer having a high concentration impurity with the wiring metal to prevent the resistance from increasing due to the Schottky barrier, but to lower the resistance. Is most effective in metal-to-metal contact. Therefore, the resistance can be reduced most if the metal or silicide lined in the diffusion layer is in contact with the wiring metal extending from the contact hole to the interlayer insulating film, and the parasitic resistance is reduced to reduce the circuit operation. Higher speed can be achieved. As described above, it is extremely effective to manufacture a high-performance integrated circuit to connect the metal lined with the diffusion layer or the silicide layer and the metal wiring extending from the contact to the interlayer insulating film only by metallic contact. It is considered to be a means.

[Problems to be solved by the invention]

However, the conventional diffusion layer backing described above is
As shown in the figure, the silicide layer 104 formed as a lining on the diffusion layer 103 on the n ⁺ diffusion layer 103 is removed by etching when opening the contact hole 107, or removed by pretreatment using hydrofluoric acid or the like. , The silicide layer 104 is not in direct contact with the upper metal wiring 108, and the contact resistivity is 10 ⁻⁶ Ωc.
There is a problem that it cannot be lower than m ² . The contact resistivity of 10 ^-6 Ωcm ² means that the resistance is 100 Ω for each contact having an opening of 1 μm × 1 μm, and the resistance further increases in the so-called submicron size of 1 μm or less. Resulting in. From the viewpoint of suppressing wiring delay, it is desirable that the resistance be smaller.

On the other hand, the conventional diffusion layer lining described above has a problem that it is necessary to simultaneously satisfy the contradictory requirements of the fine resistance and the low resistance. That is, when metallic titanium is grown on the silicon substrate to line the diffusion layer and is silicified by reacting with the substrate silicon,
It is known that titanium is silicidized by taking in substrate silicon. That is, when a very thin pn junction is formed on a substrate and titanium silicide is formed thereon,
Titanium silicide destroys the pn junction, increasing the junction leak at the pn junction. In order to prevent this, in addition to the method of deepening the diffusion layer, to the extent that the junction of the silicon substrate is not destroyed during the silicidation reaction of titanium,
The titanium film thickness must be reduced. However, the wiring of the diffusion layer and the upper layer is formed by opening a contact hole through the interlayer film and filling the contact hole with a substance having high conductivity.

By the way, in high-density integrated LSI, the wiring interval of the upper layer wiring is also narrowed, so the interlayer film minimizes the unevenness of the base,
The surface should be as flat as possible. As described above, silicidation of titanium has the advantage that a low-resistance silicide layer can be formed on the gate and the diffusion layer in a self-aligned manner. Since the planar heights of the two are different from each other, if a contact hole is to be opened in this portion, the etching is different between the gate portion and the portion on the diffusion layer. That is, when the contact hole is opened on the diffusion layer, the gate portion is over-etched. Since the titanium silicide cannot be made thick as described above, the titanium silicide is inevitably removed from the overetched portion. As for the contact between substances, the contact between metal is the lowest. When using a wiring having a polycide structure, the underlying polysilicon is exposed when the titanium silicide is removed by overetching. A metal such as tungsten can be buried in the contact hole, but since the semiconductor and the metal come into contact with each other, a Schottky junction is formed, and even if the impurity concentration is slightly lowered, the resistance of the contact portion is increased, which is preferable in circuit operation. Absent. The present invention aims to provide a wiring method that solves the above problems.

[Means for solving problems]

The contact connection structure of the present invention has a high-concentration impurity region provided on one main surface of a semiconductor substrate, a metal silicide layer selectively formed on the high-concentration impurity region, and a metal silicide layer selectively formed on the metal silicide layer. A high-melting-point metal film, an interlayer insulating film having an opening reaching the high-melting-point metal film, and a wiring metal provided in the opening to maintain metal contact with the high-melting-point metal film, The refractory metal film is formed to be thicker than 2000 liters, and the openings are formed in the thickness direction from the surface of the refractory metal film.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1 is a sectional view of an element showing a wiring structure of a first embodiment of the present invention, which is a silicon substrate 101, an n ⁺ diffusion layer 103, a first metal conductive film 104, and a selectively formed second Of the metal conductive film 105, the interlayer insulating film 106, the contact hole 107, and the aluminum wiring 108.

2 (a) to (f) are views for explaining a manufacturing process for forming the wiring structure according to the present invention shown in FIG. 1, and as an example, a silicon substrate having p-type conductivity as a semiconductor substrate. An example of forming a wiring structure using is shown. In the p-channel type, n may be replaced with p. In this embodiment, a method of forming a wiring structure using a silicon substrate will be described. However, even if the semiconductor substrate is a compound semiconductor substrate such as GaAs, the wiring structure according to the present invention can be formed by the same steps.

An element isolation silicon oxide film 102 is formed on the silicon substrate 101 by the well-known LOCOS process (FIG. 2A).

An n ⁺ diffusion layer 103 is formed by a well-known ion implantation method in a region where the element isolation silicon oxide film 102 is not formed (FIG. 2B).

Next, the first metal conductive film 104 is selectively formed only on the exposed portion of the silicon substrate. As the first metal conductive film 104, for example, titanium silicide may be used. In order to form this structure, first, metal titanium is formed on the silicon substrate 101 by a sputtering deposition method or the like to have a thickness of about 500 Å to 1000 Å. Next, titanium metal is reacted with silicon of the n ⁺ diffusion layer 103 by lamp annealing to form titanium silicide.

At this time, by performing annealing in a nitrogen atmosphere, titanium on the element isolation silicon oxide film 102 becomes titanium nitride, and this titanium nitride is dissolved in an ammonia-hydrogen peroxide solution, so that the element isolation silicon oxide film 102 is The upper titanium nitride is dissolved and removed, and a structure as shown in FIG. 2 (c) is obtained. After that, annealing may be further performed in a nitrogen atmosphere to leave the surface of titanium silicide as titanium nitride.

Next, as shown in FIG. 2D, the second metal conductive film 105 is selectively grown only on the first metal conductive film 104. Second
As the metal conductive film 105, for example, tungsten that can be selectively grown may be used. Tungsten thickness is 20
It is good if it is about 00 to 3000Å.

Next, an interlayer film 106 is grown, a planarization is performed using an organic material, and then a contact hole 107 is opened (FIG. 2 (e)).

Next, as shown in FIG. 2 (f), the upper layer metal wiring 108 is formed to complete the wiring structure. As the material of the upper wiring 108, for example, aluminum may be used, or a material having metal conductivity such as silicide may be used.

FIGS. 3A to 3G are sectional views showing the second embodiment of the present invention in the order of manufacturing steps thereof. In this embodiment, the wiring structure according to the present invention is used as an LDD-MOSFET (LIGHT-LY DOPED DRAIN M
An example applied to OSFET) will be described.

An element isolation silicon oxide film 102 is formed on a semiconductor substrate 101 by a well-known LOCOS process (FIG. 3A).

Next, a gate oxide film 109 is formed on the silicon substrate 101 on which the element isolation silicon oxide film 102 is not formed, and polysilicon to be the gate electrode 110 is formed. After the polysilicon to be the gate electrode is doped with impurities, the polysilicon is left only in the portion to be the electrode as shown in FIG. 3B by a well-known photolithography process.

Next, the insulating film sidewall 111 is formed on the sidewall of the gate electrode 110. In order to form the insulating film side wall, for example, a silicon oxide film is vapor-grown and the silicon oxide film is etched back to form the insulating film side wall 111 on the side surface of the gate electrode 110 (see FIG. 3). (C)).

Next, as shown in FIG. 3 (d), the first metal conductive film 104 is selectively formed only on the exposed portions of the gate electrode polysilicon and the silicon substrate, and becomes the source or drain. ^{The +} diffusion layer 103 is formed by an ion implantation method and a heat treatment for diffusing impurities (FIG. 3 (d)).
As the first metal conductive film 104, for example, titanium silicide may be used. The titanium silicide layer may be formed by the method described in the first embodiment.

Next, as shown in FIG. 3E, the second metal conductive film 105 is selectively grown only on the first metal conductive film 104 (third metal).
Figure (e)). As the second metal conductive film 105, for example, tungsten may be used. The film thickness of tungsten is 2000
Å ~ 3000Å is enough.

Next, an interlayer film 106 is grown, a planarization is performed using an organic material, and then a contact hole 107 is opened (FIG. 3 (f)).

Next, the contact hole 107 is filled with a low resistance metal 112. The low resistance metal 112 may be formed by selective growth of tungsten or may be filled with nickel by electroless plating of nickel. Next, the upper wiring 108 is formed to complete the wiring (FIG. 3 (g)). Aluminum may be used for the upper metal wiring, for example.

The low resistance contact connection structure according to the present invention can be realized in the same manner even if tungsten or tungsten silicide thinly grown on tungsten and reacted with the n ⁺ diffusion layer 103 is used for the first metal conductive film 104.

〔The invention's effect〕

By the wiring structure and the wiring forming method according to the present invention, the contact resistance can be reduced to about 10 ⁻⁷ Ωcm ² , and the delay time of the circuit operation due to the wiring resistance can be shortened. Further, in the present invention, since the refractory metal film is formed thicker than 2000Å, the surface of the refractory metal film is etched to form the holes in the thickness direction when the holes are formed in the interlayer insulating film. Even in the case of opening, it is possible to prevent the opening from reaching the lower metal silicide layer. On the contrary, by partially advancing the opening on the surface of the refractory metal film in the thickness direction, the substantial thickness of the refractory metal film in this part can be reduced, and the gap with the metal silicide layer can be reduced. It is also possible to reduce the electric resistance of.

[Brief description of drawings]

FIG. 1 is a vertical cross-sectional view of a contact connection structure according to a first embodiment of the present invention, FIG. 4 is a vertical cross-sectional view of a contact connection structure according to the prior art, and FIGS. 2 (a) to (f) are views of the present invention. FIGS. 3A to 3G are vertical sectional views showing main steps of manufacturing the contact connection structure of the first embodiment, and FIGS. 3A to 3G show main steps of manufacturing the contact connection structure of the second embodiment of the present invention. FIG. 101 ... Silicon substrate, 102 ... Element isolation silicon oxide film, 103 ... N ⁺ diffusion layer, 104 ... First metal conductive film, 10
5 ... second metal conductive film, 106 ... interlayer film, 107 ... contact hole, 108 ... metal wiring, 109 ... gate oxide film,
110 …… Gate electrode, 111 …… Insulating film sidewall, 11
2 …… Low resistance metal.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location H01L 29/784

Claims (1)

[Claims] 1. A high concentration impurity region provided on one main surface of a semiconductor substrate, a metal silicide layer selectively formed on the high concentration impurity region, and a metal silicide layer selectively formed on the metal silicide layer. A high melting point metal film, an interlayer insulating film having an opening reaching the high melting point metal film, and a wiring metal provided in the opening to maintain metal contact with the high melting point metal film. The contact connection structure, wherein the metal film is formed thicker than 2000Å, and the opening is formed in the thickness direction from the surface of the refractory metal film.