JPH0666063U - Hybrid integrated circuit device - Google Patents

Hybrid integrated circuit device

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Publication number
JPH0666063U
JPH0666063U JP5163691U JP5163691U JPH0666063U JP H0666063 U JPH0666063 U JP H0666063U JP 5163691 U JP5163691 U JP 5163691U JP 5163691 U JP5163691 U JP 5163691U JP H0666063 U JPH0666063 U JP H0666063U
Authority
JP
Japan
Prior art keywords
integrated circuit
insulator
circuit device
sil
terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP5163691U
Other languages
Japanese (ja)
Other versions
JPH0739260Y2 (en
Inventor
久司 金井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Taiyo Yuden Co Ltd
Original Assignee
Taiyo Yuden Co Ltd
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Filing date
Publication date
Application filed by Taiyo Yuden Co Ltd filed Critical Taiyo Yuden Co Ltd
Priority to JP5163691U priority Critical patent/JPH0739260Y2/en
Publication of JPH0666063U publication Critical patent/JPH0666063U/en
Application granted granted Critical
Publication of JPH0739260Y2 publication Critical patent/JPH0739260Y2/en
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Expired - Lifetime legal-status Critical Current

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Abstract

(57)【要約】 (修正有) 【構成】 SIL集積回路基板1の端部に列状に配置さ
れた複数の端子リード3を柱状または板状の絶縁体4の
両側に設けられた複数の溝5に沿って挿入し、上記絶縁
体4の下面に延びた上記端子リード3の先端を親基板側
に設けられた半田ランド上に載せ、半田付けできるよう
にする。 【効果】 両基板を強固に面実装することが可能とな
り、また絶縁体にフェライトコアを採用することによっ
てノイズ対策も可能である。
(57) [Summary] (Modified) [Configuration] A plurality of terminal leads 3 arranged in rows at the end of the SIL integrated circuit board 1 are provided on both sides of a columnar or plate-shaped insulator 4. It is inserted along the groove 5 and the tip of the terminal lead 3 extending to the lower surface of the insulator 4 is placed on a solder land provided on the mother board side so that soldering can be performed. [Effect] Both boards can be firmly surface-mounted, and noise can be prevented by adopting a ferrite core as an insulator.

Description

【考案の詳細な説明】[Detailed description of the device]

【0001】[0001]

【産業上の利用分野】[Industrial applications]

本考案は、面実装が可能なシングルインライン型混成集積回路装置に関する。 The present invention relates to a single in-line type hybrid integrated circuit device capable of surface mounting.

【0002】[0002]

【従来の技術】[Prior art]

特定の機能を有する混成集積回路基板の一方の辺に端子リードを一列に取付け たパッケージタイプの回路装置、いわゆるシングルインライン型混成集積回路装 置(以下これを「SIL集積回路装置」という)を他の混成集積回路基板(以下 これを「親基板」という)上に装着し、上記端子リードを介してSIL集積回路 装置と親基板とを電気的に接続する手法がある。以下この接続方法を図5(a) 、(b)にしたがって説明する。 A package type circuit device in which terminal leads are mounted in a row on one side of a hybrid integrated circuit board having a specific function, a so-called single-inline type hybrid integrated circuit device (hereinafter referred to as "SIL integrated circuit device") There is a method of mounting on a hybrid integrated circuit board (hereinafter referred to as "parent board") and electrically connecting the SIL integrated circuit device and the parent board via the terminal leads. This connection method will be described below with reference to FIGS. 5 (a) and 5 (b).

【0003】 SIL集積回路装置1はその主面の一つの端部に端子リード用半田ランド2が 一列に形成され、ここに端子リード3の一端が半田付けされ、該端子リード3が 該回路装置1の主面に対して平行に導出されている。一方親基板5は上記SIL 集積回路装置1の端子リード3が挿入されるスルーホール6を備え、ここに上記 端子リード3が挿入された後、フロー半田付け法により、電気的、機械的に端子 リードを接続・固定することで、SIL集積回路装置1が親基板に実装される。 また、混成集積回路装置に外来ノイズが混入したり、あるいは上記回路装置自身 から発するノイズによって他の回路に影響を与えるのを防止するために、図5( b)に示す如く、フェライトコア7に複数の孔8を設け、該孔8に上記端子リー ド3を挿入した後に親基板5に実装してノイズの吸収を計ることも行なわれてい る。In the SIL integrated circuit device 1, terminal lead solder lands 2 are formed in a line at one end of the main surface thereof, one end of the terminal lead 3 is soldered thereto, and the terminal lead 3 is connected to the circuit device. 1 is derived parallel to the main surface. On the other hand, the parent board 5 has through holes 6 into which the terminal leads 3 of the SIL integrated circuit device 1 are inserted, and after the terminal leads 3 are inserted therein, the terminals are electrically and mechanically formed by a flow soldering method. The SIL integrated circuit device 1 is mounted on the parent board by connecting and fixing the leads. Further, in order to prevent external noise from mixing into the hybrid integrated circuit device or affecting other circuits due to the noise generated from the circuit device itself, the ferrite core 7 is provided with the ferrite core 7 as shown in FIG. 5 (b). It is also practiced to provide a plurality of holes 8, insert the terminal lead 3 into the holes 8 and then mount the terminal lead 3 on the main board 5 to absorb noise.

【0004】[0004]

【考案が解決しようとしている課題】[Problems that the device is trying to solve]

近年、混成集積回路基板上に実装される各種電子部品は面実装方法によるもの が多くなっている。この方法は電子部品を装着する上記基板上の半田ランドにあ らかじめ一定量の半田を印刷するため、リフロー後に過剰なハンダによる端子間 のブリッジ現象が生ずることがなく、信頼性のある混成集積回路が実現できると 言う利点がある。 In recent years, various electronic components mounted on the hybrid integrated circuit board have been more and more manufactured by the surface mounting method. Since this method pre-prints a fixed amount of solder on the solder lands on the above-mentioned board on which electronic components are mounted, there is no bridging between terminals due to excessive solder after reflow, resulting in a reliable hybrid structure. There is an advantage that an integrated circuit can be realized.

【0005】 しかしながら、SIL集積回路装置を親基板に対して面実装を施すことは困難 である。例えば、図6はSIL集積回路装置が面実装されている状態の概念図を 示すもので、同図から明らかなように、SIL集積回路装置1を面実装可能にし ようとすると、端子リード3を曲げ加工する必要がある。しかし図6に示すよう にSIL集積回路装置1の主面に垂直に端子リード3を揃えて曲げることは困難 であり、曲げ角度が揃っていないと親基板5上の半田ランド9上に精度よく端子 リード3を載せることができない。 また上記した方法で面実装が可能としても、端子リード3に何等かの外力に対 する保護対策が必要であるが、そのような保護対策は実質的に困難である。However, it is difficult to surface-mount the SIL integrated circuit device on the parent board. For example, FIG. 6 is a conceptual diagram showing a state in which the SIL integrated circuit device is surface-mounted. As is apparent from FIG. 6, when the SIL integrated circuit device 1 is to be surface-mounted, the terminal leads 3 are It needs to be bent. However, as shown in FIG. 6, it is difficult to bend the terminal leads 3 aligned perpendicularly to the main surface of the SIL integrated circuit device 1. If the bending angles are not aligned, the solder lands 9 on the parent substrate 5 can be accurately aligned. Terminal lead 3 cannot be placed. Even if surface mounting is possible by the above-mentioned method, the terminal lead 3 must be protected against some external force, but such protection is substantially difficult.

【0006】 さらに図5(b)に示す如く、SIL集積回路装置をノイズ対策を施して親基 板に実装する場合、上記SIL集積回路の端子リードをフェライトコアに通して から親基板上の端子リード挿入用スルーホールに挿入する工程となる。この場合 の実装作業は手作業となり、自動実装が出来ないことから、非常に効率の悪い実 装作業が要求される。またSIL集積回路装置の基板面を親基板面に対して平行 な姿勢で実装する方法があるが、この方法はSIL集積回路装置の面積が広いた め、親基板側に設けられる半田ランドの位置決めのために、親基板側の回路パタ ーン作成時に大きな制約があるばかりでなく、SIL集積回路装置の片側に端子 リードを備えた場合は、その反対側の端部に補強用の固定手段が必要となる。Further, as shown in FIG. 5B, when the SIL integrated circuit device is mounted on the parent board by taking measures against noise, the terminal leads of the SIL integrated circuit are passed through the ferrite core and then the terminals on the parent board. This is the step of inserting into the lead insertion through hole. Since the mounting work in this case is manual work and automatic mounting cannot be performed, very inefficient mounting work is required. There is also a method of mounting the board surface of the SIL integrated circuit device in a posture parallel to the parent board surface. However, this method has a large area of the SIL integrated circuit device, and therefore the positioning of the solder land provided on the parent board side is performed. Therefore, not only is there a great restriction when creating a circuit pattern on the main board side, but when a terminal lead is provided on one side of the SIL integrated circuit device, a fixing means for reinforcement is provided at the end on the opposite side. Will be needed.

【0007】 そこで本考案の目的は前記従来技術における各種問題に鑑み、SIL集積回路 装置を親基板に対して面実装が可能な信頼性のある混成集積回路装置を提供する ことにある。In view of the above-mentioned problems in the prior art, an object of the present invention is to provide a reliable hybrid integrated circuit device capable of surface mounting the SIL integrated circuit device on a parent substrate.

【0008】[0008]

【課題を解決するための手段】[Means for Solving the Problems]

上記の本考案の目的を達成するために、本考案は、複数の端子リードが一定の 間隔で一列状に導出された回路装置と、少なくとも上記端子リードの数と同じ数 の溝が両側に形成された柱状または板状の絶縁体とを有し、上記端子リードは上 記絶縁体の両側の溝に係合され、保持されると共に、該端子リードの先端側が絶 縁体の底面に導出されていることを特徴とする混成集積回路装置を提供する。こ の場合において、前記絶縁体は磁性体で形成することができる。 In order to achieve the above object of the present invention, the present invention provides a circuit device in which a plurality of terminal leads are led out in a row at regular intervals, and at least as many grooves as the number of the terminal leads are formed on both sides. The terminal lead is engaged with and held in the grooves on both sides of the insulator, and the tip end side of the terminal lead is led out to the bottom surface of the insulator. A hybrid integrated circuit device is provided. In this case, the insulator may be made of a magnetic material.

【0009】[0009]

【作用】[Action]

本考案によれば、従来困難とされていたSIL集積回路装置の親基板への面実 装が可能となり、さらにチップ部品等と同様に自動実装も可能となる。即ち、S IL集積回路装置からの端子リードが絶縁体の両側の溝に係合され、保持されて いるため、上記絶縁体は保持具の機能を有し、外力や振動等が加わっても端子リ ードが切断されるおそれがなくなる。また端子リードの曲げ加工時は上記絶縁体 が曲げ治具の役をなすため、曲げ加工が容易になると共に、曲げ加工精度が向上 し、それによって半田接合時の位置決め精度が高くなる。 According to the present invention, it is possible to mount the SIL integrated circuit device on the parent board, which has been difficult to achieve in the past, and to automatically mount the chip as well as the chip parts. That is, since the terminal leads from the SIL integrated circuit device are engaged with and held in the grooves on both sides of the insulator, the insulator has a function of a holder and the terminal is not affected by external force or vibration. There is no risk of the lead being disconnected. Further, when the terminal lead is bent, the above-mentioned insulator serves as a bending jig, so that the bending process is facilitated and the bending accuracy is improved, which results in higher positioning accuracy when soldering.

【0010】 そしてSIL集積回路装置からの端子リードを絶縁体の底面の溝に沿って内側 に折り曲げているため、端子リードの先端を親基板上の半田ランドに位置合わせ して、絶縁体の底面を親基板上に載せれば、容易にリフローを行うことが可能と なる。 さらに上記絶縁体にフェライトを用いれば自己回路から発するノイズ、あるい は外来ノイズも上記フェライトによって吸収されるため、別にフェライトコア等 を用いる必要がなくなる。Since the terminal lead from the SIL integrated circuit device is bent inward along the groove on the bottom surface of the insulator, the tip of the terminal lead is aligned with the solder land on the mother board, and the bottom surface of the insulator is aligned. If the is mounted on the parent board, reflow can be easily performed. Further, if ferrite is used for the insulator, noise generated from the self circuit or external noise is also absorbed by the ferrite, so that it is not necessary to separately use a ferrite core or the like.

【0011】[0011]

【実施例】【Example】

次ぎに、本考案の一実施例を図1、図2にしたがって説明する。なお、これら の図面において、図5、6に示す符号と同じものは、同一記号で示した。 SIL集積回路装置1の端部に設けられた複数の半田ランド2にそれぞれ複数 の端子リード3が列状に半田付けされている点は、既に述べた通りである。本考 案では、この他に絶縁体10を用意する。この絶縁体10は、断面が二等辺三角 形となる三角柱であり、この三角形の両側の二等辺部に上記端子リード3のピッ チ間隔の2倍の間隔で複数の溝11が交互に設けられ、これらの溝11は、絶縁 体10の底面に連なっている。そして上記端子リード3はこの両側に溝11に沿 って交互に挿入され、さらに溝11に沿って絶縁体10の底面側に曲げ加工され る。 Next, an embodiment of the present invention will be described with reference to FIGS. In these drawings, the same symbols as those shown in FIGS. 5 and 6 are designated by the same symbols. As described above, the plurality of terminal lands 3 are soldered in rows to the plurality of solder lands 2 provided at the end of the SIL integrated circuit device 1, respectively. In addition to this, the insulator 10 is prepared in the present proposal. The insulator 10 is a triangular prism whose cross section is an isosceles triangle, and a plurality of grooves 11 are alternately provided on the both sides of the triangle at an interval equal to twice the pitch of the terminal leads 3. The grooves 11 are connected to the bottom surface of the insulator 10. The terminal leads 3 are alternately inserted on both sides along the groove 11, and further bent along the groove 11 to the bottom surface side of the insulator 10.

【0012】 以上の構成によれば上記絶縁体10は上記端子リード3によって挟持される形 となり、また端子リード3は絶縁体10の溝11の中に挿入されているため、端 子リード3の両端が半田で固定された状態ではコアタイプの構造となり、それに よって、外力並びに振動等による端子リード3の断線、あるいは曲がりの問題が 解決される。さらに上記絶縁体10は端子リード3の曲げ加工時の治具となり得 、それによって曲げ加工精度の向上並びに曲げ角度が均一となり、SIL集積回 路装置の面実装がより確実に行えるようになる。According to the above configuration, the insulator 10 is sandwiched between the terminal leads 3 and the terminal lead 3 is inserted into the groove 11 of the insulator 10. When both ends are fixed with solder, the structure is of a core type, which solves the problem of disconnection or bending of the terminal lead 3 due to external force or vibration. Further, the insulator 10 can be used as a jig for bending the terminal lead 3, thereby improving the bending accuracy and making the bending angle uniform, so that the surface mounting of the SIL integrated circuit device can be performed more reliably.

【0013】 また本考案の混成集積回路装置は該回路に混入する外来ノイズ、あるいは該回 路自身から発するノイズの影響を避けるために上記絶縁体10をフェライト等の 磁性体で形成すれば、この絶縁体10をノイズ除去用の従来のフェライトコアに 置き換えることができる。In the hybrid integrated circuit device of the present invention, if the insulator 10 is made of a magnetic material such as ferrite in order to avoid the influence of external noise mixed in the circuit or noise generated from the circuit itself, The insulator 10 can be replaced with a conventional ferrite core for noise removal.

【0014】 図3は本考案の他の実施例を示す図である。ここで絶縁体10は板状の形をし 、絶縁体10の両端部13にSIL混成集積回路装置1の端子リード3の倍のピ ッチで溝11が交互に設けられている。そして、SIL混成集積回路装置1の端 子リード3は板状の絶縁体10の面に沿って曲げられ、さらに絶縁体10の両側 部で、図4に示すように、溝11の中に挿入されると共に、該溝11の中で絶縁 体10の底面14側へ内側に折り曲げられる。曲げられた上記底面14側にある 端子リード3の先端側は図示を省略しているが、この先端側が親基板側に設けら れている半田ランド上に位置決めされ、リフローによってSIL集積回路装置1 が親基板に面実装される。このような板状の絶縁体を用いることにより、親基板 に実装後のSIL集積回路装置の高さは全体として低く構成することが可能とな り、より機械的な安定性が増す。FIG. 3 is a view showing another embodiment of the present invention. Here, the insulator 10 has a plate shape, and the grooves 11 are alternately provided at both ends 13 of the insulator 10 with a pitch twice as large as the terminal lead 3 of the SIL hybrid integrated circuit device 1. Then, the terminal lead 3 of the SIL hybrid integrated circuit device 1 is bent along the surface of the plate-shaped insulator 10, and is inserted into the groove 11 on both sides of the insulator 10 as shown in FIG. At the same time, it is bent inward in the groove 11 toward the bottom surface 14 side of the insulator 10. Although not shown, the tip side of the bent terminal lead 3 on the bottom surface 14 side is positioned on a solder land provided on the parent board side, and the SIL integrated circuit device 1 is reflowed. Are surface-mounted on the parent board. By using such a plate-shaped insulator, the height of the SIL integrated circuit device mounted on the parent board can be made low as a whole, and the mechanical stability is further increased.

【0015】 なお、図3、図4は絶縁体10の両側部13のみに溝11を設けた場合を示し ているが絶縁体10の平面部分に溝を設け、その中に端子リードを係合しても良 い。また、上記板状の絶縁体10をフェライトで形成すれば、前記と同様にして ノイズの除去作用を有することは言うまでもない。さらに、端子リード3を絶縁 体10の両側に交互に曲げているが、例えば、2本おきや3本おきに曲げたり、 或は両端の端子リード3を一方の側に、その中間部の端子リード3を他方の側に 曲げることができるのは、いうまでない。Although FIGS. 3 and 4 show the case where the groove 11 is provided only on the both side portions 13 of the insulator 10, the groove is provided on the plane portion of the insulator 10 and the terminal lead is engaged therein. You can do it. Needless to say, if the plate-shaped insulator 10 is made of ferrite, it has a noise removing effect in the same manner as described above. Further, the terminal leads 3 are alternately bent on both sides of the insulator 10. For example, the terminal leads 3 may be bent every two or three, or the terminal leads 3 at both ends may be bent at one side and the terminals in the middle thereof may be bent. It goes without saying that the lead 3 can be bent to the other side.

【0016】[0016]

【考案の効果】[Effect of device]

以上の説明から明らかなように、本考案による混成集積回路装置によれば、S IL集積回路装置を親基板に実装する際、絶縁体の主面に端子リードを挿入する 溝を備え、且つ端子リードが上記絶縁体を挟持する如く構成しているので、外力 に対して端子リードの曲がり、あるいは変形することが無くなり、上記両基板間 の信頼性のある面実装が実現可能となる。 As is apparent from the above description, according to the hybrid integrated circuit device of the present invention, when the SIL integrated circuit device is mounted on the parent substrate, the main surface of the insulator is provided with the groove for inserting the terminal lead, and the terminal is formed. Since the leads are configured to sandwich the insulator, the terminal leads are not bent or deformed by external force, and reliable surface mounting between the two substrates can be realized.

【図面の簡単な説明】[Brief description of drawings]

【図1】本考案の一実施例によるSIL集積回路装置の
実装方法を説明するための斜視図である。
FIG. 1 is a perspective view illustrating a method of mounting a SIL integrated circuit device according to an embodiment of the present invention.

【図2】本考案の絶縁体の一実施例を示す斜視図であ
る。
FIG. 2 is a perspective view showing an embodiment of an insulator of the present invention.

【図3】本考案からなる他の実施例を示す図であり、
(a)はその斜視図、(b)は側面図である。
FIG. 3 is a view showing another embodiment of the present invention,
(A) is the perspective view, (b) is a side view.

【図4】同実施例を示す部分拡大斜視図である。FIG. 4 is a partially enlarged perspective view showing the same embodiment.

【図5】従来技術を用いた実装方法を説明するための斜
視図であり、(a)は挿入実装方法を示し、(b)はノ
イズ対策用のフェライトコアを用いる場合を示してい
る。
5A and 5B are perspective views for explaining a mounting method using a conventional technique, FIG. 5A shows an insertion mounting method, and FIG. 5B shows a case where a ferrite core for noise suppression is used.

【図6】従来技術のもとで面実装を行なった場合の説明
図である。
FIG. 6 is an explanatory diagram of a case where surface mounting is performed under the conventional technique.

【符号の説明】[Explanation of symbols]

1 SIL集積回路装置 3 端子リード 5 親基板 6 スルーホール 7 フェライトコア 10 絶縁体 11 溝 1 SIL Integrated Circuit Device 3 Terminal Lead 5 Parent Board 6 Through Hole 7 Ferrite Core 10 Insulator 11 Groove

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─────────────────────────────────────────────────── ───

【手続補正書】[Procedure amendment]

【提出日】平成3年7月20日[Submission date] July 20, 1991

【手続補正1】[Procedure Amendment 1]

【補正対象書類名】図面[Document name to be corrected] Drawing

【補正対象項目名】全図[Correction target item name] All drawings

【補正方法】変更[Correction method] Change

【補正内容】[Correction content]

【図1】 [Figure 1]

【図2】 [Fig. 2]

【図3】 [Figure 3]

【図4】 [Figure 4]

【図5】 [Figure 5]

【図6】 ─────────────────────────────────────────────────────
[Figure 6] ─────────────────────────────────────────────────── ───

【手続補正書】[Procedure amendment]

【提出日】平成6年3月14日[Submission date] March 14, 1994

【手続補正1】[Procedure Amendment 1]

【補正対象書類名】図面[Document name to be corrected] Drawing

【補正対象項目名】全図[Correction target item name] All drawings

【補正方法】変更[Correction method] Change

【補正内容】[Correction content]

【図1】 [Figure 1]

【図2】 [Fig. 2]

【図3】 [Figure 3]

【図4】 [Figure 4]

【図5】 [Figure 5]

【図6】 [Figure 6]

Claims (2)

【整理番号】 0030031−01 【実用新案登録請求の範囲】[Reference number] 003003-01 [Claims for utility model registration] 【請求項1】 複数の端子リードが一定の間隔で一列状
に導出された回路装置と、少なくとも上記端子リードの
数と同じ数の溝が両側に形成された柱状または板状の絶
縁体とを有し、上記端子リードは上記絶縁体の両側の溝
に係合され、保持されると共に、該端子リードの先端側
が絶縁体の底面に導出されていることを特徴とする混成
集積回路装置。
1. A circuit device in which a plurality of terminal leads are led out in a line at regular intervals, and a columnar or plate-shaped insulator having at least the same number of grooves as the number of the terminal leads formed on both sides. A hybrid integrated circuit device, wherein the terminal lead is engaged with and held in grooves on both sides of the insulator and the tip end side of the terminal lead is led to the bottom surface of the insulator.
【請求項2】 前記請求項1において、絶縁体が磁性体
であることを特徴とする混成集積回路装置。
2. The hybrid integrated circuit device according to claim 1, wherein the insulator is a magnetic body.
JP5163691U 1991-06-08 1991-06-08 Hybrid integrated circuit device Expired - Lifetime JPH0739260Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5163691U JPH0739260Y2 (en) 1991-06-08 1991-06-08 Hybrid integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5163691U JPH0739260Y2 (en) 1991-06-08 1991-06-08 Hybrid integrated circuit device

Publications (2)

Publication Number Publication Date
JPH0666063U true JPH0666063U (en) 1994-09-16
JPH0739260Y2 JPH0739260Y2 (en) 1995-09-06

Family

ID=12892338

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5163691U Expired - Lifetime JPH0739260Y2 (en) 1991-06-08 1991-06-08 Hybrid integrated circuit device

Country Status (1)

Country Link
JP (1) JPH0739260Y2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2023106863A (en) * 2022-01-21 2023-08-02 太陽インキ製造株式会社 Three-dimensional assembly circuit components and three-dimensional assembly circuit structure

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2023106863A (en) * 2022-01-21 2023-08-02 太陽インキ製造株式会社 Three-dimensional assembly circuit components and three-dimensional assembly circuit structure

Also Published As

Publication number Publication date
JPH0739260Y2 (en) 1995-09-06

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