JPH066398A - Demodulating device - Google Patents

Abstract

PURPOSE:To perform demodulation processing with one bit and reduce the size by providing plural delay means and a phase comparing means and outputting respective pieces of phase difference information from a prescribed phase comparing means. CONSTITUTION:A clock generating means 7 generates a clock which has a rate higher than the symbol rate of an input signal and a 1st sampling means samples the input signal in synchronism with the clock. Then the output signal of the sampling means 1 is delayed by one symbol through a 1st delay means 2. A 2nd sampling means 4 samples the output signal of the delay means 2 and its output is delayed by a 1/4 synchronism time of the intermediate frequency of the input signal through a 2nd delay means 5. A 1st phase comparing means 3 outputs information on the phase difference between the input signal and the output signal of the delay means 2 and a 2nd phase comparing means 6 outputs the phase difference signal between the input signal and the output signal of the delay means 5. Then the demodulation processing is performed with one bit, the constitution is simplified to reduce the size of a digital part, and the power consumption is lowered.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION The present invention relates to a π / 4 shift QPSK.
The present invention relates to a demodulator for digital mobile communication based on a modulation method.

[0002]

2. Description of the Related Art At present, in digital mobile communications such as mobile phones and car phones, a .pi. / 4 shift QPSK modulation method is standardized in the United States and Japan. π / 4 shift QP
In the SK demodulation method, differential detection is an excellent method in terms of detection sensitivity, anti-fading characteristics, and LSI feasibility.

FIG. 12 shows the configuration of a baseband differential detection device used in the π / 4 shift QPSK demodulation system. The modulated signal of frequency f0 is separated into orthogonal components by the orthogonal demodulation unit 121, and the harmonic components are removed by the low pass filter 122. Then, it is converted into a digital signal by the AD converter 123, and thereafter, processing is performed with a multi-bit digital signal.

The digital signal processing section comprises a digital root roll-off filter 124 and a baseband delay detection section 125.
The baseband differential detection unit is composed of a combination of a plurality of digital multipliers, digital adders, delay devices and the like. However, these circuits that perform multi-bit digital signal processing are not suitable for downsizing because of the huge circuit scale, and there is a problem in terms of low power consumption.

[0005]

SUMMARY OF THE INVENTION According to the present invention, an AD conversion section, a digital root roll-off filter, a digital signal processing section, etc. in a baseband differential detection apparatus of a π / 4 shift QPSK signal demodulation system is a small-sized demodulation apparatus. This was done in view of the fact that it is a major obstacle to the realization of low power consumption and low power consumption.

The present invention proposes a configuration in which the demodulation process is realized by 1 bit in the differential detection system in which the phase difference information of the carrier is directly detected from the zero crossing point of the limiter output signal, thereby reducing the size of the digital section. -It is an object of the present invention to provide a demodulation device capable of reducing power consumption.

[0007]

According to the present invention, there is provided a clock generating means for generating a clock having a rate higher than a symbol rate of an input signal, and a first sampling means for sampling the input signal in synchronization with the clock from the clock generating means. Sampling means, a first delay means for delaying the output signal from the first sampling means by one symbol, and an output signal from the first delay means in synchronization with the clock from the clock generating means. Second sampling means for sampling the input signal, the second delay means for delaying the output signal from the second sampling means by 1/4 cycle time of the intermediate frequency of the input signal, the input signal and the first
Second phase comparison means for outputting phase difference information between the output signal from the delay means and the second phase comparison information for outputting phase difference information between the input signal and the output signal from the second delay means. And a demodulation device including the means.

[0008]

In the present invention, the logical value corresponding to the phase difference between the input signal sampled by the sampling means operating at a clock faster than the symbol rate of the input signal and the input signal delayed by one symbol is obtained. Thus, demodulated data 1 can be obtained. Further, the demodulated data 2 can be obtained by obtaining the logical value corresponding to the phase difference between the sampled input signal delayed by 1/4 cycle of the intermediate frequency and the input signal.
With these two demodulated data, it is possible to obtain a π / 4 shift QPSK signal corresponding to the demodulated data.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings. Figure 1
FIG. 3 is a diagram showing a basic configuration of a demodulation device of the present invention.

The π / 4 shift QPSK modulation signal is subjected to the delay detection by observing the zero cross point (phase) of the π / 4 shift QPSK signal which has passed through the limiter by removing the intersymbol interference component in the preceding stage of the limiter. Is possible. At this time, since the signal that has passed through the limiter is 1 bit, digital signal processing can be performed without providing an AD converter.

In FIG. 1, the first sampling means 1
Operates at a clock rate sufficiently higher than the symbol rate of the input signal, and a plurality of signals are sampled at high speed with respect to the input of one symbol period. The output of the first sampling signal is delayed by one symbol of the input signal TS by the first delay means 2 in order to perform differential detection with the input signal. Then, the first phase comparison means 3 outputs the demodulated data 1 by detecting the phase difference between the input signal and the output from the first delay means.

The output from the first delay means is sampled by the second sampling means 4 at a clock rate sufficiently higher than the symbol rate of the input signal.
In particular, in the example shown in FIG. 1, since the clock generation means 7 generates a clock having a higher speed than the symbol rate of the input signal, the clock is used to operate the first and second sampling means. The output of the second sampling means is equal to 1 of the intermediate frequency f0 by the second delay means.
After being delayed by 1 / (4f0) for / 4 period, the second phase comparison means 6 detects the phase difference from the input signal. This phase difference information is output as demodulation data 2. FIG. 2 is a diagram showing a specific configuration example of the demodulation device of the present invention.

The first sampling means and the first delay means are constituted by the first shift register 21, and the second sampling means and the second delay means are constituted by the second shift register 22. It is assumed that these shift registers operate at a clock rate that is sufficiently higher than the symbol rate.

In order to operate the first shift register as a one-symbol delay device, the number of flip-flop stages, the operating speed, etc. are determined by the delay time relationship between the input signal and the output signal. For example, the one-symbol delay unit is configured to equalize the number of stages of the shift register and the clock rate standardized by the symbol rate.

The second shift register determines the number of flip-flop stages, the operating speed, etc. so that the second shift register operates as a 90 ° phase shifter. In particular, when the 90 ° phase shifter and the 1-symbol delay unit are composed of flip-flops operating at the same clock rate, TS / (4f0), where TS is 1 symbol delay and f 0 is an intermediate frequency delay. The delay amount should be determined.

With this configuration, the phase shift difference between the output signals of the first shift register 21 and the second shift register 22 has a phase shift difference of ¼ cycle time of the intermediate frequency. Therefore, the phase shift difference information can be detected by detecting the π / 4 shift QPSK signal that has passed through the limiter at each timing.

The first phase comparison means and the second phase comparison means are composed of single flip-flops 23 and 24, respectively. The π / 4 shift QPSK signal that has passed through the limiter is input to the D terminals of the flip-flops 23 and 24. Here, the phase comparison characteristic of the flip-flop is shown in FIG.

(A) shows the phase relationship between the sampled signal and the reference clock. Assuming that the duty of the sampling signal is the same as that of the reference clock, the output of the terminal Q is 1 when the input signal of the flip-flop terminal D is ahead of the terminal Cp (clock), and when the input signal is delayed, The output of the terminal Q becomes 0. ((B) in the figure
reference)

FIG. 5 shows the relationship between the transmission data of the π / 4 shift QPSK signal and the differential phase value. When the magnitude of the differential phase is π / 4, 3π / 4, −π / 4, −3π / 4, (0,0), (0,1), (1,0), (1,1), respectively. )
Corresponding to.

When demodulating a π / 4 shift QPSK signal,
From the phase comparison characteristics of flip-flops, if a reference signal having a phase difference of 90 ° is used as the clock input of two flip-flops, 1 or 0 data corresponding to I channel data and Q channel data is output. , Demodulation operation can be performed. That is, in the present invention, the π / 4 shift QPSK signal that has passed through the limiter and the signal that has passed through the two delay units are input, and demodulation is performed by the phase comparison means mainly composed of flip-flops.

Next, the demodulation operation of π / 4 shift QPSK will be described. The terminal Cp of the flip-flop 23 in FIG.
Takes π / 4 shift QPSK signal delayed by one symbol by sampling at a rate higher than the symbol rate. The flip-flop 23 outputs a signal at the rising timing of the input (clock) of the terminal Cp. If the phase of the input signal with reference to the clock phase is Δφ, from the phase comparison characteristic of the flip-flop 23 (see FIG. 4), Is.

On the other hand, the input terminal Cp of the flip-flop 24 shown in FIG.
A signal having a 0 ° phase difference is input. The flip-flop 24 outputs a signal at the falling edge of the clock. From the phase comparison characteristic of the flip-flop 24 (see FIG. 4), Is.

That is, if the outputs of the flip-flops 23 and 24 are I data and Q data, respectively, π / 4, 3π
/ 4, -π / 4, -3π / 4, (0,
0), (0, 1), 91, 0), and (1, 1), which are in agreement with the relationship between the phase difference and the transmission data shown in FIG. Here, a time chart of signal transmission in the embodiment shown in FIG. 2 is shown in FIG.

The input signal frequency of the demodulator of the present invention is N times the symbol rate, and is the limiter output. Therefore, there is a relationship of TS = Nf0 between the one-symbol section TS and the input signal frequency f0. The shift registers 21 and 22 shown in FIG. 2 operate at a high rate N × M (M is an integer) times the symbol rate.

In order to realize good detection sensitivity, N,
It is considered that the larger M is, the better, but when it is realized by an LSI, it needs to be determined by trade-off with current consumption. According to the computer simulation, N = 8 and M = 32 are required to maintain the required detection sensitivity at BER = 10 −2 and 10 −4 under white noise. 6A is an input signal waveform of the flip-flops 23 and 24 of FIG. 2, which is a limited intermediate frequency signal. 6B shows an output waveform of the shift register 21 of FIG. 2, which is a signal delayed by one symbol time with respect to the waveform A. C in FIG. 6 is an output waveform of the shift register 22 in FIG. 2, which is a signal delayed from the waveform B by π / 2 phase time of the intermediate frequency. D in FIG. 6 is the timing of the sampling clock of the flip-flop 23 in FIG. 2, which is synchronized with the rising timing of the waveform B. E in FIG.
Is the timing of the sampling clock of the flip-flop 24 in FIG. 2 and is synchronized with the timing of the falling edge of the waveform C. 6F and G are the output waveforms of the flip-flops 25 and 26 for sampling the carrier A with the clocks D and E, respectively. The flip-flops 25 and 26 in FIG. 2 output demodulated data at the timing of the symbol rate.

The phase of the waveform A with reference to the waveform B of FIG. 6 is the modulation component (Δφ), which is −3/4 in this embodiment. From the mapping of π / 4 shift QPSK, it can be seen that the transmission data is (1, 1) when the phase difference is −3π / 4, which coincides with the output results F and G of this embodiment.

Next, FIG. 7 shows an example of the configuration of the second demodulation device according to the present invention. This is a method in which the output signal of the limiter 100 is sampled at both the rising and falling timings of the output pulse signal of the shift register that constitutes the one-symbol delay device 101 and the 90-degree phase shifter 102.
This can apparently increase the number of samplings per symbol as compared with the embodiment shown in FIG. 2, so that the intermediate frequency for maintaining the required detection sensitivity can be lowered. According to the computer simulation, N =
4, M = 32 is sufficient.

The multiplexers 107 and 108 of FIG. 7 are examples of the configuration of the multiplexing circuit of the present invention. The function of this multiplexing circuit is to switch the outputs of the two flip-flops in synchronization with the timing of each clock.

The flip-flop 103 in FIG. 7 outputs data at the rising timing of the same signal, and the flip-flop 104 outputs data at the falling timing of the same signal. The multiplexer 107 switches the output data at the clock timing. Similarly, the multiplexer 108 switches the data from the flip-flops 105 and 106 by a clock and outputs the data.

Here, the clocks of the multiplexers 107 and 108 can also be generated in the demodulation device. That is, if the duty ratio of the limiter output signal is approximately 1: 1, the output of the 1-symbol delay device 101 and the 90 ° phase shifter 10
By taking the exclusive OR (EXOR) from the output of 2, the timing synchronized with the clocks of the flip-flops 103 and 104 can be generated. Therefore, by inputting this clock to the multiplexer 107, the flip-flops 103 and 104 receive the clocks. It is possible to switch and output the data of.

Further, FIG. 8 shows a configuration example of the third demodulation device according to the present invention. In this embodiment, the output signals of the one-symbol delay unit and the 90-degree phase shifter are sampled using the timing of the π / 4 shift QPSK signal that has passed through the limiter in the present invention. In this configuration example, the output signals of the first delay means and the second delay means of FIG. 2 are input to the phase comparator, and the π / 4 shift QPSK signal is used as the clock of the phase comparator.

Specifically, in addition to the configuration example shown in FIG.
The part surrounded by the dotted line in FIG. 8 is added. And the flip-flops 1103, 1104, 1105, 1
Demodulated data 1 can be generated by performing phase difference detection using the respective outputs of 106. Similarly, demodulation data 2 can be generated by performing phase difference detection using the outputs of flip-flops 1107, 1108, 1109, and 1110. That is, the eight output signals of this configuration example are each subjected to multiplex processing by a flip-flop that samples the output of the one-symbol delay device and a flip-flop that samples the output of the 90-degree phase shifter to generate demodulated data. can do.

Here, the relationship between the π / 4 shift QPSK signal passed through the limiter, the output signal of the shift register 1101 which constitutes the 1-symbol delay device, and the output signal of the shift register 1102 which constitutes the 90 ° phase shifter. Figure 9
Shown in. That is, the shift registers 1101, 1102
When the phase difference information of the input signal is −π / 4, −3π / 4, π / 4, 3π / 4 with reference to the output waveform of, the phase relationship with the limiter output waveform is as shown in the figure. .

Further, in FIG. 8, flip-flops 1104, 1106, 1108, 111 surrounded by dotted lines are shown.
The phase comparison characteristic of 0 is shown in FIG. The flip-flop used here is different from the phase comparison characteristic of the flip-flop shown in FIG. 5 in that the output is switched at the rising timing of the pulse input as the clock. Then, it can be seen that what is obtained by inverting the sign of the phase comparison characteristic of FIG. 7 matches the phase comparison characteristic of FIG.

That is, in this configuration example, the phase difference information is π / shown in FIG. 4 by inverting the phase of the output signal of the flip-flop which receives the output of the 1-symbol delay device.
It becomes possible to correspond to the 4-shift QPSK signal.
Finally, if the demodulator of the present invention is more generalized and shown, it has a configuration as shown in FIG.

The modulation signal is an analog signal, and this analog signal is shaped into a digital signal of 1 and 0 by the binarizing means 8. A limiter is usually used as the binarizing means. A root roll-off filter can be used before the limiter.

The binarized input signal is sampled at high speed by the first sampling means 1. The sampling data is input to the first delay means 2 and the data synchronized with the input clock of this input data is delayed for a predetermined time and then output, so that the output timing of the delay data from the second delay means is clock generation. Equal to the circuit clock. Therefore, the present invention may be configured by omitting the second sampling means and inputting the output of the first delay means to the second delay means. In particular, when the first delay means and the second delay means are directly connected, it becomes possible to configure one delay means as shown by the dotted line in the figure, so that the system configuration can be simplified. .

The demodulated data 1 from the first phase comparison means 3 and the demodulated data 2 from the second phase comparison means 6 are
Since the output timing is shifted by the delay time of the second delay means 5, the third delay means 9 is inserted so that the output timing of the demodulated data 1 is delayed by the delay time of the second delay means and output. It is also possible to do so. This makes it possible to match the output timing of the two demodulated data.

As described above, according to the present invention, the differential detection component is extracted by extracting the phase difference component from the signal one symbol before from the zero crossing point of the π / 4 shift QPSK limiter output signal from which the intersymbol interference component is removed. Can be realized. Moreover, since the detection circuit can be configured by a 1-bit digital processing circuit, it can be realized by a simple LSI configuration.
Suitable for downsizing and low power consumption of demodulator.

[0040]

The demodulator of the present invention does not require AD conversion means, can realize a demodulator with a simple structure such as a shift register and a flop-flop, and can be realized by 1-bit digital processing. The size and power consumption of the unit can be reduced.

[Brief description of drawings]

FIG. 1 is a diagram showing a basic configuration of a demodulation device of the present invention.

FIG. 2 is a diagram showing a specific configuration of a demodulation device of the present invention.

FIG. 3 is a diagram showing phase comparison characteristics of flip-flops.

FIG. 4 is a diagram showing a mapping state of a π / 4 shift QPSK signal.

FIG. 5 is a diagram showing phase comparison characteristics of flip-flops.

6 is a diagram showing a signal chart in the demodulation device shown in FIG.

FIG. 7 is a diagram showing another configuration of the demodulation device of the present invention.

FIG. 8 is a diagram showing another configuration of the demodulation device of the present invention.

9 is a diagram showing a relationship between a limiter output and a delay device output in the demodulator shown in FIG.

FIG. 10 is a diagram showing phase comparison characteristics of flip-flops.

FIG. 11 is a diagram showing another configuration of the demodulation device of the present invention.

FIG. 12 is a diagram showing a conventional baseband differential detection device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... 1st sampling means 2 ... 1st delay means 3 ... 1st phase comparison means 4 ... 2nd sampling means 5 ... 2nd delay means 6 ... 2nd phase comparison means 7 ... Clock generation means

Claims (3)

[Claims] 1. A clock generating means for generating a clock having a rate higher than a symbol rate of an input signal, a first sampling means for sampling the input signal in synchronization with a clock from the clock generating means, and a first sampling means. First delaying means for delaying the output signal from the sampling means by one symbol, and second sampling means for sampling the output signal from the first delaying means in synchronization with the clock from the clock generating means. A second delay means for delaying the output signal from the second sampling means by a quarter cycle time of the intermediate frequency of the input signal; and the input signal and the output signal from the first delay means. First phase comparing means for outputting phase difference information, and first phase comparing information for outputting phase difference information between the input signal and the output signal from the second delay means Demodulator comprising a phase comparison means. 2. The demodulator according to claim 1, wherein the first and second phase comparison means output a 1-bit output signal. 3. One or more flip-flops having one of the first and second delay means outputs and the limiter output as an input and one of them as a clock input, and the same signal as a clock input. Of the flip-flops, one input signal is input, a sign inverting circuit that inverts and outputs the sign of the input signal, and the sign inverting circuit output signal and a flip-flop output that does not pass through the sign inverting circuit are input, The demodulation device according to claim 1, further comprising a multiplexing circuit that multiplexes and outputs on a time axis.