JPH0661828A - Output circuit - Google Patents

Abstract

PURPOSE:To obtain an output circuit suppressing output ringing by providing 1st-3rd switching elements connected in series between DC power supplies having different voltages to the circuit and providing an output terminal to a connecting point between the 1st and 2nd switching elements. CONSTITUTION:N-channel MOS transistors(TRs) 4-1, 4-2... are switching elements which are connected in parallel with a 3rd TR4 and turned on respectively by signals IFSI12, IFSI21, IFSI22 turning on a 2nd TR2 connecting respectively to other output terminals Q12, Q21, Q22 in a matrix shape. When one output terminal Q11 only changes to an L level from the state that all output terminals Q11, Q12, Q21, Q22 are at an H level, the TR 4 is connected between the TR 2 and a DC power supply VSS, the resistance is increased and the falling slows down. Thus, output ringing due to reflection or the like is suppressed. Furthermore, when all the terminals change from H to L level, since number of paths to extract the voltage at the output terminal Q11 to the voltage VSS by the TRs 4-1-4-3 connected in parallel with the TR 4 is increased, the output terminals go to an L level in a shorter time.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an output circuit which is used in an output circuit such as a semiconductor memory and suppresses output ringing.

[0002]

2. Description of the Related Art FIG. 3 is a circuit diagram showing a conventional output circuit. Such an output circuit is used as an output circuit of a semiconductor memory having a memory cell array in which memory cells are arranged in a matrix at intersections of row lines and column lines, for example. In the figure, reference numeral 1 is a first switching element, for example, an n-type MOS transistor, the drain of which is connected to a DC power supply Vcc, the gate of which is connected to the memory cell (not shown) described above, and the source of which is an output terminal Q. Connected to ₁₁ . 2 is a second switching element which is connected in series with the first transistor 1
An OS transistor whose drain is the output terminal Q
₁₁ , the gate is connected to the memory cell via the inverter 3, and the source is connected to another DC power supply Vss.

Next, the operation will be described. When receiving the signal FSI ₁₁ from the corresponding memory cell and outputting the “H (high)” level signal to the output terminal Q ₁₁ ,
SI ₁₁ becomes “H” level. As a result, the first transistor 1 is turned on, the voltage is supplied from Vcc, and the "H" level signal is output to the output terminal Q ₁₁ . However, since the signal FSI ₁₁ is inverted by the inverter 3 into the signal IFSI ₁₁ of “L (low)” level,
Transistor 2 is off.

[0004] When outputting the "L" level signal to the output terminal Q _11, the signal IFSI ₁₁ by the signal FSI ₁₁ becomes "L" level to the "H" level. As a result, the second transistor 2 is turned on, and the output terminal Q ₁₁
Is discharged to Vss, and the "L" level signal is output to the output terminal Q ₁₁ . In this case, the first transistor 1
Is off.

A problem of an output circuit of a semiconductor memory having multiple output terminals, that is, a semiconductor memory having 8 or 16 output terminals is the influence of noise between the output terminals. FIG. 4 is a waveform diagram showing an example of output waveforms at all output terminals and one output terminal in an output circuit of a semiconductor memory having multiple output terminals. For example, the output is "H"
When changing from the level to the “L” level, when only the output of one output terminal changes (shown by the broken line) and when the output of all output terminals changes (shown by the solid line),
The speed of convergence to the “L” level is different. When the output of all the output terminals changes from "H" level to "L" level at the same time, Vss of the output rises because Vss of output is common to each output terminal. It takes time to completely pull it out. Also, when the output from only one output terminal changes from the "H" level to the "L" level, it becomes easy to extract the voltage to Vss (in this case, the rise of the Vss level is very small, so it is not shown). ), Output ringing such as reflection occurs, resulting in a delay in access time.

[0006]

Since the conventional output circuit is configured as described above, the output circuit having multiple output terminals has a problem that output ringing easily occurs due to a combination of output terminals. there were.

The present invention has been made to solve such a problem, and an object thereof is to obtain an output circuit capable of suppressing output ringing.

[0008]

An output circuit according to claim 1 of the present invention includes first, second and third switching elements connected in series with each other between DC power supplies having different voltage values. 1 and an output terminal connected to the connection point of the second switching element. An output circuit according to a second aspect of the present invention is provided with a plurality of switching elements which are connected in parallel with the third switching element and which are operated by another output circuit operating signal.

[0009]

According to the present invention, the resistance of the third switching element slows the fall from the "H" level to the "L" level to suppress ringing. Further, since a plurality of switching elements increase the number of paths for pulling out to Vss, not only output ringing is suppressed but also it is possible to pull out to "L" level in a short time.

[0010]

EXAMPLES Example 1. FIG. 1 is a circuit diagram showing an embodiment of the present invention. In the figure, 1-3, Q ₁₁ , Vcc, Vss
Is exactly the same as that described with reference to FIG. Reference numeral 4 denotes a third switching element arrow-shaped n-type MOS transistor connected in series with the second transistor 2, the drain of which is connected to the source of the second transistor 2 and the gate of which is connected via the inverter 3. It is connected to the memory cell and the source is connected to Vss. 4-1 and 4
-2 and 4-3 are connected in parallel with the third transistor 4 and have other matrix-like output terminals Q ₁₂ , Q ₂₁ and Q.
Signals IFSI ₁₂ , IFSI ₂₁ , IF for turning on the second transistors 2 respectively connected to ₂₂ (not shown)
A plurality of switching elements, for example n-type MOS transistors, which are each turned on by SI ₂₂ .

Next, the operation will be described. When all the output terminals Q ₁₁ , Q ₁₂ , Q ₂₁ , Q ₂₂ are at the “H” level and only one output terminal, for example, Q ₁₁ is changed to the “L” level, the third transistor 4 Is connected between the second transistor 2 and Vss, and its resistance has increased,
Compared with the conventional output circuit, the fall from "H" level to "L" level becomes slower. Therefore, output ringing due to reflection or the like can be suppressed.

Further, when all the output terminals change from "H" level to "L" level at the same time, a plurality of transistors 4-1 connected in parallel with the third transistor 4 are provided.
Since ~ 4-3 increases the number of paths for extracting the voltage of the output terminal Q ₁₁ to Vss, it becomes "L" level in a shorter time than the conventional output circuit.

FIG. 2 is an output waveform diagram of an embodiment of the present invention. As mentioned above, the output of all output terminals is "H".
It can be seen that the speed when the level changes to the “L” level at the same time and the speed when the output from only one output terminal changes from the “H” level to the “L” level are almost the same. .

Example 2. Although the n-type MOS transistors are used as the switching elements 1, 2, 4, 4-1 to 4-3 in the first embodiment, a P-type MOS transistor may be used if the polarities of the DC power source and the signal are reversed. it can.

Example 3. Furthermore, the switching element is not limited to a transistor, and a thyristor or the like may be used.

[0016]

As described above, according to the first aspect of the invention, the DC power supplies having different voltage values are connected in series with each other.
Since the second and third switching elements and the output terminal connected to the connection point of the first and second switching elements are provided, it is possible to suppress the output ringing due to the combination of the plurality of output terminals. Play. In addition, the invention of claim 2 is provided with a plurality of switching elements that are connected in parallel with the third switching element and that are operated by other output circuit operating signals, so that " This has the effect of pulling to the L "level and eliminating the delay in access.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention.

FIG. 2 is a waveform chart for explaining the operation of the embodiment of the present invention.

FIG. 3 is a circuit diagram showing a conventional output circuit.

FIG. 4 is a waveform diagram for explaining the operation of a conventional output circuit.

[Explanation of symbols]

1 1st switching element 2 2nd switching element 4 3rd switching element 4-1 to 4-3 multiple switching elements Q ₁₁ output terminal

Claims (2)

[Claims] 1. A first switching element, a second switching element, and a third switching element connected in series between DC power supplies having different voltage values, and an output terminal connected to a connection point of the first switching element and the second switching element. And an output circuit comprising: 2. A first, a second, and a third switching element connected in series between DC power supplies having different voltage values, and an output terminal connected to a connection point of the first and second switching elements. And a plurality of switching elements that are connected in parallel with the third switching element and that are operated by another output circuit operating signal, the output circuit.