JPH066180A - Afc circuit - Google Patents

Abstract

PURPOSE:To reduce the effect of an error and to attain more accurate control by extending the counting period of time and implementing arithmetic operation with its mean counting value when an electric field input level is low and a period of time allowed for the control is longer. CONSTITUTION:An arithmetic operation 22 detects whether or not a receiver is at present in a hand-off state and when the receiver is not in hand-off state, a counted value DA by a counter 21 is fetched by 30 frequencies and its mean counted value is obtained. When the receiver is in hand-off state, whether or not an electric field input level detected by an RSSI 12 and an A/D converter 13 is -90dBm or below is detected. When the electric field input level is -90dBm or below, the counted value DA by the counter 21 is fetched twice and its average counted value is obtained. Where, the electric field input level is -90dBm or below and the counted period of time is 200msec. Thus, the error in the counted value DA in the case of deterioration in the S/N and fading or the like when the electric field input level is as low as -90dBm is averaged by two time averaging processing and the control as accurate as possible is ensured.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is used in a mobile station for digital communication to receive a base station frequency, follow this frequency, and stabilize the frequency.
control) Regarding the circuit.

[0002]

2. Description of the Related Art As a receiver of a mobile station, a superheterodyne type receiver is generally used and is equipped with a local oscillator for performing frequency conversion from a reception frequency to an intermediate frequency. This local oscillator is, for example, a reference oscillator such as a voltage-controlled temperature-compensated crystal oscillator (hereinafter abbreviated as VC-TCXO), and means for converting an oscillation frequency from the reference oscillator into an intermediate frequency (multiplier circuit, PLL synthesizer, etc.). If the oscillation frequency of this local oscillator includes a deviation, the intermediate frequency deviates from a predetermined value, accurate demodulation cannot be performed, and the transmission frequency also deviates. Therefore, it is necessary to remove the deviation from the oscillation frequency of the local oscillator so as to follow the reception frequency and stabilize the intermediate frequency. Therefore, an AFC circuit is inserted to correct the deviation of the oscillation frequency of the local oscillator.

FIG. 1 is a block diagram showing an example of the configuration of a double superheterodyne receiver provided with the above AFC circuit. In the figure, 1 is a receiving antenna, 2 and 3 are mixers, 4 is an amplifier, and 5 is an amplifier. A code determination circuit, 6 is a PLL synthesizer as the first station, 7 is an N multiplier circuit as the second station, 8 is a PLL synthesizer, 9 is a mixer, 10 is an amplifier, 11 is a transmission antenna, and 12 is RSSI (recived).
signal strngth ind-icator) circuit, 13 is an A / D converter, and 20 is an AFC circuit.

The mixer 2 receives the first local oscillation frequency F _L1 from the PLL synthesizer 6, and the mixer 3 receives the second local oscillation frequency F _L2 from the N multiplication circuit 7 and inputs from the receiving antenna 1. The signal F _R is converted into the first intermediate frequency F _IF1 via the mixer 2 and the second intermediate frequency F _IF1 via the mixer 3.
Converted to intermediate frequency F _IF2 and amplified by amplifier 4,
It is input to the code determination circuit 5 to perform code determination and obtain a demodulation output. Further, in the RSSI circuit, the output from the amplifier 4 is monitored, the electric field input level thereof is set to a DC voltage, the A / D converter 13 converts it into digital data, and the digital data is input to the arithmetic unit 22. The input level is reported.

Next, the AFC circuit 20 will be described. A
The FC circuit 20 includes a counter 21, a calculation unit 22, and a ROM 2.
3, the D / A converter 24, and the VC-TCXO 25, and follows the reception frequency F _R to generate the intermediate frequency F
_In order to stabilize _IF1 , F _IF2 , and F _IFT , control is performed to correct the deviation of the oscillation frequency of the local oscillator. This will be described below.

If the deviation α is superimposed on the output f ₀ from the AFC circuit 20, the output of the PLL synthesizer 6 is FL ₁ (1 + α), and the output of the N multiplication circuit 7 is _{FL 2} (1+).
α), the output of the PLL synthesizer 8 is F _IFT (1 + α)
Becomes Then, the first intermediate frequency including the deviation is F ′
_IF1, 'if indicated by the _IF2, F' also the second intermediate frequency _{F IF1 = F L1 (1 +} α) -F R F = 'IF2 = F L2 (1 + α) -F' IF1 F L2 (1 + α) -F L1 ( _{1 + α) + F R =} α a _{(F L2 -F L1) + F} L2 -F L1 + F R. Substituting F _IF1 = F _L1 −F _R F _IF2 = F _L2 −F _IF1 = F _L2 −F _L1 + F _R into the following equation, it can be expressed as F ′ _IF2 = α (F _IF2 −F _R ) + F _IF2 . 'If during the gate time the _{IF2 G T = n / f 0} (1 + α) (n is the frequency division number) for counting, the count value D _A is, D _A = F' the intermediate frequency F _IF2 × G _T = {α (F _IF2- F _R ) + F _IF2 } × {n / f ₀ (1 + α)} = {F _IF2 (1 + α) −αF _R } × {n / f ₀ (1 + α)} = n / f ₀ · (F _IF2 ) -Αn / f ₀ (1 + α). Therefore, when the count value D _A is brought close to n / f ₀ · (F _IF2 ), the deviation α also becomes α → 0, and the oscillation frequency can be controlled so that the deviation α · f ₀ disappears.

That is, in the AFC circuit 20, the counter 21 measures the output frequency from the amplifier 4 by VC-TCXO2.
The output frequency of 5 is divided by n for a counting time G _T (for example, this counting time G _T is 100 msec),
As shown in the flowchart of FIG. 3, the calculation unit 22 fetches this count value D _A and calculates D _B = a · {n / f ₀ · (F _IF2 ) −D _A } based on the contents of the ROM 23. And output the correction data D _B. Incidentally, when feedback control is not performed, D _B = a · D _A. Data D _B corrected by feedback control
Is converted into an analog DC voltage by the D / A converter 24, input to the VC-TCXO 25, and the VC-TCXO 25
The oscillation frequency f _{0 of} 25 is controlled. And VC-TC
The oscillation output of the XO25 is the PLL synthesizers 6 and 8,
It is supplied to the N multiplication circuit 7.

As described above, control is performed such that the deviation α · f ₀ of the oscillation frequency of the VC-TCXO 25 becomes 0, tracking of the reception frequency F _R is ensured, and reception of the transmission frequency F _T is further performed. Tracking to the frequency F _R (transmission frequency of the base station in the case of mobile radio) is ensured. In addition, the oscillation frequency of each local oscillator is set to one reference oscillator VC-TCXO2.
Since it is based on 5, there is a feature that the configuration can be relatively simple.

[0009]

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention
Although the FC circuit is configured and operates as described above, if fading occurs when the reception input level is low near the sensitivity, an error occurs in the count value of the counter 21 and it becomes difficult to accurately control the oscillation frequency. There was a problem.

Such a problem is particularly problematic when it is applied to, for example, US specification digital cellular. That is, in this American specification, the frequency deviation allowed on the mobile station side while following the base station is a small value of ± 200 Hz (± 0.25 ppm because the RF frequency is in the 800 MHz band), and is -90 dBm during handoff. Within 130 msec at input, 25 at -103 dBm input
Within 0 msec, within this frequency deviation, VC-TCXO2
The frequency of 5 must be pulled in and transmission started. Therefore, the intermediate frequency counting time is 1
Considering 30 msec and looking at the margin, for example, 10
If it is 0 msec, one counting error is 10 Hz in the deviation of the oscillation frequency, and if there are 20 or more counting errors, ±
The allowable value of 200 Hz cannot be satisfied, and the conventional AFC circuit as described above cannot be applied. Further, even when the reception input level is high, when the deviation of the modulation pattern of the reception signal or multipath fading occurs, an error occurs in the count value of the counter 21, and the oscillation frequency cannot be controlled accurately. The present invention has been made to solve such problems.

[0011]

The AFC circuit according to the present invention is provided with a means for detecting whether or not the mobile station is in a handoff state and a means for detecting an electric field input level of a reception frequency, and is in a handoff state. If there is no counter, the counting time for counting the intermediate frequency is set to, for example, 30 times the counting time of the counter, and the average value is used as the count value. For example, when the electric field input level of the reception frequency is low in the handoff state, When the electric field input level is high, the average value is set to be twice as long as the counting time, and the voltage-controlled oscillator is controlled while the calculation value is updated with the count value of the counter.

[0012]

In the present invention, when the hand-off state is not present, the electric field input level is low, the permissible range counting time is set long and the average thereof is used as the count value, so that the reception input level is low near the sensitivity. The effect of fading can be reduced.

[0013]

Embodiments of the present invention will be described below with reference to the drawings. The configuration of the receiver including the AFC circuit of this embodiment is the same as that shown in FIG. 1, and a duplicate description will be omitted here. FIG. 2 is a flow chart showing the operation of the arithmetic unit 22 in this embodiment, and the operation of this embodiment will be explained using FIG. 1 and FIG. In the calculation unit 22, step S
In step 1, it is detected whether or not the receiver is currently in the handoff state. If not, the process proceeds to step S8,
The count value D _A obtained by the counter 21 is fetched 30 times and the average value D _A30 thereof is obtained. For example, if the counting time in the counter 21 is 100 msec, the counting time is 3 sec.
The count value of c minutes is taken in, divided by the count time to obtain D _A30 , the error due to the modulation pattern or fading is averaged, and then the calculation is performed in step S9 to obtain the correction data D
Seeking _B, by controlling the oscillation frequency of the VC-TCXO25 a value of this D _B was converted to a digital value by the D / A converter 24, by reducing the errors due to deviation or multipath fading modulation pattern of the received signal Get precise control.

If it is during handoff, step S2
Then, it is checked whether the electric field input level detected by the RSSI 12 and the A / D converter 13 is -90 dBm or less,
If the electric field input level is -90 dBm or less, step S
6, the count value D _A obtained by the counter 21 is fetched twice, and the average value D _A2 thereof is calculated.
Execute 5. In the case of US-specification digital cellular, V is within 130 msec when -90 dBm is input during handoff and 250 msec when -103 dBm is input.
It is necessary to comply with the specifications for starting transmission by pulling in the oscillation frequency of the C-TCXO25. Here, electric field input is -90 dB.
The counting time is 200 msec at m or less. In this way, when the electric field input level is low at −90 dBm or less, errors in the count value D _A due to deterioration of the SN ratio, modulation pattern, fading, etc. are averaged by averaging twice, and even when the electric field input is low, Ensure as accurate control as possible.

If the electric field input level is -90 dBm or more at the time of handoff, the count value D _A by the counter 21 is fetched once at step S3, and D _B is calculated at step S4 based on this D _A. Then, with this count value D _B , V
Control C-TCXO. In this case, the SN ratio is good, there is no error due to deterioration of the SN ratio, and accurate control can be performed. As described above, when the electric field input level is low, the count value of the counter 21 is averaged by increasing the counting time of the intermediate frequency to 200 msec, and the control with less influence of the error becomes possible. If the time allowed for counting other than the above is long, the influence of the error is further reduced by lengthening the counting time and averaging.

[0016]

As described above, according to the present invention, when the electric field input level is low or the time allowed for the control is long, the counting time is lengthened and the average value is calculated. There is an effect that the influence of the error can be minimized and more accurate control can be performed.

[Brief description of drawings]

FIG. 1 is a block diagram illustrating a configuration example of a receiver including an AFC circuit.

FIG. 2 is a flowchart showing the operation of the embodiment of the present invention.

FIG. 3 is a flowchart showing the operation of a conventional AFC circuit.

[Explanation of symbols]

12 RSSI (recived signal strength indicator)
Circuit 13 A / D converter 20 AFC circuit 21 Counter 22 Calculation part 23 ROM 24 D / A converter 25 VC-TCXO

Claims (1)

[Claims] 1. A feedback control circuit used in a mobile station for digital communication, for inputting an intermediate frequency and controlling a local oscillator for stabilizing an intermediate frequency by following a received frequency, a counter, an arithmetic unit, and a voltage. AFC (automatic frequency contr) that has a control oscillator, counts the intermediate frequency sequentially by the counter, performs sequential calculation processing based on the count value, and controls the voltage controlled oscillator while updating the calculation value.
ol) means for detecting whether or not the mobile station is in the handoff state, means for detecting the electric field input level of the reception frequency, and counting time for counting the intermediate frequency by the counter when the mobile station is not in the handoff state. Is an allowable time (for example, 30 times the counting time of the counter), and the average value is used as a count value. Based on this count value, the mobile station is in the handoff state and the electric field input level of the reception frequency is low. In this case, when the counting time for counting the intermediate frequency in the handoff state is allowed (for example, twice the counting time of the counter), its average value is used as the count value, and the mobile station In the handoff state and when the electric field input level of the reception frequency is high, the arithmetic unit sequentially performs arithmetic processing on the basis of the count value of the counter to obtain the arithmetic value. AFC circuit having means, for controlling the voltage controlled oscillator while new.