JP2540093B2 - AFC circuit - Google Patents

AFC circuit

Info

Publication number
JP2540093B2
JP2540093B2 JP4187410A JP18741092A JP2540093B2 JP 2540093 B2 JP2540093 B2 JP 2540093B2 JP 4187410 A JP4187410 A JP 4187410A JP 18741092 A JP18741092 A JP 18741092A JP 2540093 B2 JP2540093 B2 JP 2540093B2
Authority
JP
Japan
Prior art keywords
frequency
electric field
input level
field input
value
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP4187410A
Other languages
Japanese (ja)
Other versions
JPH066180A (en
Inventor
元 菅沼
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Japan Radio Co Ltd
Original Assignee
Japan Radio Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Japan Radio Co Ltd filed Critical Japan Radio Co Ltd
Priority to JP4187410A priority Critical patent/JP2540093B2/en
Priority to CA002098660A priority patent/CA2098660C/en
Priority to US08/080,407 priority patent/US5513388A/en
Priority to AU41408/93A priority patent/AU659018B2/en
Priority to EP95104800A priority patent/EP0662754A1/en
Priority to EP93304891A priority patent/EP0580294B1/en
Priority to EP95104801A priority patent/EP0663725A1/en
Priority to DE69317825T priority patent/DE69317825T2/en
Publication of JPH066180A publication Critical patent/JPH066180A/en
Priority to AU13453/95A priority patent/AU670896B2/en
Priority to AU13454/95A priority patent/AU671570B2/en
Application granted granted Critical
Publication of JP2540093B2 publication Critical patent/JP2540093B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、デイジタル通信の移動
局に用いられ基地局周波数を受信してこの周波数に追従
させ周波数を安定化させるAFC(automatic frequency
control) 回路に関する。
BACKGROUND OF THE INVENTION The present invention relates to an AFC (automatic frequency) which is used in a mobile station for digital communication and which receives a base station frequency and makes it follow this frequency to stabilize the frequency.
control) Regarding the circuit.

【0002】[0002]

【従来の技術】移動局の受信機には、一般にスーパーヘ
テロダイン方式の受信機が用いられ、受信周波数から中
間周波数への周波数変換を行う局部発振器を備えてい
る。この局部発振器は、例えば、電圧制御−温度補償水
晶発振器(以下、VC−TCXOと略記する)等の基準
発振器と、基準発振器からの発振周波数を中間周波数に
変換する手段(逓倍回路、PLLシンセサイザ等)とか
ら構成されるが、この局部発振器の発振周波数に偏差が
含まれていると、中間周波数が所定値からずれ、正確な
復調ができなくなり、送信周波数もずれてしまう。従っ
て、受信周波数に追従して中間周波数を安定化させるべ
く、局部発振器の発振周波数から偏差を除去する必要が
ある。このため、AFC回路を挿入して局部発振器の発
振周波数の偏差を補正している。
2. Description of the Related Art As a receiver of a mobile station, a superheterodyne type receiver is generally used and is equipped with a local oscillator for performing frequency conversion from a reception frequency to an intermediate frequency. This local oscillator is, for example, a reference oscillator such as a voltage-controlled temperature-compensated crystal oscillator (hereinafter abbreviated as VC-TCXO), and means for converting an oscillation frequency from the reference oscillator into an intermediate frequency (multiplication circuit, PLL synthesizer, etc.). If the oscillation frequency of this local oscillator includes a deviation, the intermediate frequency deviates from a predetermined value, accurate demodulation cannot be performed, and the transmission frequency also deviates. Therefore, it is necessary to remove the deviation from the oscillation frequency of the local oscillator so as to follow the reception frequency and stabilize the intermediate frequency. Therefore, an AFC circuit is inserted to correct the deviation of the oscillation frequency of the local oscillator.

【0003】図1は、上述のAFC回路を備えたダブル
スーパーヘテロダイン受信機の一構成例を示すブロック
図であり、図において、1は受信アンテナ,2,3はミ
キサ、4は増幅器、5は符号判定回路、6は第1局発と
してのPLLシンセサイザ、7は第2局発としてのN逓
倍回路、8はPLLシンセサイザ、9はミキサ、10は
増幅器、11は送信アンテナ、12はRSSI(recived
signal strngth ind-icator) 回路、13はA/Dコン
バータ、20はAFC回路を示す。
FIG. 1 is a block diagram showing an example of the configuration of a double superheterodyne receiver provided with the above AFC circuit. In the figure, 1 is a receiving antenna, 2 and 3 are mixers, 4 is an amplifier, and 5 is an amplifier. A code determination circuit, 6 is a PLL synthesizer as the first station, 7 is an N multiplier circuit as the second station, 8 is a PLL synthesizer, 9 is a mixer, 10 is an amplifier, 11 is a transmission antenna, and 12 is RSSI (recived).
signal strngth ind-icator) circuit, 13 is an A / D converter, and 20 is an AFC circuit.

【0004】ミキサ2にはPLLシンセサイザ6からの
第1局部発振周波数FL1が入力され、ミキサ3にはN逓
倍回路7からの第2局部発振周波数FL2が入力され、受
信アンテナ1からの入力信号FR がミキサ2を介して第
1中間周波数FIF1 に変換され、ミキサ3を介して第2
中間周波数FIF2 に変換されて、増幅器4で増幅され、
符号判定回路5に入力されて符号判定が行われて復調出
力が得られる。また、RSSI回路では、増幅器4から
の出力をモニタしてその電界入力レベルを直流電圧と
し、A/Dコンバータ13でディジタルデータに変換し
て演算部22へ入力しており、基地局へ逐次電界入力レ
ベルを報告している。
The mixer 2 receives the first local oscillation frequency F L1 from the PLL synthesizer 6, and the mixer 3 receives the second local oscillation frequency F L2 from the N multiplication circuit 7 and inputs from the receiving antenna 1. The signal F R is converted into the first intermediate frequency F IF1 via the mixer 2 and the second intermediate frequency F IF1 via the mixer 3.
Converted to intermediate frequency F IF2 and amplified by amplifier 4,
It is input to the code determination circuit 5 to perform code determination and obtain a demodulation output. Further, in the RSSI circuit, the output from the amplifier 4 is monitored, the electric field input level thereof is set to a DC voltage, the A / D converter 13 converts it into digital data, and the digital data is input to the arithmetic unit 22. The input level is reported.

【0005】次にAFC回路20について説明する。A
FC回路20は、カウンタ21、演算部22、ROM2
3、D/Aコンバータ24、VC−TCXO25で構成
されており、受信周波数FR に追従して中間周波数F
IF1 ,FIF2 ,FIFT を安定化すべく、局部発振器の発
振周波数の偏差を補正する制御を行っている。以下、こ
れを説明する。
Next, the AFC circuit 20 will be described. A
The FC circuit 20 includes a counter 21, a calculation unit 22, and a ROM 2.
3, the D / A converter 24, and the VC-TCXO 25, and follows the reception frequency F R to generate the intermediate frequency F
In order to stabilize IF1 , F IF2 , and F IFT , control is performed to correct the deviation of the oscillation frequency of the local oscillator. This will be described below.

【0006】仮に、AFC回路20からの出力f0 に偏
差αが重畳している場合、PLLシンセサイザ6の出力
はFL1(1+α),N逓倍回路7の出力はFL2(1+
α),PLLシンセサイザ8の出力はFIFT (1+α)
となる。そして、偏差を含む第1中間周波数をF’
IF1 、同じく第2中間周波数をF’IF2 で表せば、 F’IF1 =FL1(1+α)−FR F’IF2 =FL2(1+α)−F’IF1 =FL2(1+α)−FL1(1+α)+FR =α(FL2−FL1)+FL2−FL1+FR となる。 後式に FIF1 =FL1−FRIF2 =FL2−FIF1 =FL2−FL1+FR を代入すると、 F’IF2 =α(FIF2 −FR )+FIF2 と表せる。こ
の中間周波数F’IF2 をゲートタイム GT =n/f0 (1+α) の間(nは分周数)計数す
ると、その計数値DA は、 DA =F’IF2 ×GT ={α(FIF2 −FR )+FIF2 }×{n/f0 (1+α)} ={FIF2 (1+α)−αFR }×{n/f0 (1+α)} =n/f0 ・(FIF2 )−αn/f0 (1+α) と表せる。 従って、計数値DA をn/f0 ・(FIF2 )に近づけれ
ば、偏差αもα→0となり、偏差α・f0 がなくなるよ
うに発振周波数を制御できる。
If the deviation α is superimposed on the output f 0 from the AFC circuit 20, the output of the PLL synthesizer 6 is FL 1 (1 + α), and the output of the N multiplication circuit 7 is FL 2 (1+).
α), the output of the PLL synthesizer 8 is F IFT (1 + α)
Becomes Then, the first intermediate frequency including the deviation is F ′
IF1, 'if indicated by the IF2, F' also the second intermediate frequency F IF1 = F L1 (1 + α) -F R F = 'IF2 = F L2 (1 + α) -F' IF1 F L2 (1 + α) -F L1 ( 1 + α) + F R = α a (F L2 -F L1) + F L2 -F L1 + F R. Substituting F IF1 = F L1 −F R F IF2 = F L2 −F IF1 = F L2 −F L1 + F R into the following equation, it can be expressed as F ′ IF2 = α (F IF2 −F R ) + F IF2 . 'If during the gate time the IF2 G T = n / f 0 (1 + α) (n is the frequency division number) for counting, the count value D A is, D A = F' the intermediate frequency F IF2 × G T = {α (F IF2- F R ) + F IF2 } × {n / f 0 (1 + α)} = {F IF2 (1 + α) −αF R } × {n / f 0 (1 + α)} = n / f 0 · (F IF2 ) -Αn / f 0 (1 + α). Therefore, when the count value D A is brought close to n / f 0 · (F IF2 ), the deviation α also becomes α → 0, and the oscillation frequency can be controlled so that the deviation α · f 0 disappears.

【0007】すなわちAFC回路20では、増幅器4か
らの出力周波数を、カウンタ21で、VC−TCXO2
5の出力周波数をn分周した計数時間GT (例えば、こ
の計数時間GT を100msecとする)の間計数し、
演算部22で、図3のフローチャートに示すように、こ
の計数値DA を取り込み、ROM23の内容に基づい
て、DB =a・{n/f0 ・(FIF2 )−DA }の演算
を行い、補正データDBを出力する。ちなみに、フィー
ドバック制御を行わない場合には、DB =a・DA とな
る。フィードバック制御により補正されたデータDB
は、D/Aコンバータ24でアナロクの直流電圧に変換
され、VC−TCXO25に入力され、VC−TCXO
25の発振周波数f0 を制御する。そして、VC−TC
XO25の発振出力が、PLLシンセサイザ6及び8、
N逓倍回路7に供給される。
That is, in the AFC circuit 20, the counter 21 measures the output frequency from the amplifier 4 by VC-TCXO2.
The output frequency of 5 is divided by n for a counting time G T (for example, this counting time G T is 100 msec),
As shown in the flowchart of FIG. 3, the calculation unit 22 fetches this count value D A and calculates D B = a · {n / f 0 · (F IF2 ) −D A } based on the contents of the ROM 23. And output the correction data D B. Incidentally, when feedback control is not performed, D B = a · D A. Data D B corrected by feedback control
Is converted into an analog DC voltage by the D / A converter 24, input to the VC-TCXO 25, and the VC-TCXO 25
The oscillation frequency f 0 of 25 is controlled. And VC-TC
The oscillation output of the XO25 is the PLL synthesizers 6 and 8,
It is supplied to the N multiplication circuit 7.

【0008】以上のようにして、VC−TCXO25の
発振周波数の偏差α・f0 が0となるような制御が行わ
れ、受信周波数FR への追従が確保され、さらに送信周
波数FT の受信周波数FR (移動無線の場合、基地局の
送信周波数)への追従が確保される。また、各局部発振
器の発振周波数を、一つの基準発振器VC−TCXO2
5を基準としているため、比較的その構成が簡素にでき
るという特徴がある。
As described above, control is performed such that the deviation α · f 0 of the oscillation frequency of the VC-TCXO 25 becomes 0, tracking of the reception frequency F R is ensured, and reception of the transmission frequency F T is further performed. Tracking to the frequency F R (transmission frequency of the base station in the case of mobile radio) is ensured. In addition, the oscillation frequency of each local oscillator is set to one reference oscillator VC-TCXO2.
Since it is based on 5, there is a feature that the configuration can be relatively simple.

【0009】[0009]

【発明が解決しようとする課題】上記のような従来のA
FC回路は以上のように構成され動作するが、受信入力
レベルが感度付近の低いときにフェージングが発生する
と、カウンタ21の計数値に誤差が発生し、発振周波数
の正確な制御が困難になるという問題点があった。
DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention
Although the FC circuit is configured and operates as described above, if fading occurs when the reception input level is low near the sensitivity, an error occurs in the count value of the counter 21 and it becomes difficult to accurately control the oscillation frequency. There was a problem.

【0010】このような問題は、例えば米国仕様ディジ
タルセルラーに適用する場合に特に問題となる。すなわ
ちこの米国仕様では、基地局に追従した状態で移動局側
に許容される周波数偏差は、±200Hz(RF周波数
が800MHz帯なので±0.25ppm)という小さ
な値であり、且つ、ハンドオフ時には−90dBm入力
時に130msec以内、−103dBm入力時に25
0msec以内でこの周波数偏差内にVC−TCXO2
5の周波数を引き込んで送信を開始しなければならな
い。従って、中間周波数計数時間を仕様の一番厳しい1
30msecを考慮し、且つ、余裕を見て、例えば10
0msecとすると、1つの計数誤差が発振周波数の偏
差では10Hzとなり、20個以上計数誤差があると±
200Hzの許容値を満足できなくなり、上述のような
従来のAFC回路は適用できなくなる。また、受信入力
レベルが大きいときであっても、受信信号の変調パター
ンの偏りやマルチパスフェージングが発生した時にはカ
ウンタ21の計数値に誤差が発生し、発振周波数の正確
な制御が行えなくなる。本発明はかかる問題点を解決す
るためになされたものである。
Such a problem is particularly problematic when it is applied to, for example, US specification digital cellular. That is, in this American specification, the frequency deviation allowed on the mobile station side while following the base station is a small value of ± 200 Hz (± 0.25 ppm because the RF frequency is in the 800 MHz band), and is -90 dBm during handoff. Within 130 msec at input, 25 at -103 dBm input
Within 0 msec, within this frequency deviation, VC-TCXO2
The frequency of 5 must be pulled in and transmission started. Therefore, the intermediate frequency counting time is 1
Considering 30 msec and looking at the margin, for example, 10
If it is 0 msec, one counting error is 10 Hz in the deviation of the oscillation frequency, and if there are 20 or more counting errors, ±
The allowable value of 200 Hz cannot be satisfied, and the conventional AFC circuit as described above cannot be applied. Further, even when the reception input level is high, when the deviation of the modulation pattern of the reception signal or multipath fading occurs, an error occurs in the count value of the counter 21, and the oscillation frequency cannot be controlled accurately. The present invention has been made to solve such problems.

【0011】[0011]

【課題を解決するための手段】本発明に係わるAFC回
路は、当該移動局がハンドオフ状態にあるか否かを検出
する手段受信周波数の電界入力レベルを所定のしき
い値と比較して、このしきい値を超えていれば電界入力
レベルが高いと判断し、このしきい値を超えていなけれ
ば電界入力レベルが低いと判断する電界入力レベル検出
手段と、 上記計数値のn回(nは1以上の整数)の平均
値を基に演算部で順次演算処理を行い演算値を更新しな
がら電圧制御発振器を制御する手段とを備え、 当該移動
局がハンドオフ状態か否か、ハンドオフ状態であっても
受信周波数の電界入力レベルの高低により、上記nの値
を変化させることを特徴とする
AFC circuit according to the present invention SUMMARY OF THE INVENTION includes means for detecting whether the mobile station is in a handoff state, an electric field input level to a predetermined threshold of received frequency
If this threshold is exceeded, the electric field input
Judge that the level is high and exceed this threshold
Electric field input level detection to judge that the electric field input level is low
Means and average of the above-mentioned count value n times (n is an integer of 1 or more)
Do not update the calculated value by performing sequential calculation processing in the calculation section based on the value.
And means for controlling the reluctant voltage controlled oscillator, the mobile
Whether the station is in handoff or not
The value of n depends on the level of the electric field input level of the reception frequency.
It is characterized by changing .

【0012】[0012]

【作用】本発明においては、ハンドオフ状態にない場
合、電界入力レベルが低い場合、それぞれ許容される範
囲計数時間を長くとりその平均を計数値とすることによ
り、受信入力レベルが感度付近の低いときのフェージン
グの影響を少なくすることができる。
In the present invention, when the hand-off state is not present, the electric field input level is low, the permissible range counting time is set long and the average thereof is used as the count value, so that the reception input level is low near the sensitivity. The effect of fading can be reduced.

【0013】[0013]

【実施例】以下、本発明の実施例を図面に基づき説明す
る。なお、本実施例のAFC回路を備えた受信機の構成
は図1に示す構成と同様であり、ここでは重複した説明
は省略する。図2は、本実施例における演算部22の動
作を示すフローチャートであり、図1,図2を用いて本
実施例の動作を説明する。演算部22では、ステップS
1で現在受信機がハンドオフ状態にあるか否かを検出
し、ハンドオフしてない場合にはステップS8に移り、
カウンタ21による計数値DA を30回分取り込み、そ
の平均値DA30 を求める。例えば、カウンタ21におけ
る計数時間が100msecとすると、計数時間3se
c分の計数値を取り込み、計数時間で割ってDA30 を求
め、変調パターンあるいはフェージングによる誤差を平
均化してからステップS9で演算を行い、補正データD
B を求め、このDB をD/Aコンバータ24でディジタ
ル値に変換した値でVC−TCXO25の発振周波数を
制御することにより、受信信号の変調パターンの偏りや
マルチパスフェージングによる誤差を少なくして正確な
制御を行う。
Embodiments of the present invention will be described below with reference to the drawings. The configuration of the receiver including the AFC circuit of this embodiment is the same as that shown in FIG. 1, and a duplicate description will be omitted here. FIG. 2 is a flow chart showing the operation of the arithmetic unit 22 in this embodiment, and the operation of this embodiment will be explained using FIG. 1 and FIG. In the calculation unit 22, step S
In step 1, it is detected whether or not the receiver is currently in the handoff state. If not, the process proceeds to step S8,
The count value D A obtained by the counter 21 is fetched 30 times and the average value D A30 thereof is obtained. For example, if the counting time in the counter 21 is 100 msec, the counting time is 3 sec.
The count value for c is taken in, divided by the count time to obtain D A30 , the error due to the modulation pattern or fading is averaged, and then the calculation is performed in step S9 to obtain the correction data D
Seeking B, by controlling the oscillation frequency of the VC-TCXO25 a value of this D B was converted to a digital value by the D / A converter 24, by reducing the errors due to deviation or multipath fading modulation pattern of the received signal Get precise control.

【0014】また、ハンドオフ時であればステップS2
へ移り、RSSI12,A/Dコンバータ13で検出さ
れる電界入力レベルが−90dBm以下か否かを調べ、
電界入力レベルが−90dBm以下の場合はステップS
6へ移り、カウンタ21による計数値DA を2回取り込
み、その平均値DA2を求め、ステップS7,ステップS
5を実行する。米国仕様ディジタルセルラーの場合、ハ
ンドオフ時には−90dBm入力時に130msec以
内、−103dBm入力時には250msec以内にV
C−TCXO25の発振周波数を引き込んで送信を開始
する仕様上の必要があり、ここでは電界入力−90dB
m以下で計数時間を200msecとする。このように
して、電界入力レベルが−90dBm以下の低い場合
の、SN比の劣化,変調パターン,フェージング等によ
る計数値DA の誤差を2回の平均により平均化し、電界
入力が低い場合でも、出来るだけ正確な制御を確保す
る。
If it is during handoff, step S2
Then, it is checked whether the electric field input level detected by the RSSI 12 and the A / D converter 13 is -90 dBm or less,
If the electric field input level is -90 dBm or less, step S
6, the count value D A obtained by the counter 21 is fetched twice, and the average value D A2 thereof is calculated.
Execute 5. In the case of US-specification digital cellular, V is within 130 msec at -90 dBm input at handoff and 250 msec at -103 dBm input.
It is necessary to comply with the specifications for starting transmission by pulling in the oscillation frequency of the C-TCXO25. Here, electric field input is -90 dB.
The counting time is 200 msec at m or less. In this way, when the electric field input level is low at −90 dBm or less, errors in the count value D A due to deterioration of the SN ratio, modulation pattern, fading, etc. are averaged by averaging twice, and even when the electric field input is low, Ensure as accurate control as possible.

【0015】また、ハンドオフ時であり、電界入力レベ
ルが−90dBm以上の場合には、ステップS3でカウ
ンタ21による計数値DA を一回取り込み、このDA
基にステップS4でDB を演算し、この計数値DB でV
C−TCXOを制御する。この場合はSN比は良好であ
り、SN比の劣化による誤差はなく、正確な制御が行え
る。以上のように、電界入力レベルが低い時は、中間周
波数の計数時間を200msecと長くすることによっ
て、カウンタ21による計数値の平均化を行い、誤差の
影響を少なくした制御が可能となり、ハンドオフ時以外
の計数に許される時間が長い場合、計数時間を長くして
平均化することで誤差の影響を更に少なくする。
If the electric field input level is -90 dBm or more at the time of handoff, the count value D A by the counter 21 is fetched once at step S3, and D B is calculated at step S4 based on this D A. Then, with this count value D B , V
Control C-TCXO. In this case, the SN ratio is good, there is no error due to deterioration of the SN ratio, and accurate control can be performed. As described above, when the electric field input level is low, the count time of the intermediate frequency is lengthened to 200 msec to average the count values by the counter 21, and control with less influence of error becomes possible. If the time allowed for counting other than the above is long, the influence of the error is further reduced by lengthening the counting time and averaging.

【0016】[0016]

【発明の効果】本発明は以上説明したように、電界入力
レベルが低い場合や制御を行うときに許される時間が長
い場合に、計数時間を長くしてその平均値で演算を行う
ことにより、誤差の影響をすくなくでき、より正確な制
御が行えるという効果がある。
As described above, according to the present invention, when the electric field input level is low or the time allowed for the control is long, the counting time is lengthened and the average value is calculated. There is an effect that the influence of the error can be minimized and more accurate control can be performed.

【図面の簡単な説明】[Brief description of drawings]

【図1】AFC回路を備えた受信機の一構成例を示すブ
ロック図である。
FIG. 1 is a block diagram illustrating a configuration example of a receiver including an AFC circuit.

【図2】本発明の一実施例の動作を示すフローチャート
である。
FIG. 2 is a flowchart showing the operation of one embodiment of the present invention.

【図3】従来のAFC回路の動作を示すフローチャート
である。
FIG. 3 is a flowchart showing the operation of a conventional AFC circuit.

【符号の説明】[Explanation of symbols]

12 RSSI(recived signal strength indicator)
回路 13 A/Dコンバータ 20 AFC回路 21 カウンタ 22 演算部 23 ROM 24 D/Aコンバータ 25 VC−TCXO
12 RSSI (recived signal strength indicator)
Circuit 13 A / D converter 20 AFC circuit 21 Counter 22 Calculation part 23 ROM 24 D / A converter 25 VC-TCXO

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 ディジタル通信の移動局に用いられ、受
信周波数に追従させて中間周波数を安定化させるため中
間周波数を入力し局部発振器を制御するフィードバック
制御回路に組み込まれ、 カウンタと演算部と電圧制御発振器とを有し、 カウンタで中間周波数を順次計数し、計数値を基に演算
部で順次演算処理を行い、演算値を更新しながら電圧制
御発振器を制御するAFC(automatic freque-ncy cont
rol)回路において、 当該移動局がハンドオフ状態にあるか否かを検出する手
、 受信周波数の電界入力レベルを所定のしきい値と比較し
て、このしきい値を超えていれば電界入力レベルが高い
と判断し、このしきい値を超えていなければ電界入力レ
ベルが低いと判断する電界入力レベル検出手段と、 上記計数値のn回(nは1以上の整数)の平均値を基に
演算部で順次演算処理を行い演算値を更新しながら電圧
制御発振器を制御する手段とを備え、 当該移動局がハンドオフ状態か否か、ハンドオフ状態で
あっても受信周波数の電界入力レベルの高低により、上
記nの値を変化させることを特徴とするAFC回路。
1. Used in a mobile station of digital communication,
Medium to stabilize the intermediate frequency by following the received frequency
Feedback to input local frequency and control local oscillator
Built into the control circuit, it has a counter, a calculation unit, and a voltage-controlled oscillator.
Part performs sequential calculation processing, and the voltage control is performed while updating the calculation value.
AFC (automatic freque-ncy cont) that controls the oscillator
rol) circuit to detect whether the mobile station is in the handoff state.
StepWhen, The electric field input level of the receiving frequencyCompared to a given threshold
If this threshold is exceeded, the electric field input level is high.
If this threshold is not exceeded, the electric field input level is
An electric field input level detecting means for judging that the bell is low, Based on the average value of the above counts n times (n is an integer of 1 or more)
The calculation unit performs sequential calculation processing and updates the calculated value
And a means for controlling the controlled oscillator, Whether the mobile station is in the handoff state or not
Even if there is, the level of the electric field input level of the reception frequency
An AFC circuit characterized by changing the value of n.
JP4187410A 1992-06-23 1992-06-23 AFC circuit Expired - Lifetime JP2540093B2 (en)

Priority Applications (10)

Application Number Priority Date Filing Date Title
JP4187410A JP2540093B2 (en) 1992-06-23 1992-06-23 AFC circuit
CA002098660A CA2098660C (en) 1992-06-23 1993-06-17 Automatic frequency control circuit
US08/080,407 US5513388A (en) 1992-06-23 1993-06-18 Automatic frequency control circuit
AU41408/93A AU659018B2 (en) 1992-06-23 1993-06-21 Automatic frequency control circuit
EP93304891A EP0580294B1 (en) 1992-06-23 1993-06-23 Automatic frequency control circuit
EP95104801A EP0663725A1 (en) 1992-06-23 1993-06-23 Automatic frequency control circuit
EP95104800A EP0662754A1 (en) 1992-06-23 1993-06-23 Automatic frequency control circuit
DE69317825T DE69317825T2 (en) 1992-06-23 1993-06-23 Automatic frequency control circuit
AU13453/95A AU670896B2 (en) 1992-06-23 1995-02-23 Automatic frequency control circuit
AU13454/95A AU671570B2 (en) 1992-06-23 1995-02-23 Automatic frequency control circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4187410A JP2540093B2 (en) 1992-06-23 1992-06-23 AFC circuit

Publications (2)

Publication Number Publication Date
JPH066180A JPH066180A (en) 1994-01-14
JP2540093B2 true JP2540093B2 (en) 1996-10-02

Family

ID=16205554

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4187410A Expired - Lifetime JP2540093B2 (en) 1992-06-23 1992-06-23 AFC circuit

Country Status (1)

Country Link
JP (1) JP2540093B2 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08182780A (en) * 1994-12-27 1996-07-16 Yamaha Corp Club head for golf
JP2755210B2 (en) * 1995-04-11 1998-05-20 日本電気株式会社 Automatic frequency control circuit
JP3042418B2 (en) * 1996-09-27 2000-05-15 日本電気株式会社 Frequency adjustment method and frequency adjustment circuit for digital receiver

Also Published As

Publication number Publication date
JPH066180A (en) 1994-01-14

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