JPH0661650A - Production of multilayer ceramic board - Google Patents

Production of multilayer ceramic board

Info

Publication number
JPH0661650A
JPH0661650A JP21311292A JP21311292A JPH0661650A JP H0661650 A JPH0661650 A JP H0661650A JP 21311292 A JP21311292 A JP 21311292A JP 21311292 A JP21311292 A JP 21311292A JP H0661650 A JPH0661650 A JP H0661650A
Authority
JP
Japan
Prior art keywords
sheet
substrate
shrinkage
sheets
multilayer ceramic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP21311292A
Other languages
Japanese (ja)
Inventor
Manabu Tazaki
学 田崎
Eishin Nishikawa
英信 西川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP21311292A priority Critical patent/JPH0661650A/en
Publication of JPH0661650A publication Critical patent/JPH0661650A/en
Pending legal-status Critical Current

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  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

PURPOSE:To facilitate formation of an outermost wiring pattern by removing a columnar electrode in flush with a compositional sheet of a board. CONSTITUTION:A compositional sheet 1 of a board and a contraction suppressing sheet 2 are formed on a film 3. A hole is drilled through both sheets and subsequently filled with a conductor paste 4. A plurality of compositional sheets 1 are then laminated sequentially between uppermost and lowermost contraction suppressing sheets 2. An inner layer conductor pattern 5 is foamed between the compositional sheets 1 at that time. The laminate of sheets is then sintered at such temperature as only a compositional sheet 1 made of low temperature sintering material is sintered and the uppermost and lowermost contraction suppressing sheets 2 not sintered under that temperature, are removed thus forming a columnar electrode 6. The columnar electrode 6 is then machined aligning the upper and lower surfaces of the compositional sheet 1 thus forming an outermost wiring pattern easily.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は半導体LSI、チップ部
品などを搭載し、かつそれらを容易に相互配線できる多
層セラミック基板の製造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a multi-layer ceramic substrate on which a semiconductor LSI, chip parts, etc. can be mounted and which can be easily interconnected.

【0002】[0002]

【従来の技術】近年、多層セラミック基板は、デバイス
の急激な進展にともなって高密度なものが要求され、回
路のデジタル化に伴う多ピン化、狭ピッチ化と実装形態
の面実装化、さらにはフリップチップ実装化に進んでい
る。
2. Description of the Related Art In recent years, a multilayer ceramic substrate is required to have a high density in accordance with the rapid progress of devices, and the increase in the number of pins due to the digitization of circuits, the narrower pitch and the surface mounting of the mounting form, Is advancing to flip chip mounting.

【0003】しかしながら、多層セラミック基板にはそ
の焼成時の焼結にともない収縮が生じるという問題があ
る。この焼結にともなう収縮は、使用する基板材料、グ
リーンシート組成、粉体ロットなどにより異なり、これ
らにより多層セラミック基板の作製においていくつかの
問題が生じている。
However, the multilayer ceramic substrate has a problem that shrinkage occurs due to sintering during firing. The shrinkage due to the sintering varies depending on the substrate material used, the green sheet composition, the powder lot, and the like, which causes some problems in the production of the multilayer ceramic substrate.

【0004】まず第一に、多層セラミック基板の作製に
おいて内層配線の焼成を行ってから最上層などの最外層
配線の形成を行うため、基板材料の収縮誤差が大きい
と、最外層配線パターンと内層電極との接続が行えない
ので、収縮誤差を予測して、補正するように最外層電極
部に必要以上の大きい面積のランドを形成しなければな
らず、高密度の配線を必要とする回路には支障が生じ
る。また、収縮誤差にあわせて最外層の配線のためのス
クリーン版をいくつか用意しておき、多層セラミック基
板の収縮率に応じて使用する方法が取られているが、こ
の方法ではスクリーン版を数多く用意しなければならず
不経済である。
First, in manufacturing a multilayer ceramic substrate, the inner layer wiring is fired and then the outermost layer wiring such as the uppermost layer is formed. Therefore, when the shrinkage error of the substrate material is large, the outermost layer wiring pattern and the inner layer wiring are formed. Since it is not possible to connect to the electrodes, it is necessary to form a land with a larger area than necessary in the outermost layer electrode part so as to predict and correct the shrinkage error, which is suitable for circuits that require high-density wiring. Causes problems. In addition, there is a method of preparing several screen plates for the wiring of the outermost layer according to the shrinkage error and using them according to the shrinkage rate of the multilayer ceramic substrate. It is uneconomical to prepare.

【0005】一方、最外層の配線を内層焼成と同時に行
えば大きなランドを必要としないが、この同時焼成法に
よっても多層セラミック基板そのものの収縮誤差はその
まま存在するので、最後の部品搭載時のクリーム半田印
刷において、その誤差のため必要な部分に印刷できない
場合が起こる。また部品実装においても所定の部品位置
とずれが生じる。
On the other hand, if the wiring of the outermost layer is performed simultaneously with the firing of the inner layer, a large land is not required. However, since the shrinkage error of the multilayer ceramic substrate itself remains as it is by this simultaneous firing method, the cream when mounting the last component In solder printing, there may be a case where printing cannot be performed on a necessary portion due to the error. Also, when mounting components, a deviation from a predetermined component position occurs.

【0006】第二にグリーンシート積層法による多層セ
ラミック基板は、グリーンシートの造膜方向によって幅
方向と長手方向によってもその収縮率が異なるので多層
セラミック基板の作製の支障となっている。
Secondly, the multilayer ceramic substrate produced by the green sheet laminating method has a different shrinkage factor depending on the film-forming direction of the green sheet depending on the width direction and the longitudinal direction, which is an obstacle to the production of the multilayer ceramic substrate.

【0007】これらの収縮誤差をなるべく少なくするた
めには、製造工程において、基板材料及びグリーンシー
ト組成の管理はもちろん、粉体ロットの違いやプレス圧
力、温度などの積層条件を十分管理する必要がある。し
かし、一般に収縮率の誤差は、±0.5%程度が存在する
と言われている。このことは多層セラミック基板の焼結
をともなうものに共通の課題である。
In order to reduce these shrinkage errors as much as possible, it is necessary to control not only the substrate material and the green sheet composition but also the lamination conditions such as the difference in powder lot, the press pressure, and the temperature in the manufacturing process. is there. However, it is generally said that the shrinkage ratio error is about ± 0.5%. This is a problem common to those involving the sintering of multilayer ceramic substrates.

【0008】そこでセラミック基板の作製にあたり、基
板構成シートを作製し、導体ペーストで電極パターンを
形成し、基板構成シートと別の電極パターンの形成済み
のシートを所望枚数積層した後に、基板構成シートの積
層体の両面、もしくは片面に、基板構成シートの焼成温
度で焼結しない収縮抑制シートを挟み込むように積層し
て、積層体を焼成する。しかる後、焼結しない収縮抑制
シートを取り除くことにより、焼成時の収縮が起こらな
い多層セラミック基板を作製する。以下に上述の従来の
多層セラミック基板の製造方法について説明する。
Therefore, in manufacturing a ceramic substrate, a substrate-constituting sheet is prepared, an electrode pattern is formed with a conductor paste, and a desired number of sheets on which another electrode pattern has been formed are laminated with the substrate-constituting sheet. A shrinkage suppression sheet that does not sinter at the firing temperature of the substrate-constituting sheet is laminated on both sides or one side of the laminate so that the laminate is fired. Thereafter, the shrinkage-restraining sheet that does not sinter is removed to produce a multilayer ceramic substrate that does not shrink during firing. Hereinafter, a method for manufacturing the above-mentioned conventional multilayer ceramic substrate will be described.

【0009】図3(a),(b)に示すように、基板構
成シート11は収縮抑制シート12はシート成形工程に
よりフィルム13上に形成される。収縮抑制シート12
の材料は基板構成シート11より高い焼結温度をもつ材
料を使用する。このようにして形成した基板構成シート
11を図3(c)に示すように孔あけ加工して、その孔
を導体ペースト14で充填する。つぎに図3(d)に示
すように、収縮抑制シート12を最上層と最下層とし、
その内部には複数の基板構成シート11を順次積層す
る。この時、基板構成シート11の間に内層導体パター
ン15が形成される。この積層シートを基板構成シート
11のみが焼結し、収縮抑制シート12が焼結しない温
度で焼成する。そして図3(e)に示すように、焼結し
ていない収縮抑制シート12を除去することにより収縮
差の存在しない多層セラミック基板が製作できる。
As shown in FIGS. 3 (a) and 3 (b), the substrate constituting sheet 11 and the shrinkage suppressing sheet 12 are formed on the film 13 by a sheet forming process. Shrinkage suppression sheet 12
As the material of (1), a material having a sintering temperature higher than that of the substrate constituting sheet 11 is used. The board-constituting sheet 11 thus formed is perforated as shown in FIG. 3C, and the holes are filled with the conductor paste 14. Next, as shown in FIG. 3D, the shrinkage suppression sheet 12 is the uppermost layer and the lowermost layer,
A plurality of substrate component sheets 11 are sequentially laminated inside the sheet. At this time, the inner layer conductor pattern 15 is formed between the substrate constituting sheets 11. This laminated sheet is fired at a temperature at which only the substrate constituent sheet 11 is sintered and the shrinkage suppression sheet 12 is not sintered. Then, as shown in FIG. 3E, by removing the non-sintered shrinkage suppression sheet 12, a multilayer ceramic substrate having no shrinkage difference can be manufactured.

【0010】[0010]

【発明が解決しようとする課題】しかしながら上記の従
来の方法では、収縮抑制シート12を除去した後に基板
構成シート11の最上層および最下層など最外層に配線
パターンを形成する場合に、内部電極、特に基板構成シ
ート11の最外層と収縮抑制シート12と接している内
部電極部のガラス成分と収縮抑制シート12の組成のア
ルミナが反応して形成された絶縁層によって、最外層の
配線パターンの形成ができないという問題点を有してい
た。
However, in the above-mentioned conventional method, when the wiring patterns are formed on the outermost layers such as the uppermost layer and the lowermost layer of the substrate constituting sheet 11 after removing the shrinkage suppressing sheet 12, the internal electrodes, In particular, a wiring pattern of the outermost layer is formed by an insulating layer formed by reacting the glass component of the internal electrode portion in contact with the outermost layer of the substrate constituent sheet 11 and the shrinkage suppressing sheet 12 with alumina of the composition of the shrinkage suppressing sheet 12. It had a problem that it could not be done.

【0011】本発明は上記従来の問題点を解決するもの
で、基板構成シートの最外層と収縮抑制シートと接して
いる内部電極のガラス成分と収縮制御シートの組成のア
ルミナとの反応を防ぎ、かつ絶縁層の形成をも防止し
て、最外層の配線パターンが容易に形成できる多層セラ
ミック基板の製造方法を提供することを目的とする。
The present invention solves the above-mentioned problems of the prior art by preventing the reaction between the glass component of the internal electrode in contact with the outermost layer of the substrate-constituting sheet and the shrinkage suppressing sheet and the alumina of the shrinkage controlling sheet, Moreover, it is an object of the present invention to provide a method for manufacturing a multilayer ceramic substrate, which can prevent the formation of an insulating layer and easily form an outermost wiring pattern.

【0012】[0012]

【課題を解決するための手段】この目的を達成するため
に本発明の多層セラミック基板の製造方法は、基板構成
シートと収縮抑制シートの両方に形設した孔に導体ペー
ストを埋めて、電極を形成し、その収縮抑制シートを最
外層として、内部に複数の基板構成シートを順次積層し
た多層シートを焼成した後、最外層の収縮抑制シートお
よびそれらの柱状電極を除去する方法である。
In order to achieve this object, a method for manufacturing a multilayer ceramic substrate according to the present invention is to fill a conductor paste into holes formed in both a substrate constituent sheet and a shrinkage suppression sheet to form an electrode. This is a method of forming a shrinkage-suppressing sheet as the outermost layer, firing a multilayer sheet in which a plurality of substrate-constituting sheets are sequentially laminated inside, and then removing the outermost shrinkage-restraining sheet and the columnar electrodes thereof.

【0013】[0013]

【作用】この方法において、収縮抑制シートの組成のア
ルミナと内部電極のガラス成分との反応を防ぎ、基板構
成シートの最外層に絶縁層を形成させないこととなる。
In this method, the reaction between the alumina of the composition of the shrinkage suppressing sheet and the glass component of the internal electrode is prevented, and the insulating layer is not formed on the outermost layer of the substrate constituting sheet.

【0014】[0014]

【実施例】(実施例1)以下本発明の一実施例につい
て、図面を参照しながら説明する。
(Embodiment 1) An embodiment of the present invention will be described below with reference to the drawings.

【0015】図1(a),(b)に示すように基板構成
シート1と収縮抑制シート2はシート成形工法によりフ
ィルム3上に形成される。基板構成シート1の材料は、
アルミナにガラスを含ませた低温焼結材料であり、収縮
抑制シート2の材料は基板構成シート1より高い焼結温
度をもつ材料、例えば、純アルミナ、窒化ボロン、酸化
マグネシウムなどである。このようにして形成した両シ
ートを図1(c),(d)に示すように孔あけ加工し、
その孔を導体ペースト4で充填する。この導体ペースト
4の主材料としては一般に酸化銅を使用するが、他の材
料、例えば銀、銀とパラジウムとの合金、銀と白金との
合金、銅などを使用してもよい。つぎに図1(e)に示
すように、収縮抑制シート2を最上層と最下層とし、複
数の基板構成シート1を順次積層する。このとき、基板
構成シート1の間に内層導体パターン5が形成される。
この積層シートを低温焼結材料からなる基板構成シート
1のみが焼結する温度で焼成し、この温度で焼結しない
収縮抑制シート2の最上層と最下層のみを除去すると、
図1(f)に示すように柱状電極6が形成される。さら
に図1(g)に示すように、柱状電極6を基板構成シー
ト1の上下面と同一面に合わせて加工除去する。
As shown in FIGS. 1A and 1B, the substrate-constituting sheet 1 and the shrinkage-restraining sheet 2 are formed on the film 3 by a sheet forming method. The material of the substrate component sheet 1 is
It is a low temperature sintering material containing glass in alumina, and the material of the shrinkage suppression sheet 2 is a material having a sintering temperature higher than that of the substrate constituent sheet 1, for example, pure alumina, boron nitride, magnesium oxide and the like. Both sheets thus formed are perforated as shown in FIGS. 1 (c) and 1 (d),
The hole is filled with the conductor paste 4. Copper oxide is generally used as a main material of the conductor paste 4, but other materials such as silver, an alloy of silver and palladium, an alloy of silver and platinum, and copper may be used. Next, as shown in FIG. 1E, the shrinkage suppression sheet 2 is used as the uppermost layer and the lowermost layer, and a plurality of substrate component sheets 1 are sequentially laminated. At this time, the inner layer conductor pattern 5 is formed between the substrate constituting sheets 1.
If this laminated sheet is fired at a temperature at which only the substrate-constituting sheet 1 made of a low-temperature sintering material is sintered, and only the uppermost layer and the lowermost layer of the shrinkage suppression sheet 2 not sintered at this temperature are removed,
The columnar electrodes 6 are formed as shown in FIG. Further, as shown in FIG. 1G, the columnar electrodes 6 are processed and removed so as to be flush with the upper and lower surfaces of the substrate constituting sheet 1.

【0016】以上のように本実施例によれば、収縮抑制
シートに孔をあけ、導体ペーストを印刷、焼成すること
で、柱状電極6を形成し、基板構成シート面に合わせて
除去することにより、基板構成シート1の最外層と収縮
抑制シート2と接している内部電極のガラス成分と収縮
抑制シート2の組成のアルミナとの反応を防ぎ、かつ絶
縁層の形成を防ぎ、最外層の配線パターンの形成を容易
にできる。
As described above, according to this embodiment, the columnar electrodes 6 are formed by forming holes in the shrinkage suppressing sheet, printing and firing the conductor paste, and removing the columnar electrodes 6 in accordance with the surface of the substrate constituting sheet. A wiring pattern of the outermost layer, which prevents the reaction between the glass component of the internal electrode in contact with the outermost layer of the substrate constituent sheet 1 and the shrinkage suppressing sheet 2 and the alumina of the composition of the shrinkage suppressing sheet 2, and prevents the formation of an insulating layer. Can be easily formed.

【0017】(実施例2)以下本発明の第2の実施例に
ついて図面を参照しながら説明する。
(Second Embodiment) A second embodiment of the present invention will be described below with reference to the drawings.

【0018】上述の第1の実施例の図1(a)ないし図
1(e)で説明したようにして、図2(a)に示すよう
に収縮抑制シート2を最上層と最下層とし、複数の基板
構成シート1を順次積層する。この積層シートを基板構
成シート1のみが焼結する温度で焼成した後、図2
(b)に示すように、焼結しない収縮抑制シート2の最
上層と最下層と収縮抑制シート2に含まれた柱状電極6
を同時に除去する。このとき柱状電極6は基板構成シー
ト1の面に合わせて除去する。
As described with reference to FIGS. 1 (a) to 1 (e) of the first embodiment, the shrinkage suppressing sheet 2 is the uppermost layer and the lowermost layer as shown in FIG. 2 (a), A plurality of substrate constituting sheets 1 are sequentially laminated. After firing this laminated sheet at a temperature at which only the substrate-constituting sheet 1 is sintered,
As shown in (b), the columnar electrodes 6 included in the uppermost layer and the lowermost layer of the shrinkage suppression sheet 2 which are not sintered and the shrinkage suppression sheet 2
Are removed at the same time. At this time, the columnar electrodes 6 are removed according to the surface of the substrate constituting sheet 1.

【0019】本実施例が第1の実施例と異なるのは、柱
状電極6を収縮抑制シート2を除去した後に除去せずに
収縮抑制シート2と、同時に除去する点である。
The present embodiment differs from the first embodiment in that the columnar electrodes 6 are removed at the same time as the shrinkage suppression sheet 2 without removing the shrinkage suppression sheet 2.

【0020】以上のように本実施例によれば、第1の実
施例と同等の効果が得られる。
As described above, according to this embodiment, the same effect as that of the first embodiment can be obtained.

【0021】[0021]

【発明の効果】以上の実施例の説明からも明らかなよう
に本発明は、基板構成シートと収縮抑制シートの両方に
形設した孔に導体ペーストを埋めて、電極を形成し、そ
の収縮制御シートを最外層として、その内部に複数の基
板構成シートを順次積層した多層シートを焼成した後、
最外層の収縮抑制シートおよびそれらの柱状電極を除去
する方法により、基板構成シートの最外層と収縮抑制シ
ートと接している内部電極部のガラス成分と収縮抑制シ
ートの組成のアルミナとの反応を防ぎ、かつ絶縁層の形
成をも防止して最外層の配線パターンが容易に形成でき
る優れた多層セラミック基板の製造方法を実現できるも
のである。
As is apparent from the above description of the embodiments, the present invention fills holes formed in both the substrate component sheet and the shrinkage suppression sheet with a conductive paste to form electrodes, and controls shrinkage thereof. After firing a multilayer sheet in which a plurality of substrate constituent sheets are sequentially laminated inside the sheet as the outermost layer,
By the method of removing the outermost layer shrinkage suppressing sheet and those columnar electrodes, it is possible to prevent the reaction between the glass component of the inner electrode portion in contact with the outermost layer of the substrate constituting sheet and the shrinkage suppressing sheet and the alumina of the composition of the shrinkage suppressing sheet. In addition, it is possible to realize an excellent method for manufacturing a multilayer ceramic substrate in which the formation of the insulating layer can be prevented and the wiring pattern of the outermost layer can be easily formed.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の第1の実施例の多層セラミック基板の
製造方法の工程順に示した断面略図
FIG. 1 is a schematic sectional view showing the order of steps in a method for manufacturing a multilayer ceramic substrate according to a first embodiment of the present invention.

【図2】本発明の第2の実施例の多層セラミック基板の
製造方法の工程順に示した断面略図
FIG. 2 is a schematic cross-sectional view showing the order of steps in a method for manufacturing a multilayer ceramic substrate according to a second embodiment of the present invention.

【図3】従来の多層セラミック基板の製造方法の工程順
に示した断面略図
FIG. 3 is a schematic cross-sectional view showing the order of steps in a conventional method for manufacturing a multilayer ceramic substrate.

【符号の説明】[Explanation of symbols]

1 基板構成シート 2 収縮抑制シート 4 導体ペースト 6 柱状電極 1 Substrate constituent sheet 2 Shrinkage suppression sheet 4 Conductor paste 6 Columnar electrode

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】基板構成シートと収縮抑制シートの両方に
形設した孔に導体ペーストを埋めて電極を形成し、前記
収縮抑制シートを最外層として、その内部に複数の基板
構成シートを順次積層した多層シートを焼成した後、最
外層の収縮抑制シートを除去し、ついで、形成された柱
状電極を基板構成シートの同一面に合わせて除去する多
層セラミック基板の製造方法。
1. A conductor paste is embedded in holes formed in both a substrate constituent sheet and a shrinkage suppressing sheet to form an electrode, and the shrinkage suppressing sheet is used as an outermost layer, and a plurality of substrate constituent sheets are sequentially laminated therein. A method for manufacturing a multilayer ceramic substrate, comprising: firing the multilayer sheet, removing the outermost shrinkage suppressing sheet, and then removing the formed columnar electrodes so as to be aligned with the same surface of the substrate constituting sheet.
【請求項2】基板構成シートと収縮抑制シートの両方に
形設した孔に導体ペーストを埋めて電極を形成し、前記
収縮抑制シートを最外層として、その内部に複数の基板
構成シートを順次積層した多層シートを焼成した後、最
外層の収縮抑制シートと、それらに含まれた柱状電極と
を同時に基板構成シートの同一面に合わせて除去する多
層セラミック基板の製造方法。
2. A conductor paste is embedded in holes formed in both the substrate constituent sheet and the shrinkage suppression sheet to form an electrode, and the shrinkage suppression sheet is used as an outermost layer, and a plurality of substrate constituent sheets are sequentially laminated therein. A method for manufacturing a multilayer ceramic substrate, comprising: firing the multilayer sheet and then removing the outermost shrinkage-restraining sheet and the columnar electrodes contained therein simultaneously on the same surface of the substrate-constituting sheet.
【請求項3】収縮抑御シートが基板構成シートより高い
焼結温度を有し、収縮抑制シートの焼結温度と基板構成
シートの焼結温度の範囲内の温度で焼結する請求項1ま
たは2記載の多層セラミック基板の製造方法。
3. The shrinkage control sheet has a sintering temperature higher than that of the substrate constituent sheet, and is sintered at a temperature within a range of a sintering temperature of the shrinkage suppressing sheet and a sintering temperature of the substrate constituent sheet. 2. The method for manufacturing a multilayer ceramic substrate according to 2.
【請求項4】導体ペーストが、酸化銅、銀、銀とパラジ
ウムとの合金、銀と白金との合金、銅からなる群のうち
から選ばれた導体ペーストである請求項1ないし3のい
づれかに記載した多層セラミック基板の製造方法。
4. The conductor paste according to claim 1, which is selected from the group consisting of copper oxide, silver, an alloy of silver and palladium, an alloy of silver and platinum, and copper. A method for manufacturing the described multilayer ceramic substrate.
JP21311292A 1992-08-11 1992-08-11 Production of multilayer ceramic board Pending JPH0661650A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP21311292A JPH0661650A (en) 1992-08-11 1992-08-11 Production of multilayer ceramic board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP21311292A JPH0661650A (en) 1992-08-11 1992-08-11 Production of multilayer ceramic board

Publications (1)

Publication Number Publication Date
JPH0661650A true JPH0661650A (en) 1994-03-04

Family

ID=16633782

Family Applications (1)

Application Number Title Priority Date Filing Date
JP21311292A Pending JPH0661650A (en) 1992-08-11 1992-08-11 Production of multilayer ceramic board

Country Status (1)

Country Link
JP (1) JPH0661650A (en)

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