JPH0661350A - Layout processing for semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To prevent a wiring from becoming long without making a wiring bypass even in the case where the number of positions, where the wiring can be passed through on each standard cell row, is enough to the number of positions required for the wiring to pass through the upper part of each standard cell row. CONSTITUTION:Standard cells are laid out in a step 1 and thereafter, the standard cells are laid out side by side in a step 2, whereby standard cell rows are constituted. Then, the number of positions required for a wiring to pass through the upper part of each standard cell row is calculated in a step 3 and the number of positions, where the wiring can be passed through on each standard cell row, is calculated in a step 4. A feedthrough cell is inserted in each standard cell row in a step 5. At this time, even in the case where the number of positions required for the wiring, which is calculated in the step 3, is compared with the number of positions, where the wiring can be passed through, calculated in the step 4 and the number of positions, where the wiring can be passed through, is enough to the number of positions required for the wiring, the feedthrough cell is inserted.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a layout processing method for a semiconductor integrated circuit, and more particularly to a layout processing method for a standard cell in which wiring passes over a standard cell row.

[0002]

2. Description of the Related Art In a conventional semiconductor integrated circuit layout processing method, when a wiring passes over a standard cell row in a standard cell, processing is performed as follows.

On the standard cell row, there are positions where wiring can pass and positions where wiring cannot pass. The position where the wiring cannot pass refers to a place where the wiring cannot pass due to the design rule or a portion where the wiring layer is already used in the standard cell on the standard cell row.

Therefore, the number of wirings passing through the standard cell row and the number of positions where wirings can pass through the standard cell row are calculated,
When the number of wiring passable positions on the standard cell row is sufficient with respect to the number of wirings passing on the standard cell row, wiring is performed at a wiring passable position such that the wiring length is as short as possible.

When the number of wiring passages on the standard cell row is less than the number of wirings passing on the standard cell row, it is used as a dummy cell for wiring on the cell. The feed-through cell is inserted into a position on the standard cell row where the wiring length is as short as possible due to the shortage of positions where wiring can pass, and wiring is performed on the feed-through cell.

However, if the number of wiring passage positions on the standard cell row is equal to or slightly larger than the number of wiring passages on the standard cell row, the wiring passage position is located at a place distant from the terminal. Even if there is, it will pass over it,
As a result, the wiring had detoured.

This will be described with reference to FIG. FIG. 4 shows standard cells that form standard cell rows 101, 102, and 103 by arranging standard cells and arranging the standard cells side by side. Now, from the terminals 108 to 115 on the standard cells on the standard cell row 101 to the terminals 116 on the standard cell row 103.
Wire up to 123.

At this time, since the number of wirings passing through the standard cell row 102 is eight, the number of positions required for wiring on the standard cell row 102 is eight. In contrast, standard cell row 1
The number of positions through which wiring can pass on 02 is 124 to 131, which is eight. That is, the number of positions where wiring can pass on the standard cell row is satisfied with respect to the number of positions required for wiring that passes on the standard cell row. Therefore, each wiring is performed by passing over the wiring passage possible position on the standard cell row such that the wiring length becomes as small as possible.

For example, wiring is made from the terminal 111 on the standard cell 104 to the terminal 119 on the standard cell 106. Therefore, a wiring passable position where the wiring length is as small as possible is searched from the above eight locations, and wiring is performed on the wiring passable position 124 where the wiring length is the smallest. However, although the terminal 111 on the standard cell row 104 is on the straight line with the terminal 119 on the standard cell row 106,
Since the central portion of the above is a position where the wiring cannot pass, the on-cell passing wiring was performed at the wiring passable position 124 apart from the terminal.

[0010]

In the conventional layout processing method for a semiconductor integrated circuit, when a wiring passes through a standard cell row, the number of wirings passing through the standard cell row is larger than the number of wirings passing through the standard cell row. When the number of positions where wiring can pass is sufficient, wiring was performed at positions where wiring could pass.

However, in such a method, when the number of wiring passage positions on the standard cell row is equal to or slightly larger than the number of wiring lines passing on the standard cell, the wiring passage position from the terminal is determined. Even if it is away from the terminals,
Since it is passed over it, the wiring route is detoured and the wiring length is increased. Therefore, there is a problem that the width of the wiring region is expanded.

[0012]

According to the present invention, in the layout design of a standard cell including a standard cell row, a means for arranging the standard cell and the number of positions required for wiring passing on each standard cell row are calculated. Means, means for calculating the number of wiring passable positions on each standard cell row, the above calculated,
Means for comparing the number of positions required for wiring and the number of positions where wiring can pass, means for calculating the number of feed-through cells used as dummy cells for performing wiring on the standard cell, and means for arranging the standard cell Among them, there is a means for inserting the feedthrough cell into the standard cell row and a means for wiring between the standard cells, and when performing wiring passing over the standard cell row, it passes over the standard cell row. And a means for inserting the feedthrough cell so that the number of wiring passable positions is larger than the number of wirings.

[0013]

The present invention will be described below with reference to the drawings.

FIG. 1 is a flow chart for explaining the first embodiment of the present invention. FIG. 2 is a layout diagram of a semiconductor chip using this embodiment.

In the feedthrough cell insertion method of this embodiment, as shown in the flow chart of FIG. 1, the standard cells are arranged in step 1 and then the standard cells are arranged side by side in step 2. Make up. Next step 3
Then, the number of positions required for the wiring passing on each standard cell row is calculated, and at step 4, the number of wiring passable positions on each standard cell row is calculated. Then, in step 5, a feedthrough cell is inserted. At this time, when the number of positions required for wiring calculated in step 3 is compared with the number of positions where wiring can pass calculated in step 4 and the number of positions where wiring can pass is sufficient for the number of positions required for wiring But insert a feedthrough cell. In step 6, it is determined whether or not the number of positions required for wiring and the number of positions where wiring can pass through have been calculated for all standard cell columns, and the process is executed until calculation is performed for all standard cell columns. When the process is executed for all the standard cell columns, wiring is performed in step 7.

FIG. 2 is a layout diagram of a semiconductor chip using the first embodiment, where A is a diagram before wiring and B is a diagram after wiring.

In both figures, the standard cells 11 to 13 are constructed by arranging the standard cells side by side.

First, in FIG. A, from terminals 18 to 25 on the standard cell row 11 to terminals 26 to 33 on the standard cell row 13.
Trying to wire up. At this time, since the number of wirings passing through the standard cell row 12 is eight, the number of positions on the standard cell row 12 required for wiring is eight. On the other hand, the number of positions on the standard cell row 12 through which the wiring can pass is 34 to 41. That is, the number of positions where wiring can pass on the standard cell row is satisfied with respect to the number of positions required for wiring that passes on the standard cell row.

However, in order to increase the number of positions where wiring can pass on the standard cell row more than the number of positions required for wiring that passes on the standard cell row, the feedthrough cells 51 to 58 are arranged on the standard cell row 12. insert. Then, from the terminals 18 to 25 on the standard cell row 11 to the terminals 26 to 3 on the standard cell row 13.
Since the wirings up to 3 pass through the wiring passable positions where the wiring length is as small as possible, the wirings pass through the inserted feedthrough cells.

For example, from the terminal 21 on the standard cell 14,
The terminals 29 on the standard cell 16 are wired. Therefore, a wiring passable position where the wiring length is as small as possible is searched from the originally existing wiring passageable positions on the standard cell row of 8 positions and the inserted feedthrough cells of 16 positions in total, and the wiring is carried out in that position. Wiring is performed on the feedthrough cell 51 having the minimum length. Therefore, it can be said that the wiring in which the feedthrough cell is inserted can be the wiring having the minimum wiring length. Therefore, there is no need to route the wiring, and the width of the wiring region can be reduced.

FIG. 3 is a flow chart of the second embodiment of the present invention. In the second embodiment, as shown in the flowchart of FIG. 3, the standard cells are arranged in step 61, and then step 62 is performed.
A standard cell column is formed by arranging the standard cells side by side with. Next, at step 63, the number of positions required for wirings passing through each standard cell row is calculated, and at step 64, the number of wiring passable positions on each standard cell row is calculated for all standard cell rows in the chip. Then, in step 65, a number obtained by subtracting the number of wiring passable positions on each standard cell row calculated in step 64 from the number of positions required for wiring on each standard cell row calculated in step 63 is calculated. Determines whether exceeds the default value. Exceeding the default value means that the number of wiring passable positions on the standard cell row is insufficient. Furthermore, it is expected that a large number of feedthrough cells will be inserted on the standard cell row.

As described above, when a large number of feedthrough cells are inserted on a specific standard cell row, the width of the cell row is expanded and the chip area is also expanded accordingly.
Therefore, in step 66, the standard cells on the standard cell row as described above are moved to another standard cell row and rearranged.

Then, the number of positions required for wiring passing through each standard cell row and the number of wiring passable positions on the standard cell row are calculated again, and the standard cell is calculated from the number of locations required for wiring on the standard cell row. Repeat until there is no cell row in which the number of possible wiring passage positions on the row exceeds the default value. When the standard cell row as described above is gone, a feedthrough cell is inserted in step 67 and wiring is performed in step 68.

As a result, the width of a part of the standard cell row is not expanded, and the chip area is reduced.

[0025]

As described above, according to the present invention, in the layout design of the standard cell including the standard cell row,
Even if the number of wires that can pass through the standard cell row is sufficient for the number of wires that pass through the standard cell row, by inserting an appropriate amount of feed-through cells, wiring that reduces the wiring length is performed. It becomes possible.

In other words, even if there is a wiring passage position on the standard cell row, it is possible to carry out wiring at a position where the wiring length becomes shorter without using the position away from the terminal.

Therefore, it is possible to perform wiring without bypassing the wiring path, and there is an effect that the width of the wiring region is reduced.

[Brief description of drawings]

FIG. 1 is a flowchart illustrating a first embodiment of the present invention.

FIG. 2 is a layout diagram of a semiconductor chip using the first embodiment of the present invention.

FIG. 3 is a flow chart of a second embodiment of the present invention.

FIG. 4 is a layout diagram of a semiconductor chip created by a conventional technique.

[Explanation of symbols]

1 standard cell placement step 2 standard cell row generation step 3 step for extracting the number of positions required for wiring passing on each standard cell row 4 step for extracting the number of wiring passable positions on each standard cell row 5 feedthrough cell Insert step 6 Step 7 to check whether all standard cell rows have been executed 7 Wiring step 11 to 13 Standard cell row 14 to 17 Standard cell 18 to 33 Terminal 34 to 41 Wiring passable position 51 to 58 Feed through cell 61 Standard cell arrangement Step 62 Standard cell string generation step 63 Steps for extracting the number of positions required for wiring passing on each standard cell string 64 Steps for extracting the number of wiring passable positions on each standard cell row 65 Required number of positions-possible positions Step 66 to judge whether the number exceeds the default value. Move to upper level cell column step 67 feed through cell inserting step 68 wirings step 101 to 103 standard cell rows 104 to 107 standard cells 108-123 terminals 124-131 wiring passable position

Claims (1)

[Claims] 1. In a layout design of a standard cell including a standard cell row, a means for arranging the standard cell, a means for calculating the number of positions required for wiring passing on each standard cell row, and a means for each standard cell row Of the number of possible wiring passage positions, a means for comparing the calculated number of positions required for the wiring with the number of possible wiring passage positions, and a dummy cell for performing wiring on the standard cell A means for calculating the number of feed-through cells, a means for arranging the standard cells, a means for inserting the feed-through cells into a standard cell row, and a means for wiring between the standard cells; When the wiring passing through the cell row is performed, the feedthrough cell is inserted so that the number of wiring passable positions is larger than the number of wiring passing through the standard cell row. Layout processing method of the conductor integrated circuit.