JPH0660676A - Semiconductor storage - Google Patents

Abstract

PURPOSE:To provide a semiconductor storage in which a high speed reading can be executed even in a large-scale storage cell array. CONSTITUTION:A storage cell array 11 is formed of EPROM transistors Q411-Q4mn, one cell is selected by outputs from a column decoder 13, a row decoder 14, and a cell output (a) is obtained corresponding to a first load transistor Q11. One of dummy EPROM transistors Q41-Q4m is selected corresponding to outputs of the decoders 13, 14, and a dummy cell output (b) is selected corresponding to a second load transistor Q12. The dummy cell output (b) has the same bit line capacity as that of a storage cell output, and the outputs (a) and (b) are compared by a differential amplifier 15. Thus, a reference voltage of the amplifier 15 of the output (b) is varied by following-up a variation in the output (a) of the cell.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device such as a mask ROM, EPROM, or EEPROM which outputs a read signal from a memory cell array using a differential sense amplifier.

[0002]

2. Description of the Related Art As means for reading stored data from a semiconductor memory composed of a memory cell array, as disclosed in, for example, Japanese Patent Laid-Open No. 59-40397,
There is known a differential type sense amplifier which compares a read output from a memory cell array with a predetermined set voltage Vref in a differential amplifier.

FIG. 6 shows a circuit example of such a conventional semiconductor memory device. EPROM transistors Q411 to Q4mn forming memory cells in n columns and m rows, respectively.
The memory cell array 11 is arranged. The drains of the EPROM transistors in each column of the memory cell array 11 are commonly connected to the bit lines b11 to b1n in column units, and the bit lines b11 to b1n are connected to the column select transistors Q31 to Q3n, respectively.

The read address of the memory cell array 11 is set by the address counter 12, and the address data from the address counter 12 is supplied to the column decoder 13 and the row decoder 14, and the column decoder 13 outputs n columns. Column select signals SC1 to SCn for selecting one are output. The column select signals SC1 to SCn are supplied to the gates of the column select transistors Q31 to Q3n, respectively.

Further, the row selection signal SR from the row decoder 14
1 to SRm are supplied to the commonly connected gates of the EPROM transistors in each row unit, and one EP that constitutes a memory cell array by the column selection signal and the row selection signal.
ROM transistor is selected and this selected EPR
The data stored in the OM transistor is read out as the memory cell output a via the selected column select transistor.

Each EPRO forming the memory cell array 11
The M transistors Q411 to Q4mn are in a written state (threshold voltage Vt is 4.5 V or more) or an erased state (threshold voltage is approximately 1.5 V) corresponding to data "1" or "0", respectively. ) Is set.

The memory cell output a is supplied to the load transistor Q1 of the sense amplifier circuit which constitutes the output judging circuit. The memory cell output a is compared with the reference voltage Vref from a predetermined reference power source in the differential amplifier 15. To be done. The output from the differential amplifier 15 is taken out as the output O via the inverter circuit 16. That is, the high level or low level of the output is determined depending on whether or not the level of the memory cell output a exceeds the reference voltage Vref.

In such a semiconductor memory device, when the EPROM transistor forming the selected memory cell is in the off state and the output a becomes the high level, FIG.
As shown in (A), the output a changes to the low voltage side due to the redistribution of charges by the bit line capacitance, and rises at the time constant determined by the ON resistance of the load transistor Q1 and the bit line capacitance. When the output a exceeds the reference voltage Vref,
After the delay t3 of the sense amplifier, as shown in FIG. 9B, the output O of the sense amplifier is set to the high level. Therefore, as the memory scale increases and the bit line capacity increases, the read time inevitably increases.

[0009]

SUMMARY OF THE INVENTION The present invention has been made in view of the above points, and the reference voltage is changed in accordance with the change in the output of the selected memory cell in the memory cell array. For example, it is an object of the present invention to provide a semiconductor memory device capable of high-speed reading of write data even if the memory scale increases and the bit line capacity increases.

[0010]

A semiconductor memory device according to the present invention includes a memory cell array in which one memory cell is selected based on a column selection signal and a row selection signal corresponding to an address command, and A dummy cell unit configured to include at least one dummy cell having the same configuration as the memory cell, and a capacitive load equal to a capacitive load connected to one bit line of the memory cell array is set. A first and a second load transistor to which the output of the cell array and the output from the dummy cell means are respectively coupled, wherein the dummy cell means and the second load transistor are column select signals of the memory cell array. Is connected through a dummy column select transistor whose conduction state is set by a signal corresponding to. Then, the memory cell output and the dummy cell output obtained respectively corresponding to the first and second load transistors are judged by the differential sense amplifier output judging means.

[0011]

In the semiconductor memory device configured as described above, one memory cell is selected in response to addressing and at the same time one dummy cell is selected, and the memory cell output a and the dummy cell output b are the first It comes from the first and second load transistors. And output a
And b are supplied to the differential sense amplifier circuit, and output b
The output a is determined on the basis of the reference value, and in this case, the output b is changed in a state of following the fluctuation of the memory cell output a, and the output a is changed to the predetermined reference voltage V.
The difference is generated in the sense amplifier determination means earlier than the time when ref is exceeded, and high-speed reading becomes possible.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows the configuration thereof. As in the conventional example shown in FIG. 6, EPROM transistors Q411 to Q4m forming memory cells arranged in m rows and n columns respectively.
The memory cell array 11 including n is provided, and the drains of the EPROM transistors in each column forming the memory cell array 11 are commonly connected to the bit lines b11 to b1n in each column unit. The connection point of each column unit is connected to the first load transistor Q11 as the memory cell output a via the column select transistors Q31 to Q3n.

A column select signal S from a column decoder 13 generated corresponding to the address data of the address counter 12 is applied to each gate of the column select transistors Q31 to Q3n.
C1 to SCn are supplied respectively. In addition, the EPROM transistors Q411 to Q4mn of the memory cell array 11 are
Are connected in common to each row unit, and the row selection signal S from the row decoder 14 which is also generated corresponding to the address data from the address counter 12 is applied to the gate of each row unit.
R1 to SRm are supplied.

Therefore, one EPROM transistor is selected corresponding to the address data output from the address counter 12, the read data from the selected EPROM transistor is output as a, and the drain of the first load transistor Q11 is selected. Is supplied to.

A dummy cell circuit 21 including dummy EPROM transistors Q41 to Q4m corresponding to each row of the memory cell array 11 is provided. The drains of the EPROM transistors Q41 to Q4m of the dummy cell circuit 21 are commonly connected to the dummy bit line b1d, and the row selection signals SR1 to SRm from the row decoder 14 are supplied to the respective gates thereof. The dummy bit line b1d is connected to the dummy column select transistor Q3, and the dummy cell output b is taken out from this dummy column select transistor Q3 and supplied to the drain of the second load transistor Q12.

The dummy column select signal S from the dummy column decoder 22 is applied to the gate of the dummy column select transistor Q3.
D is supplied, and when the column decoder 13 generates one column selection signal, the dummy column selection signal SD is generated in synchronization with the column selection signal. Then, in response to the dummy column selection signal SD, the second load transistor Q
A dummy cell output b is generated corresponding to 12 and this output b is supplied to the non-inverting side input of the differential amplifier 15 as a reference voltage of the differential sense amplifier circuit. That is, the dummy cell circuit 21 and the dummy column select transistor Q
The reference voltage generating circuit 23 is constituted by 3 and the like.

A memory cell output a obtained corresponding to the first and second load transistors Q11 and Q12, respectively.
The dummy cell output b and the dummy cell output b are compared by the differential amplifier 15 constituting the sense amplifier circuit, and the memory cell output determination is performed. The output from the differential amplifier 15 is obtained as the determination output O via the inverter circuit 16. To be

Here, the dummy EPROM transistor Q
41 to Q4m is always erased (threshold Vt is 1.5V)
Is. Then, the output voltage Vb corresponding to the dummy cell output b is set to Vref when the dummy column select transistor Q3 is in the conductive state and in the circuit steady state, and the EPROM transistor constituting the memory cell array 11 is erased (Vt. When the output voltage of the memory cell output a in the state of V is 1.5 V) and the output voltage in the written state is Vw, Vs <Vref <Vw (1) must be satisfied.

Therefore, the second load transistor Q12
Ratio of gate width WQ2 to gate length LQ2 "WQ2 / LQ2
"Is the gate width WQ1 of the first load transistor Q11.
The first and second load transistors Q11 and Q12 are determined so as to satisfy the following expression for the ratio "WQ1 / LQ1" of the gate length LQ1 to the gate length LQ1. (WQ2 / LQ2)> (WQ1 / LQ1) (2) FIG. 2A shows a concrete circuit example of the dummy column decoder 22. The column selection signal S output from the column decoder 13 is shown in FIG.
Two different sets of C1 to SCn are input to the exclusive OR circuits 251, 252, ... 262, ... And the last one
A dummy column selection signal SD is output from one exclusive OR circuit 27. Therefore, when the column selection signals SC1 to SCn are generated as shown in FIG.
When any one of these column selection signals SC1 to SCn is at the high level, the dummy column selection signal SD is set to the high level and the dummy column selection transistor Q3 is rendered conductive.

In the semiconductor memory device configured as described above, for example, the column address signal c from the address counter 12
a and the row address signal ra are output, and the column decoder 13
When the column selection signal SC1 is set to the high level and the row selection signal SR1 is set to the high level from the row decoder 14,
The column select transistor Q31 is turned on and the EPROM transistor Q411 of the memory cell array 11 is selected.
At the same time, the dummy column select transistor Q3 of the reference voltage generating circuit 23 becomes conductive and the dummy EPROM transistor Q41 is selected.

FIG. 3 shows the operation-related part in such a state by extracting it, and the operation will be described below using this circuit. In this figure, Cb11 is a bit line b
11 is a bit line capacitance composed of drain junction capacitances of the EPROM transistors Q421 to Q4m1 connected to 11 and in a non-selected state, where Cbb is the bit line capacitance per memory cell, "Cb11 = Cbb * (m -1) ".

Cb1d is a dummy bit line capacitance composed of drain junction capacitances of the dummy EPROM transistors Q42 to Q4m connected to the dummy bit line b1d and in a non-selected state. The dummy bit line capacitance per cell is C.
If dd, then "Cb1d = Cdd * (m-1)". Ca is a parasitic capacitance connected to the memory cell output a, and C
b is a parasitic capacitance connected to the dummy cell output b.

Column selection signal SC1, dummy column selection signal S
D and row selection signal SR1 are low level (ground potential)
At this time, the column select transistor Q31 and the dummy column select transistor Q3 are turned off, and E
Both the PROM transistor Q411 and the dummy EPROM transistor Q41 are in the non-selected state, and the voltage Va of the memory cell output a and the voltage Vb of the dummy cell output b are set.
Are both at the power supply voltage Vcc.

The voltages Vb11 and Vb1d of the bit line b11 and the dummy bit line b1d are at the ground potential (0V) because the bit line capacitance Cb11 and the dummy bit line capacitance Cb1d are discharged.

In such a state, when the row selection signal SR1, the column selection signal SC1 and the dummy column selection signal SD become high level and the column select transistor Q31 and the dummy column select transistor Q3 become conductive, the memory cell output a is connected. The charge is redistributed between the generated parasitic capacitance Ca and the bit line capacitance Cb11, and the voltage V of the memory cell output a is
a transiently drops as follows. Va = Ca / (Ca + Cb11) .Vcc (3) At this time, also in the dummy cell output b, charge is redistributed between the parasitic capacitance Cb and the dummy bit line capacitance Cb1d, and the dummy cell output b The voltage Vb transiently drops as shown by the following equation. Vb = Cb / (Cb + Cb1d) .Vcc (4) Here, the circuit configurations seen from the memory cell output a and the dummy cell output b are made equal, and the wiring area and the drain area of the connected transistor are By making the layout shapes equal, the parasitic capacitances Ca and Cb can be made equal.

Further, a dummy EPROM transistor Q41
Of the EPROM transistor Q411 and the layout shapes thereof are also equal, the bit line capacitance Cbb per cell and the dummy bit line capacitance Cdd can be made equal, and the dummy bit line b1d of the dummy memory cell circuit 21 can be made equal. The dummy bit line capacitance Cb1d and the bit line capacitance Cb11 can be made equal by setting the number of dummy EPROM transistors connected to the same to the number of EPROM transistors connected to the bit line b11.

FIG. 4 shows operation waveforms when the EPROM transistor Q411 of the memory cell array 11 is set to the write state.
When 1 is in the written state, the bit line capacitance Cb11 is gradually charged with a time constant determined by the conduction resistance of the first load transistor Q11 and the bit line capacitance Cb11 after the output voltage of the equation (3) changes. As a result, the voltage Va of the memory cell output a reaches the voltage Vw in the written state.

Therefore, as shown in FIG. 7, in the prior art, the voltage of the memory cell output a exceeds the fixed voltage Vref and the voltage between the inverting input terminal and the non-inverting input terminal of the differential amplifier 15 is increased. The sense amplifier determination output O is fixed at a high level after the difference voltage ΔV at
The read time tacc becomes long.

On the other hand, according to the device shown in the embodiment, the dummy cell output b serving as the reference voltage supplied to the differential amplifier 15 follows the fluctuation of the memory cell output a, and therefore the memory cell Before the output a exceeds the reference voltage Vref, the differential voltage ΔV is generated between the inverting side input terminal and the non-inverting side input terminal of the differential amplifier 15.
Therefore, the delay due to the fluctuation of the bit line potential can be shortened, and the read time tacc is shorter than that in the conventional technique.
The high level of the sense amplifier output O is determined by '(tacc'<tacc). That is, high-speed reading is possible.

FIG. 5 shows another embodiment. In the above embodiment, the capacitive load connected to the dummy bit line of the dummy memory cell circuit 21 is set to a plurality of dummy EPROM transistors corresponding to each row. Although it is realized by Q41 to Q4m, in this embodiment, it is realized by one dummy EPROM transistor Q41 whose gate is connected to the power supply voltage Vcc and one capacitance element Cx.

Here, the value of the capacitive element Cx is Cx = Cbb * (m-1) ... (5). The capacitive element Cx may be configured by a capacitive element that can be realized in a semiconductor such as a MOS capacitor.

Further, in the above embodiments, the memory cell array has been described as being constructed by using the EPROM transistor, but this is, for example, the mask ROM, the EE.
Any memory element, such as a PROM, that stores data depending on whether the memory element is conductive or non-conductive can be appropriately applied.

[0033]

As described above, according to the semiconductor memory device of the present invention, when the differential sense amplifier output is judged by comparing the read output from the memory cell array with the reference voltage, the reference voltage is applied to the memory cell. It is varied in a state of following the variation of the output from the array, and the comparison / determination output can be obtained before the memory cell output reaches the reference voltage Vref to enable high-speed reading. .

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram for explaining a semiconductor memory device according to an embodiment of the present invention.

FIG. 2A is a diagram illustrating a configuration of a dummy column decoder used in the above embodiment, and FIG. 2B is a signal waveform diagram illustrating an operation of the decoder.

FIG. 3 is a circuit configuration diagram for explaining the operation of the above embodiment.

4A and 4B are voltage waveform and output waveform diagrams for explaining the operation of the above embodiment.

FIG. 5 is a circuit configuration diagram illustrating another embodiment of the present invention.

FIG. 6 is a circuit configuration diagram showing a conventional semiconductor memory device.

7A and 7B are voltage waveform and output waveform charts for explaining the operation of the above-mentioned conventional technique.

[Explanation of symbols]

11 ... Memory cell array, 12 ... Address counter, 13 ... Column decoder, 14 ... Row decoder, 15 ... Differential amplifier (sense amplifier circuit), 16 ... Inverter circuit, 21 ... Dummy memory cell circuit, 22 ... Dummy column decoder, 23 ... Reference voltage generating circuit, Q411 to Q4mn ... EPROM transistor,
Q41-Q4m ... Dummy EPROM transistors, Q31-Q
3n ... Column select transistor, Q3 ... Dummy column select transistor, Q11, Q12 ... First and second load transistors.

Claims (3)

[Claims] 1. A memory cell in which a plurality of memory cells are arranged along rows and columns, and one memory cell is selected based on a column selection signal and a row selection signal obtained in response to an address command. An array, and at least one dummy cell having the same configuration as the memory cell,
A dummy cell means for setting a capacitive load equal to a capacitive load connected to one bit line; a first load transistor to which the output of the memory cell array is coupled; and a second load transistor to which the output from the dummy cell means is coupled. And a dummy column select transistor which is set to connect the memory cell means and the second load transistor, and which is set in a conductive state by a signal corresponding to a column select signal of the memory cell array, A semiconductor memory device comprising: a differential-type sense amplifier output determining means to which a memory cell output and a dummy cell output obtained respectively corresponding to the first and second load transistors are supplied. 2. The dummy cell means is composed of the same number of dummy cells as one column of the memory cell array, one of the dummy cells is selected by a column selection signal supplied to the memory cell array, and the other dummy cells are selected. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is used as a capacitive load. 3. The semiconductor memory device according to claim 1, wherein said dummy cell means is composed of one dummy cell and a capacitive element set to a capacitance value equal to a bit line capacitance.