JP2011090744A - Output circuit, semiconductor memory device and data reading method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a sense amplifier circuit for a memory cell array arranged in a matrix, capable of accurately reading a data value stored in each memory cell even when noise is applied, and to provide a semiconductor memory device including the sense amplifier. <P>SOLUTION: The semiconductor memory device S includes: a memory cell array 100 composed of memory cells MC each disposed by being connected to one bit line B and one bit word line W at an intersection point between the plurality of bit lines B and the plurality of word lines W; and a plurality of dummy cells DC each having the same structure as that of the memory cell MC, wherein each of the dummy cells DC includes a single dummy cell array 110 which is arranged in the same layout as that of each memory cell MC of the memory cell array 100. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

The present invention relates to a sense amplifier circuit used in a semiconductor memory device, and more particularly to a sense amplifier circuit having high noise resistance.

  In recent years, many products equipped with semiconductor storage devices such as personal computers or mobile phones have been put into practical use. A semiconductor memory device mounted on such an electronic device has a memory cell array composed of a plurality of memory cells, and a cell current is output according to the data value of each memory cell. Data output. In particular, since such a semiconductor memory device has a very small amount of cell current or potential that changes based on the cell current, the cell current or potential that changes based on the cell current is amplified to a level that can be handled as a digital level. A sense amplifier circuit is provided.

  Specifically, the sense amplifier circuit includes a circuit (hereinafter referred to as “dummy cell circuit”) configured by the same cell (that is, a dummy cell) as a memory cell configuring the memory cell array, and outputs from the dummy cell circuit. The reference current that is generated or the reference voltage that changes based on the reference current is compared with the cell current that is output from the memory cell array based on the reading of data from the memory cell or the cell potential that changes based on the cell current. . The sense amplifier circuit outputs a signal indicating a data value stored in the memory cell at a predetermined level based on the comparison result. That is, the sense amplifier circuit outputs “1” when the reference current or reference voltage matches the cell current or cell potential, and outputs “0” otherwise.

  In such a sense amplifier circuit, since the data value of each memory cell is detected based on a minute change in cell current, various noises are applied to the cell current, such as when noise is generated inside. It is difficult to accurately detect the cell current and determine the data value based on it, so it is necessary to eliminate the influence of noise.

  For example, a sense amplifier that accurately detects a cell current is known in which a capacitor (parasitic capacitor) is provided in the dummy cell circuit so that the capacitance in the memory cell array is equal to the capacitance in the dummy cell circuit. (For example, patent document 1). Specifically, the sense amplifier circuit disclosed in Patent Document 1 includes capacitances in corresponding paths in the memory cell array and the dummy cell circuit, that is, a path through which a MOS transistor and a cell current flow and a path through which a reference current flows. Are provided in a predetermined element of the dummy cell circuit. As other sense amplifiers, in order to make the load of the bit line through which the cell current flows in the memory cell array and the dummy bit line through which the reference current flows in the dummy cell circuit the same, There is also known one in which the size of each element of the memory cell is the same (for example, Patent Document 2).

Japanese Patent Publication No.7-15952 Japanese Patent Laid-Open No. 9-139066

  However, in the sense amplifier circuit described in Patent Document 1, a memory cell array having a plurality of memory cells arranged in a matrix is not assumed, and a memory cell array having memory cells in a matrix is not assumed. Thus, it is impossible to avoid erroneous determination in the sense amplifier when reading the data value stored in the memory cell.

  Further, this sense amplifier circuit has a dummy cell circuit having a single dummy cell, the layout of the memory cell array having a plurality of memory cells is not identical, and the dummy cells are linked to the memory cells. Therefore, the parasitic capacitances in the dummy cell circuit and the memory cell cannot be made completely the same, and the erroneous determination in the sense amplifier when reading the data value stored in the memory cell is avoided. I can't let you.

  Further, in the sense amplifier circuit described in Patent Document 2, the connection of some of the transistors in the memory cell and the dummy cell circuit is different. Specifically, some of the transistors (see FIG. Since the connection of the source and the drain of the transistor Tr2) shown in FIG. Therefore, in this sense amplifier circuit, the memory cell array and the dummy cell circuit have the same circuit configuration, so that even if noise is applied, the data value stored in each memory cell can be read accurately. There is no mention of that.

  Further, in the sense amplifier circuit described in Patent Document 2, as in Patent Document 1, a memory cell array having a plurality of memory cells arranged in a matrix is not assumed. For a memory cell array having cells, it is impossible to avoid erroneous determination in the sense amplifier when reading the data value stored in the memory cell.

  The present invention has been made to solve the above-described problems, and its object is to form a matrix that can accurately read and output data values stored in each memory cell even when noise is applied. It is an object of the present invention to provide a sense amplifier circuit for a memory cell array and a semiconductor memory device having the same.

  (1) In order to solve the above-described problem, the present invention provides a plurality of bit lines, a plurality of word lines, and a plurality of bit lines and a plurality of word lines arranged in a matrix at each intersection of the plurality of bit lines and the plurality of word lines. And a plurality of dummy cells having the same characteristics as each of the memory cells connected to one bit line and one word line. A dummy cell array having the same layout for a column of memory cells formed on the basis of at least one bit line of the memory cell array, and one memory cell based on a predetermined instruction. First detection means for detecting a bit line current flowing through the bit line when selected, and in conjunction with the selection of the one memory cell. Second detection means for detecting a reference current output from the dummy cell array by selecting one dummy cell corresponding to the selected memory cell; the detected bit line current; and the detected reference current; And determining means for determining the data value stored in the selected memory cell, and output means for outputting the data value determined by the determining means to the outside. .

  With this configuration, the present invention has a dummy cell array having the same layout with respect to a column of memory cells formed based on at least one bit line of the memory cell array. When a memory cell is selected, one dummy cell corresponding to the selected memory cell is selected, and a reference current based on the selected dummy cell can be detected.

  Therefore, according to the present invention, the parasitic capacitance formed on the bit line connected to the selected memory cell (that is, the path through which the bit line current flows) and the path of the dummy cell array through which the reference current flows (that is, the reference current is The parasitic capacitance formed on the flow path) can be easily equalized without complicating the circuit configuration, so that even if noise is applied, the noise-based changes in the bit line current and reference current are equal. Therefore, the data value stored in each memory cell can be accurately read and output.

  (2) Further, in the present invention, the dummy cell array has the same matrix as the matrix structure of the memory cell array formed by the rows formed based on the word lines and the columns formed based on the bit lines. When the one memory cell is selected, one dummy cell belonging to the same arrangement position as the selected memory cell is selected.

  With this configuration, when one memory cell is selected based on a predetermined instruction, the present invention can select dummy cells belonging to the same array position in a dummy cell array having the same matrix structure. The parasitic capacitance formed on the bit line to which the selected memory cell is connected (that is, on the path through which the bit line current flows) and the path in the column to which the selected dummy cell belongs (that is, on the path through which the reference current flows) Can be made equal to the parasitic capacitance formed.

  Therefore, according to the present invention, even if noise is applied, the change based on the noise in the bit line current and the reference current becomes equal, so that the data value stored in each memory cell can be accurately read and output.

  (3) Further, in the present invention, the dummy cell array is formed of a single column having the same column structure as the column of each bit line of the memory cell array formed based on the bit line. When a memory cell is selected, one dummy cell belonging to the same row as the selected memory cell is selected.

  With this configuration, when one memory cell is selected based on a predetermined instruction, the present invention can select a dummy cell belonging to the same row in a dummy cell array having the same column structure. While simplifying the structure, the parasitic capacitance formed on the bit line (that is, on the path through which the bit line current flows) and the path in the column of the dummy cell array to which the selected dummy cell belongs (that is, on the path through which the reference current flows) Can be made equal to the parasitic capacitance formed.

  (4) The present invention further includes a plurality of first changeover switches for selecting a bit line to which the memory cell belongs from a plurality of bit lines of the memory cell array when one memory cell is selected. Memory cell column selection means, the dummy cell column selection means having the same characteristics as the first changeover switch and having the same number of second changeover switches as the first changeover switch, And a dummy cell column selection unit connected to the dummy cell array, wherein the dummy cell column selection unit selects the one memory cell when the one memory cell is selected. A second changeover switch corresponding to a first changeover switch for selecting a column of one bit line to which the cell belongs is driven; It has a configuration in which the dummy cell array having a single row are connected.

  With this configuration, the present invention enables the memory cell column selection means and the dummy cell column selection means to be connected to a column on the same dummy cell array regardless of which memory cell connected to any bit line is connected. Therefore, the parasitic capacitance formed on the path through which the bit line current flows can be made equal to the parasitic capacitance formed on the path through which the reference current flows, while simplifying the structure of the dummy cell array. it can.

  (5) Moreover, this invention has the structure by which the same value as another dummy cell is memorize | stored in each dummy cell of the said dummy cell array.

  By having this configuration, the present invention always detects the reference current based on the same value regardless of which dummy cell is selected, so that the cell current can always be accurately compared with the reference current as a reference. The data value stored in each memory cell can be determined and output.

  (6) In order to solve the above-described problem, the present invention provides a plurality of bit lines, a plurality of word lines, and a plurality of bit lines and a plurality of word lines arranged in a matrix at each intersection point A memory cell array, and a plurality of dummy cells having the same characteristics as each of the memory cells connected to one bit line and one word line, the memory cell array A dummy cell array having the same layout for a column of memory cells formed on the basis of at least one bit line, and a bit line current flowing through the bit line by selecting one memory cell based on a predetermined instruction First dummy detecting means and a dummy cell corresponding to the selected memory cell are selected in conjunction with the selection of the one memory cell. Is stored in the selected memory cell on the basis of the second detection means for detecting the reference current output from the dummy cell array, the detected bit line current and the detected reference current. A determination means for determining the data value being output, and an output means for outputting the data value determined by the determination means to the outside.

  With this configuration, the present invention has a dummy cell array having the same layout with respect to a column of memory cells formed based on at least one bit line of the memory cell array. When a memory cell is selected, one dummy cell corresponding to the selected memory cell is selected, and a reference current based on the selected dummy cell can be detected.

  Therefore, according to the present invention, the parasitic capacitance formed on the bit line connected to the selected memory cell (that is, the path through which the bit line current flows) and the path of the dummy cell array through which the reference current flows (that is, the reference current is Since the parasitic capacitance formed on the flowing path can be easily equalized without complicating the circuit configuration, the present invention is based on the noise in the bit line current and the reference current even when noise is applied. Since the changes are equal, the data value stored in each memory cell can be accurately read and output.

  (7) The present invention includes a plurality of the memory cell arrays, the same structure as each memory cell array, and a single dummy cell array.

  With this configuration, the present invention can output reference currents in a plurality of memory cell arrays based on a single dummy cell array, so that the dummy cell array is simplified and formed on a path through which a bit line current flows. The parasitic capacitance formed on the path through which the reference current of the dummy cell array flows can be made equal.

  (8) In order to solve the above problem, the present invention provides a plurality of bit lines, a plurality of word lines, and a plurality of bit lines and a plurality of word lines arranged in a matrix at each intersection of the plurality of bit lines and the plurality of word lines. A memory cell array, and a plurality of dummy cells having the same characteristics as each of the memory cells connected to one bit line and one word line, the memory cell array A data reading method for reading a data value stored in the memory cell in a semiconductor memory device having a dummy cell array having the same layout for a column of memory cells formed based on at least one bit line A first selection step in which one memory cell is selected based on a predetermined instruction, and in conjunction with the selection of the one memory cell. A second selection step in which one dummy cell corresponding to the selected memory cell is selected; a bit line current flowing through the bit line output from the memory cell array when the one memory cell is selected; A determination step of determining a data value stored in the selected memory cell based on a reference current output from the dummy cell array when the one dummy cell is selected; And an output process for outputting the data value to the outside.

  With this configuration, the present invention has a dummy cell array having the same layout with respect to a column of memory cells formed based on at least one bit line of the memory cell array. When a memory cell is selected, one dummy cell corresponding to the selected memory cell is selected, and a reference current based on the selected dummy cell can be detected.

  Therefore, according to the present invention, the parasitic capacitance formed on the bit line connected to the selected memory cell (that is, the path through which the bit line current flows) and the path of the dummy cell array through which the reference current flows (that is, the reference current is The parasitic capacitance formed on the flow path can be easily equalized without complicating the circuit configuration. Even if noise is applied, the change in the bit line current and the reference current based on the noise becomes equal, so that the data value stored in each memory cell can be accurately read and output.

  The present invention provides a parasitic capacitance formed on a bit line connected to a selected memory cell (that is, a path through which a bit line current flows) and a dummy cell array path through which a reference current flows (that is, a path through which the reference current flows). Since the parasitic capacitance formed in (above) can be easily made equal without complicating the circuit configuration, even if noise is applied, the change based on the noise in the bit line current and the reference current becomes equal. The data value stored in each memory cell can be accurately read and output.

1 is a configuration diagram showing a configuration of a semiconductor memory device in a first embodiment of a semiconductor memory device according to the present invention. It is a figure for demonstrating operation | movement of the column address decoder and row address decoder in 1st Embodiment. It is a figure for demonstrating the relationship between the memory cell array of the semiconductor memory device in 1st Embodiment, and a dummy cell array, and is a figure which shows the structural example of a memory cell array and a dummy cell array. FIG. 2 is a circuit diagram illustrating a bias potential generation circuit and a sense amplifier circuit according to the first embodiment. It is a figure for demonstrating the relationship between the memory cell array and dummy cell array of the semiconductor memory device in 2nd Embodiment, and is a figure which shows the structural example of a memory cell array and a dummy cell array.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the embodiment described below, a semiconductor memory having a memory cell array composed of a plurality of memory cells each storing predetermined data values (for example, “0” and “1”) such as ROM: Read Only Memory. In this embodiment, the output circuit and the semiconductor memory device of the present invention are applied to the device.

<First Embodiment>
First, a first embodiment of a semiconductor memory device S according to the present invention will be described with reference to FIGS.

  First, the configuration of the semiconductor memory device S of this embodiment will be described. FIG. 1 is a configuration diagram showing the configuration of the semiconductor memory device S in the present embodiment.

  As shown in FIG. 1, the semiconductor memory device S of the present embodiment is provided at each intersection of a plurality of bit lines B and a plurality of word lines W while being connected to one bit line B and one word line W. A memory cell array 100 composed of each memory cell MC, and stored in the memory cell MC from a memory cell MC selected based on address data having a memory address of a plurality of bits input as a predetermined instruction The read data value is read out and output as data to the outside.

  In particular, the semiconductor memory device S of the present embodiment includes a plurality of dummy cells DC having the same structure as each memory cell MC in order to accurately output data read from the memory cell MC, and each dummy cell DC is a memory. It has a single dummy cell array 110 arranged in the same layout as each memory cell MC of the cell array 100.

In addition, the semiconductor memory device S uses n bits to identify one memory cell MC in the memory cell array 100 from address data composed of n + m bits by using an upper n bit column address and a lower m bit row address. A column address decoder 120 having a ^2n- bit address output for an address input composed of a row address, and a row address decoder 130 having a 2m-bit address output for a ^m- bit address input. is doing,

  Further, the semiconductor memory device S includes a bias potential generation circuit 140 that generates a reference voltage for determining the data value of the selected memory cell MC based on the reference current output from the dummy cell array 110, and a reference voltage. A plurality of sense amplifiers 150 for determining the data value of the selected memory cell MC based on the cell current output from the memory cell array 100 to the selected memory cell MC and outputting the determination result to the outside as data ,have.

  For example, the dummy cell array 110, the bias potential generation circuit 140, and the sense amplifier 150 according to the present embodiment constitute an output circuit according to the present invention. In particular, the bias potential generation circuit 140 constitutes a second detection unit according to the present invention. To do. Further, for example, the sense amplifier 150 of this embodiment constitutes a first detection unit and a determination unit of the present invention.

  Next, details of each part in the semiconductor memory device S of the present embodiment will be described with reference to FIGS. 2 is a diagram for explaining the operations of the column address decoder 120 and the row address decoder 130 in the present embodiment, and FIG. 3 is a diagram illustrating the memory cell array 100 and the dummy cell array 110 of the semiconductor memory device S in the present embodiment. It is a figure for demonstrating the relationship of these. FIG. 4 is a circuit diagram showing circuits of the bias potential generation circuit 140 and the sense amplifier 150 of the present embodiment.

The column address decoder 120 includes n logical negation circuits and 2 ⁿ logical product circuits. The column address decoder 120 receives column address data composed of upper n bits of address data, and receives the received column address data. Based on this, one column address output is output as a data value of “1”. For example, as shown in FIG. 2A, when receiving a column address composed of two bits A0 and A1, the column address decoder 120 includes two logical negation circuits and four logical products. The data value of any column address output of C0 to C3 is set to “1” based on the data values of “0” and “1” input to A0 and A1, and output to the memory cell array 100. It is supposed to be.

The row address decoder 130 has m logical negation circuits and 2 ^m logical product circuits, receives row address data composed of lower m bits of the address data, and receives the received row address data. Based on this, one row address output is output as a data value of “1”. For example, as shown in FIG. 2B, when receiving a row address composed of two bits of 0 and B1, the column address decoder 120 includes two logical NOT circuits and four logical products. The data value of the row address output of any of R0 to R3 is set to “1” based on the data values of “0” and “1” input to A3 and A4 and output to the memory cell array 100. It is supposed to do.

  The memory cell array 100 has a plurality of memory cells MC in a matrix so that one bit line B is selected based on the column address output and one word line W is selected based on the row address output. is doing. That is, in this memory cell array 100, a memory cell MC group belonging to one column in each memory cell MC in a matrix is selected based on the column address output, and the memory cell MC belonging to the selected one column. One memory cell MC is selected from the group based on the row address output. When one memory cell MC is selected, the memory cell array 100 senses a cell current (hereinafter also referred to as “bit line current”) based on the data value of the selected memory cell MC. 150 is output.

  For example, as shown in FIG. 3, the memory cell array 100 of the present embodiment includes a plurality of switching transistors ST provided on each bit line B that is driven based on the output of each column address for each column address output. The memory cell MC is provided at each intersection of the bit line B and the word line W, and is connected to any one bit line B and any one word line W. For example, the switching transistor ST in the memory cell array 100 of this embodiment constitutes a memory cell column selection unit of the present invention.

  Each switching transistor ST is an N-type MOS transistor and is provided at the head of each dummy bit line DB, that is, between the memory cell MC in the first row and the sense amplifier 150 in each dummy bit line DB. It has become. Each switching transistor ST has a gate terminal connected to each column address output, a drain terminal connected to the sense amplifier 150, and a source terminal connected to each memory cell MC in the first row. Have.

  Each memory cell MC has a MOS transistor 10 having a floating gate structure. This MOS transistor 10 has a control gate terminal connected to each row address output via a word line W, and a bit line B. A drain terminal to be connected and a source terminal to be grounded are provided. Each MOS transistor 10 stores a predetermined data value, for example, “0” or “1”.

  3 is a diagram showing the memory cell array 100 corresponding to one sense amplifier 150. In the present embodiment, since there are a plurality of sense amplifiers 150, the sense amplifier 150 shown in FIG. A plurality of dummy cell arrays 110 corresponding to the sense amplifiers 150 are formed.

  The dummy cell array 110 has the same structure as the memory cell array 100, and includes a plurality of memory cells (that is, dummy cells (dummy memory cells)) DC in a matrix.

  In this dummy cell array 110, the same as the bit line B of the memory cell array 100 based on the column address output so as to be linked to the memory cell array 100 (specifically, the memory cell MC selected based on the address data). A bit line (hereinafter referred to as “dummy bit line”) DB formed in a column is selected. In the dummy cell array 110, each word line W connected to each memory cell MC of the memory cell array 100 is connected to each dummy cell DC. That is, the dummy cell array 110 is the same as the bit line B of the memory cell array 100 based on the column address output so that the dummy cells DC arranged at the same position as the memory cell array 100 are selected based on the address data. The dummy bit line DB formed in the column is selected, and the same word line W as the memory cell array 100 is selected based on the row address output. The dummy cell array 110 outputs a reference current (hereinafter also referred to as “dummy bit line current”) to the sense amplifier 150 based on a predetermined data value of the selected dummy cell DC. Yes.

  For example, as shown in FIG. 3, the dummy cell array 110 includes switching transistors provided on dummy bit lines DB that are driven on the basis of the output of each column address for each column address output in conjunction with the memory cell array 100. ST has a plurality of dummy cells DC provided at each intersection of the dummy bit line DB and the word line W and connected to any one bit line B and any one word line W. For example, the switching transistor ST in the dummy cell array 110 of this embodiment constitutes a dummy cell column selection unit of the present invention.

  Each switching transistor ST is an N-type MOS transistor, and is provided at the head of each dummy bit line DB, that is, between the dummy cell DC in the first row in each dummy bit line DB and the bias potential generation circuit 140. It has become. Each switching transistor ST has a gate terminal connected to each column address output, a drain terminal connected to the sense amplifier 150, and a source terminal connected to each dummy cell DC in the first row. is doing.

  Each dummy cell DC has a MOS transistor 20 having a floating gate structure. This MOS transistor 20 is connected to each row address output via a word line W and to each bit line B. And a source terminal connected to the ground. Each MOS transistor 20 has a state in which data is written in advance, that is, a data value “1”.

  The bias potential generation circuit 140 detects the dummy cell current output from the dummy cell array 110, that is, the reference current, and the sensed reference current of the memory cell MC selected by the sense amplifier 150 based on the cell current. The voltage is converted into a voltage (that is, a reference voltage) that serves as a reference for determining the data value, and the converted voltage is output to the sense amplifier 150.

  Specifically, as shown in FIG. 4, the bias potential generation circuit 140 includes three P-type MOS transistors (hereinafter referred to as “PMOS transistors”) 141, 142, and 143, and three N-type transistors. MOS transistors (hereinafter referred to as “NMOS transistors”) 144, 145, and 146.

  The first PMOS transistor 141 is connected to the gate and drain of the second PMOS transistor 142 and the gate connected to the dummy cell array 110 via the first NMOS transistor 144, the source connected to the power supply voltage VDD, and the sense amplifier 150. The third NMOS transistor 146 includes a drain connected to the gate and the drain.

  The second PMOS transistor 142 is connected to the gate of the first PMOS transistor 141 and is short-circuited to the drain, and is connected to the dummy cell array 110 via the first NMOS transistor 144; a source connected to the power supply voltage VDD; The drain is connected to the dummy cell array 110 via the gate of the first PMOS transistor 141 and the first NMOS transistor 144 while being short-circuited with the gate.

  The third PMOS transistor 143 includes a gate grounded, a source connected to the power supply voltage VDD, and a drain connected to the gate of the first NMOS transistor 144 and the drain of the second NMOS transistor 145.

  The first NMOS transistor 144 is connected to the gate connected to the drain of the third PMOS transistor 143 and the drain of the second NMOS transistor 145, the gate of each of the first PMOS transistor 141 and the second PMOS transistor 142, and the drain of the second PMOS transistor 142. A drain connected to the dummy cell array 110 and a source connected to the second NMOS transistor 145 and the gate.

  The second NMOS transistor 145 is connected to the dummy cell array 110 and connected to the source of the first NMOS transistor 144, the drain connected to the gate of the first NMOS transistor 144 and the drain of the third PMOS transistor 143, and grounded. Source.

  The third NMOS transistor 146 includes a gate connected to the sense amplifier 150 and short-circuited to the drain, a drain connected to the sense amplifier 150 and short-circuited to the gate, and a source grounded.

  The sense amplifier 150 detects a cell current output from the memory cell array 100, and a difference between a voltage that changes based on the detected cell current (that is, a cell voltage) and a reference voltage output from the bias potential generation circuit 140. A voltage value indicating the difference is output to the outside as a data value. That is, since the reference voltage is a voltage indicating the data value “1”, if the data value of the memory cell MC selected by the address data is “1” or “0”, the differentially amplified voltage is predetermined. Therefore, the sense amplifier 150 determines the data value of the memory cell MC selected by the address data by performing differential amplification based on the cell voltage and the reference voltage. In other words, a voltage value that matches the data value and whose level is amplified can be output.

  Specifically, the sense amplifier 150 includes three PMOS transistors 151, 152 and 153 and four NMOS transistors 154, 155, 156 and 157 as shown in FIG.

  The fourth PMOS transistor 151 includes a gate connected to the memory cell array 100 via the gate and drain of the fifth PMOS transistor 152 and the fifth NMOS transistor 155, a source connected to the power supply voltage VDD, an output terminal T, and the fourth NMOS transistor 154. And a drain connected to the drain of each other.

  The fifth PMOS transistor 152 is connected to the gate of the fourth PMOS transistor 151 and shorted with the drain, a source connected to the power supply voltage VDD, and a drain connected to the memory cell array 100 via the fifth NMOS transistor 155. And.

  The sixth PMOS transistor 153 includes a gate grounded, a source connected to the power supply voltage VDD, and a drain connected to the gate of the fifth NMOS transistor 155 and the drain of the sixth NMOS transistor 156.

  The fourth NMOS transistor 154 includes a gate to which the voltage (reference voltage) output from the bias potential generation circuit 140 is applied, a drain connected to the output terminal T and the drain of the fourth PMOS transistor 151, and a seventh NMOS. And a source connected to the drain of the transistor 157.

  The fifth NMOS transistor 155 is connected to the gate connected to the drain of the sixth PMOS transistor 153 and the gate of the sixth NMOS transistor 156, the gates of the fourth PMOS transistor 151 and the fifth PMOS transistor 152, and the drain of the fifth PMOS transistor 152. A drain connected to the memory cell array 100 and a source connected to the gate of the sixth NMOS transistor 156.

  The sixth NMOS transistor 156 is connected to the memory cell array 100 and connected to the source of the fifth NMOS transistor 155, the drain connected to the gate of the fifth NMOS transistor 155 and the drain of the sixth PMOS transistor 153, and grounded. Source.

  The seventh NMOS transistor 157 includes a gate connected to the power supply voltage VDD, a drain connected to the source of the fourth NMOS transistor 154, and a source grounded.

  Next, the read operation of the data value stored in the memory cell MC in the semiconductor memory device S of this embodiment will be described.

  First, when the column address decoder 120 and the row address decoder 130 receive address data instructed by a control unit (not shown), one memory cell MC is selected based on the address data, and one memory cell MC In conjunction with the selection, one dummy cell DC corresponding to the selected memory cell MC is selected.

  Next, a cell current is generated on one bit line B in the matrix to which the selected memory cell MC belongs based on the data value of the selected memory cell MC and is input to the sense amplifier 150, and the selected dummy cell A reference current is generated in a predetermined dummy bit line DB based on DC and is input to the bias potential generation circuit 140.

  Finally, when the bias potential generation circuit 140 detects the reference current, it converts the reference current into a reference voltage and outputs the reference voltage to the sense amplifier 150. When the sense amplifier 150 detects the input cell current, The cell voltage is changed based on the current, and the difference between the converted cell voltage and the reference voltage output from the bias potential generation circuit 140 is amplified, and the voltage indicating the difference, that is, the level is selected. The voltage value indicating the data value of the memory cell MC is output to the outside.

  As described above, in the semiconductor memory device S of this embodiment, when one memory cell MC is selected based on the address data, the selected memory cell in the dummy cell array 110 having the same matrix structure as the memory cell array 100 is selected. Since a dummy cell DC belonging to the same arrangement position as the cell MC can be selected, a parasitic capacitor formed on the bit line B connected to the selected memory cell MC and a path on the dummy cell array 110 through which a reference current flows. That is, the parasitic capacitance formed on the dummy bit line DB can be made equal. Therefore, the semiconductor memory device S does not have a complicated circuit configuration, and even if noise is applied, the change based on the noise in the bit line B current and the reference current becomes equal and is stored in each memory cell MC. Data values can be read and output accurately.

  In the semiconductor memory device S of this embodiment, since the same value as that of the other dummy cells DC is stored in each dummy cell DC of the dummy cell array 110, it is always the same no matter which dummy cell DC is selected. A reference current based on the value can be detected. Therefore, since the semiconductor memory device S can always compare the cell current with the reference current as a reference, it can accurately determine and output the data value stored in each memory cell MC.

Second Embodiment
Next, a second embodiment of the semiconductor memory device S according to the present invention will be described with reference to FIG.

  In the semiconductor memory device S of this embodiment, the same column structure as that of each bit line B of the memory cell array 100 is used instead of the dummy cell array 110 having the same matrix cell structure as the memory cell array 100 in the first embodiment. The other features are the same as those of the first embodiment, and the same members are denoted by the same reference numerals. Therefore, the description is omitted.

  FIG. 5 is a diagram for explaining the relationship between the memory cell array 100 and the dummy cell array 110 of the semiconductor memory device S in the second embodiment, and is a diagram illustrating a configuration example of the memory cell array 100 and the dummy cell array 110. However, FIG. 5 is a diagram showing the memory cell array 100 corresponding to one sense amplifier 150. Since this embodiment has a plurality of sense amplifiers 150, the sense amplifier 150 shown in FIG. Are provided, and a dummy cell array 110 corresponding to the sense amplifiers 150 is formed.

  As described above, the dummy cell array 110 according to the present embodiment has the same column structure as each column of the memory cell array 100 and includes the same number of dummy cells (dummy memory cells) DC as the columns of the memory cell array 100.

  In this dummy cell array 110, a single dummy bit line DB is selected based on the column address output. In the dummy cell array 110, as in the first embodiment, each word line W connected to each memory cell MC of the memory cell array 100 is connected to each dummy cell DC. That is, the dummy cell array 110 switches the dummy bit line DB for column address output so that the dummy cells DC arranged in the same row in each column of the memory cell array 100 are selected based on the address data. However, the single dummy bit line DB is always selected, and the same word line W as the memory cell array 100 is selected based on the row address output. The dummy cell array 110 outputs a reference current to the sense amplifier 150 based on a predetermined data value of the selected dummy cell DC.

  For example, the dummy cell array 110 is a switching transistor ST that is driven on the basis of the output of each column address for each column address output in conjunction with the memory cell array 100, as shown in FIG. The switching transistor ST connected to the bit line DB is provided at each intersection of the single dummy bit line DB and the word line W, and is connected to the single dummy bit line DB and any one word line W. And a plurality of dummy cells DC.

  Each switching transistor ST is an N-type MOS transistor, and is provided at the head of each dummy bit line DB, that is, between the dummy cell DC of the first row in the single dummy bit line DB and the bias potential generation circuit 140. A gate terminal connected to each column address output, a drain terminal connected to the sense amplifier 150, and a dummy cell DC provided on a single dummy bit line DB in the first row. And a source terminal to be connected.

  Each dummy cell DC has a MOS transistor 20 having a floating gate structure. This MOS transistor 20 has a control gate terminal connected to each row address output via each word line W, and a single dummy bit. A drain terminal connected to the line DB and a source terminal connected to the grant are included. Each MOS transistor 20 has a state in which data is written in advance, that is, a data value “1”, as in the first embodiment.

  As described above, the semiconductor memory device S according to the present embodiment has the same column structure as each column of the memory cell array 100 when a single memory cell MC is selected based on the address data. Since dummy cells DC belonging to the same row in the configured dummy cell array 110 can be selected, the dummy cell array 110 is formed on the bit line B connected to the selected memory cell MC while simplifying the structure. The parasitic capacitance and the path on the dummy cell array 110 through which the reference current flows, that is, the parasitic capacitance in the dummy bit line DB can be made equal. Therefore, the semiconductor memory device S does not have a complicated circuit configuration, and even if noise is applied, the change based on the noise in the bit line B current and the reference current becomes equal and is stored in each memory cell MC. Data values can be read and output accurately.

  In the semiconductor memory device S of this embodiment, since each dummy cell DC of the dummy cell array 110 stores the same value as the other dummy cells DC, as in the first embodiment, any dummy cell DC is stored. Even if is selected, a reference current based on the same value can always be detected. Therefore, the semiconductor memory device S can always accurately compare the cell current with the reference current as a reference, and can determine and output the data value stored in each memory cell MC.

B ... Bit line S ... Semiconductor memory device T ... Output terminal W ... Word line DB ... Dummy bit line DC ... Dummy cell MC ... Memory cell ST ... Switching transistor 10, 20 ... MOS transistor (floating gate)
DESCRIPTION OF SYMBOLS 100 ... Memory cell array 110 ... Dummy cell array 120 ... Column address decoder 130 ... Row address decoder 140 ... Bias potential generation circuit 141 ... 1st PMOS transistor 142 ... 2nd PMOS transistor 143 ... 3rd PMOS transistor 144 ... 4th PMOS transistor 145 ... 5th PMOS transistor 146 ... sixth PMOS transistor 150 ... sense amplifier 151 ... first NMOS transistor 152 ... second NMOS transistor 153 ... third NMOS transistor 154 ... fourth NMOS transistor 155 ... fifth NMOS transistor 156 ... sixth NMOS transistor 157 ... seventh NMOS transistor

Claims (8)

Data is read from a memory cell array having a plurality of bit lines, a plurality of word lines, and a plurality of memory cells arranged in a matrix at each intersection of the plurality of bit lines and the plurality of word lines. An output circuit that outputs to the outside,
A dummy cell array composed of a plurality of dummy cells having the same characteristics as each of the memory cells connected to one bit line and one word line, and is formed based on at least one bit line of the memory cell array. A dummy cell array having the same layout for the memory cell columns;
First detection means for detecting a bit line current flowing through the bit line when one memory cell is selected based on a predetermined instruction;
Second detection means for detecting a reference current output from the dummy cell array by selecting one dummy cell corresponding to the selected memory cell in conjunction with the selection of the one memory cell;
Determining means for determining a data value stored in the selected memory cell based on the detected bit line current and the detected reference current;
Output means for outputting the data value determined by the determination means to the outside;
An output circuit comprising: The output circuit according to claim 1,
The dummy cell array has the same matrix structure as the matrix structure of the memory cell array formed by rows formed based on the word lines and columns formed based on the bit lines;
An output circuit, wherein when one memory cell is selected, one dummy cell belonging to the same arrangement position as the selected memory cell is selected. The output circuit according to claim 1,
The dummy cell array is formed from a single column having the same column structure as each bit line column of the memory cell array formed based on the bit lines,
An output circuit, wherein when one memory cell is selected, one dummy cell belonging to the same row as the selected memory cell is selected. The output circuit according to claim 3.
A memory cell column selecting unit having a plurality of first changeover switches for selecting a bit line to which the memory cell belongs from among a plurality of bit lines of the memory cell array when one memory cell is selected;
Dummy cell column selection means having the same characteristics as the first changeover switch and having the same number of second changeover switches as the first changeover switch, and having the same structure as the memory cell column selection means. Column selection means for dummy cells connected to the dummy cell array;
Further comprising
The dummy cell column selecting means drives a second changeover switch corresponding to a first changeover switch for selecting a column of one bit line to which the one memory cell belongs when the one memory cell is selected. And
The output circuit, wherein each of the second changeover switches is connected to the dummy cell array having the single column. The output circuit according to any one of claims 1 to 4,
Each dummy cell of the dummy cell array stores the same value as other dummy cells. A memory cell array having a plurality of bit lines, a plurality of word lines, and a plurality of memory cells arranged in a matrix at intersections of the plurality of bit lines and the plurality of word lines;
A dummy cell array composed of a plurality of dummy cells having the same characteristics as each of the memory cells connected to one bit line and one word line, and is formed based on at least one bit line of the memory cell array. A dummy cell array having the same layout for the memory cell columns;
First detection means for detecting a bit line current flowing through the bit line when one memory cell is selected based on a predetermined instruction;
Second detection means for detecting a reference current output from the dummy cell array by selecting one dummy cell corresponding to the selected memory cell in conjunction with the selection of the one memory cell;
Determining means for determining a data value stored in the selected memory cell based on the detected bit line current and the detected reference current;
Output means for outputting the data value determined by the determination means to the outside;
A semiconductor memory device comprising: The semiconductor memory device according to claim 6.
A semiconductor memory device comprising a plurality of the memory cell arrays, having the same structure as each memory cell array, and comprising a single dummy cell array. A memory cell array having a plurality of bit lines, a plurality of word lines, and a plurality of memory cells arranged in a matrix at intersections of the plurality of bit lines and the plurality of word lines, and one bit A dummy cell array composed of a plurality of dummy cells having the same characteristics as each of the memory cells connected to a line and one word line, the memory cell being formed based on at least one bit line of the memory cell array A data reading method for reading a data value stored in the memory cell in a semiconductor memory device having a dummy cell array having the same layout for
A first selection step in which one memory cell is selected based on a predetermined instruction;
A second selection step in which one dummy cell corresponding to the selected memory cell is selected in conjunction with the selection of the one memory cell;
A bit line current flowing through the bit line output from the memory cell array when the one memory cell is selected and a reference current output from the dummy cell array when the one dummy cell is selected. A determination step of determining a data value stored in the selected memory cell based on:
An output step of outputting the data value determined by the determination means to the outside;
A method for reading data, comprising:

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