JPH0660675A - Semiconductor storage - Google Patents

Abstract

PURPOSE:To eliminate simultaneous charging of a column line and a spare column line by a sense amplifier and to accelerate data reading at the time of selecting the spare column line by connecting only the selected spare column line to the amplifier. CONSTITUTION:When a spare storage cell column is selected in a spare storage cell array 24, a control signal SPECB becomes a logic '0' level, and a select command signal becomes a logic '1' level. A transistor(Tr) MOS 1 is turned OFF, a spare column gate 29 is turned ON, a node SA is electrically disconnected from column lines BL1-BLn, and connected to the selected spare column line RBLi. On the contrary, when a storage cell column of a storage cell array 23 is selected, a signal SPECB becomes a logic '1' level, and a select command signal becomes logical '0' level. The Tr MOS 1 is turned ON, the gate 29 is turned OFF, thereby the node SA is electrically connected to the selected line BLi, and electrically disconnected from the lines RBL1-RBLn1.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device.

[0002]

2. Description of the Related Art A conventional semiconductor memory device, for example, EPRO
The structure of M is shown in FIG. This EPROM includes a row address buffer 21, a row decoder 22, a memory cell array 23, a spare memory cell array 24, a column address buffer 25, a column decoder 26, and a spare decoder 27.
A column gate transistor circuit (hereinafter also referred to as a column gate) 28, a spare column gate transistor circuit (hereinafter also referred to as a column gate) 29, a sense amplifier 30, and an output buffer 31 are provided.

The row address buffer 21 receives the row address signals A1, ... Ak ₁ from the outside and outputs the row address signals A1, ... Ak ₁ and its inverted signal bar A.
1, ... Outputs the bar Ak ₁ . The row decoder 22 receives the memory cell array 2 based on the output of the row address buffer 21.
3 and a plurality of row lines WL1, of the spare memory cell array 24
One row line WLi (1.ltoreq.i.ltoreq.m) corresponding to the row address signals A1, ..., Ak ₁ is selected from ... WLm.

[0004] Also, the column address buffer 25 are column address signals B1 inputted from the outside, ... Bk ₂ The column address signal B1 based on, ... Bk ₂ and its inverted signal bar B
1, ... Outputs the bar Bk ₂ . The column decoder 26 uses the output of the column address buffer 25 to output the memory cell array 2
3 of a plurality of column lines BL1, ... column address signals B1, ... 1 pieces of columns corresponding to the Bk ₂ lines BLj (1 ≦ j from among BLn
A column line selection signal Xj for selecting ≦ n) is output and sent to the column gate 28.

The column gate 28 is composed of, for example, n transistors BT1, ... BTn, and each transistor BTi.
(I = 1, ..., N) are connected to the column line BLi. When the column line selection signal Xj is received, the column line selection signal Xj
The transistor BTj corresponding to j is turned on, and the column line BL
The data read in j is sent to the sense amplifier 30. Therefore, the row address signal A1 from the outside, ... Ak _1, and column address signals B1, ... when Bk ₂ is given, the memory cell at the intersection of the selected row line WLi and column line BLj is selected. The information stored in the selected memory cell is sent to the sense amplifier 30, detected and amplified, and output to the outside via the output buffer 31.

If a memory cell column in the memory cell array 23 has a defect, and the column address signal of the defective memory cell column is input, a control signal SPECB is sent from the spare column decoder 27 to the column decoder 26. At the same time, a spare column line RBLi (1 ≦
A selection command signal RX for selecting i ≦ n1) is sent. When the column decoder 26 receives the control signal SPECB,
The decoding operation is stopped.

Upon receiving the selection command signal RX, the column gate 29 selects one spare column line RBLi (1≤i≤n1) from the spare column lines RBL1, ..., RBLn1, and the selected spare column line is selected. The information of the spare memory cell read by RBLi is sent to the sense amplifier 30. Therefore, in this case, information is read from the memory cell of the spare memory cell column corresponding to the row address.

The reading of information from the memory cells of the EPROM described above will be described with reference to FIG. In FIG. 5, M
_{C 11, MC 12, ...,} MC 1n, ..., memory cells each consisting of _{MC mn} floating gate type MOSFET, D
, DCm are dummy cells made of floating gate type MOSFETs, WL1, WL2, ..., WLm are row lines, BL1, BL2, ..., BLn are column lines, and DB, respectively.
L is a dummy column line, 22 is a row decoder, 26 is a column decoder, BT1, BT2, ..., BTn are column gate MOSFETs, respectively, and DBT is equivalent to a column gate MOSFET. MOSFET, 13 is N-channel MO
SFET QM1-QM6 and P-channel MOSFET
A first load circuit composed of T QM7, 14 is an N-channel MOSFET QD1 to QD6 and a P-channel MO
A second load circuit composed of SFET QD7, 30 is a sense amplifier, and 31 is an output buffer.

Further, RMC1 to RMCm are spare memory cells, RBLm is a spare column line, and RBT is a spare column gate transistor. Here, the case where there is one spare column line is described, but when a plurality of spare column lines are provided as shown in FIG. 4, the plurality of spare column lines pass through a plurality of spare column gate transistors. Connected to the node SA. In addition, MOS with no specified channel
All FETs are N-channel.

In the EPROM having such a configuration, the memory cell selected according to the reference potential Vref generated by the second load circuit 14 and the outputs of the row decoder 22 and the column decoder 26 based on the data of the dummy cell DC. The sense amplifier 30 detects the data stored in the selected memory cell MC by comparing the potential Vin generated by the first load circuit 13 based on the data read from MC with the sense amplifier 30, 30 to output buffer 30
To read and supply data. The dummy cell DC
, A MOSFET equivalent to the memory cell MC on the main body side is used, and a dummy column line DBL equivalent to the column line BL is also used.

In each memory cell of such an EPROM, data is programmed by selectively injecting electrons into the floating gate. That is, when injecting electrons into the floating gate, a voltage sufficiently higher than the normal power supply voltage Vcc, for example, 12.5 V is applied to the column line and the row line selected by the row decoder 22 and the column decoder 26.
It is performed by applying a voltage of ˜21V. When such a high voltage is applied, impact ionization (Impact Ionization) occurs in the channel region near the drain of the memory cell located at the intersection of the selected column line and row line.
on) is generated, and electrons generated from the generated electrons and hole pairs are injected into the floating gate. The threshold voltage of the memory cell into which electrons have been injected is sufficiently higher than that of the memory cell into which electrons have not been injected. That is, a memory cell in which electrons have been injected into the floating gate maintains an off state even when a “1” level signal (power supply voltage Vcc) is supplied to the control gate, that is, a row line, and an on-state does not inject electrons. On the other hand, since electrons are not injected into the dummy cell DC, it is equivalent to a memory cell on the main body side where electrons are not injected, and as it is, there is no difference between the potentials Vref and Vin. Therefore, the load M in the second load circuit 14
The channel width WD7 of the OSFET QD7 is made larger than the channel width WM7 of the load MOSFET QM7 in the first load circuit 13 so that the MOSFET QD7
The current supply capacity of No. 7 is set larger than that of MOSFET QM7. As a result, even when a memory cell into which electrons have not been injected is selected, the potentials Vref and Vin
A predetermined potential difference is generated between and. When a memory cell into which electrons have been injected is selected, the potential Vin changes from the power supply voltage Vcc to the load MOSFET.
The potential is set to a value obtained by subtracting the threshold voltage of QM7.

[0012]

In the conventional semiconductor memory device as described above, the operation of the semiconductor memory device when the address of the defective column line is input and the spare column line is selected will be described with reference to FIG. Explain. If the column line BL1 is selected by the output of the selection signal X1 from the column decoder 26 (time t ₀ ), the column address corresponding to the defective memory cell column, for example, the column line BLn is selected. When the signal is input, the selection signal Xn for selecting the column line BLn output from the column decoder 26 starts to rise (time t ₁ ) and the control signal SPECB for stopping the decoding operation of the column decoder 26 falls. start. After that, at time t ₂ after the signal X1 for selecting the column line BL1 starts to fall, the control signal SPECB becomes the logic “0” level, and the spare memory cell column output from the spare column decoder 27 is selected. The selection signal RX begins to rise. At this time, the potential of the column line BLn also starts to rise.
Then, at time t ₃ , the potential of the selected spare column line also starts to rise, and the output signal of the column decoder 26 switches from the signal X0 to Xn. However, since the column decoder 26 to stop the decoding by the time t ₂ Oite control signal SPECB becomes logic "0", the selection signal Xn is a logic "1" value not reach the level gradually lowered , At time t ₄ , the value of the selection signal Xn becomes the logic “0” level. Moreover, the potential of the defective column line BLn also gradually decreases.

On the other hand, the potential of the spare column line RBL selected by the selection signal RX further rises and approaches a predetermined value.
Accordingly, when the data read from the spare memory cell is “1”, the potential Vin of the detection side node of the sense amplifier 30 also rises, and exceeds the potential Vref of the reference side node of the sense amplifier 30 at time t5. It is detected that the read data is "1".

As described above, in the conventional semiconductor memory device, when the spare column line is selected, after the control signal SPECB is output (becomes the logic "0" level),
(It takes T1 (= t ₄ −t ₂ ) time until the output signal of the column decoder 26 (Xn in the above case) becomes the logic “0” level. Therefore, at least the time t ₂ to the time t _The column line corresponding to the defective memory cell column is charged together with the selected spare column line up to _4. Then, since the read speed generally depends on the charge speed of the column line, a conventional semiconductor memory is required. In the device, there is a problem that the reading speed becomes slow when the spare column line is selected.

The present invention has been made in consideration of the above circumstances, and when the spare memory cell is selected, the data stored in the spare memory cell can be read out as fast as possible. It is an object of the present invention to provide a semiconductor memory device that can be used.

[0016]

In a semiconductor memory device according to the present invention, a spare memory having a memory cell array in which a plurality of memory cells are arranged in m rows and n columns and a spare memory cell column consisting of m spare memory cells is provided. A cell array, a column line from which data of a memory cell of a memory cell column of the memory cell array is read, a spare column line from which data of a memory cell of a spare memory cell column of the spare memory cell array is read, and a column address signal based on a column address signal. A column decoder that outputs a first selection signal that selects a column line corresponding to the column address signal, and a second decoder that selects one spare memory cell column based on the column address signal of the defective memory cell column of the memory cell array. A spare column decoder that outputs a selection signal and a control signal, and a column gate that selects one corresponding column line based on the first selection signal. Circuit, a spare column gate circuit for selecting one corresponding spare column line based on the second selection signal, and a potential of the selected column line or spare column line is amplified and compared with a reference potential, and compared. When the spare column line is selected based on the control signal from the spare decoder and the sense amplifier that outputs according to the result, the connection is switched to electrically connect the defective column line corresponding to this spare column line from the sense amplifier. Connection switching means for disconnecting and electrically connecting the spare column line to the sense amplifier.

[0017]

According to the semiconductor memory device of the present invention configured as described above, the first selection signal is output from the column decoder when the spare column line is not selected, but the second selection is performed from the spare column decoder. No signal or control signal is output. As a result, only one column line is selected by the column gate circuit, and only the selected column line is connected to the sense amplifier via the connection switching means. When the spare column line is selected, the column decoder outputs the first selection signal and the spare column decoder outputs the second selection signal and the control signal. As a result, one spare column line is selected by the column gate circuit, but in this case, the connection switching means connects only the selected spare column line to the sense amplifier. As a result, the column line and the spare column line are not simultaneously charged by the sense amplifier, and the data read operation when the spare column line is selected can be performed at high speed.

[0018]

1 shows the configuration of a first embodiment of a semiconductor memory device according to the present invention. The semiconductor memory device of this embodiment is
In the conventional semiconductor memory device shown in FIG. 4, a column gate transistor circuit (hereinafter, also referred to as a column gate) 2
8 and a node SA (see FIG. 5) on the detection side of the sense amplifier 30 include one N-channel transistor MOS1.
And the control signal SPECB from the spare column decoder 27 is input to the gate of the transistor MOS1. One terminal of the source or the drain of the transistor MOS1 has one end at the column line BLi (i = 1, ...
n) the transistor BT of the column gate 28 connected to
i is connected to the other end, and the other terminal is connected to the detection-side node SA of the sense amplifier 30. Each transistor of the spare column gate 29 of this embodiment has one end connected to the corresponding spare column line and the other end connected to the node SA, as in the conventional case. Also, the control signal SPE
Unlike the conventional case, the CB is not sent to the column decoder 26. That is, when the spare column line is selected, the decoding operation of the column decoder 26 is not prohibited.

Therefore, in this embodiment, when the spare memory cell column in the spare memory cell array 24 is selected, the control signal SPECB becomes the logic "0" level and the selection command signal becomes the logic "1" level. , The transistor MOS1 is turned off and the spare column gate 29 is turned on.
As a result, the node SA is electrically separated from the column lines BL1, ... BLn and the selected spare column line RBLi.
(I = 1, ..., N1) is electrically connected. On the contrary, when the memory cell column of the memory cell array 23 is selected, the control signal SPECB goes to the logic "1" level and the selection command signal goes to the logic "0" level.
When the OS1 is turned on and the spare column gate transistor 29 is turned off, the node SA is electrically connected to the selected column line BLi (1 ≦ i ≦ n), and the spare column lines RBL1, ... RBLn ₁ And are electrically separated.

In the thus configured semiconductor memory device of the first embodiment, the read operation of the memory cell data when the spare column is selected will be described with reference to FIG. now,
When the column line BL1 is selected by the selection signal X1 being output from the column decoder 26 (time t ₀ ),
A column line connected to the defective memory cell column, for example, the column line BLn
When the column address signal for selecting is selected, the selection signal Xn for selecting the column line BLn from the column decoder 26 starts to rise (time t ₁ ), and the transistor MOS1 is selected.
The control signal SPECB that is input to the gate of the gate starts falling. After that, at time t ₂ after the signal for selecting the column line BL 1 starts to fall, the control signal SPECB becomes the logic “0” level, and the selection signal RX for selecting the spare memory cell column output from the spare column decoder 27 is output. Begins to rise. At this time, since the SPECB becomes the logic "0" level, the transistor MOS1 is turned off and the column line BL
1, ... BLn is a node SA, that is, the sense amplifier 30
And electrically separated.

At time t ₃ , the potential of the selected spare column line RBLj (1 ≦ j ≦ n ₁ ) also starts to rise and the output signal of the column decoder 26 switches from X0 to Xn. At this time, in the present embodiment, unlike the conventional case, since the control signal SPECB is not input to the column decoder 26, the selection signal Xn continues to rise and reaches the logic "1" level.

After that, at time t ₄ , the selection command signal RX from the spare column decoder 26 becomes a logic "1" level and the selected spare column line RBLj (1≤j≤n1) and the node SA, that is, the sense amplifier. 30 is electrically connected and the potential of the selected spare column line is charged to a predetermined potential, and the potential Vin of the detection side node of the sense amplifier 30 becomes higher than the potential Vref of the reference side node. At time t5 '(time t5'), the output signal D of the sense amplifier 30 changes, and the data in the memory cell is read.
At time t ₂ , the control signal SPECB goes to the logic “0” level, so that the column line BLn corresponding to the defective memory cell column is electrically isolated from the node SA and remains at zero volt without being charged. The potential of the column line BL1 selected by the selection signal X1 is gradually discharged by selecting the defective column line BLn.

As described above, when the spare column line is selected, the column line corresponding to this spare column line, for example, the column line BL.
Since the spare column line is selected and charged after n is electrically disconnected from the node SA, the charging time of the spare column line is shortened and the read speed can be increased. For example, the potential Vin of the detection side node is equal to the potential Vref of the reference side node.
As shown in FIG. 2, the time to reach the time t is time t ₅ ′ in the present embodiment, whereas time t ₅ (> t in the conventional case is reached.
₅ '), and the time _{T2 (= t 5 -t 5'} ) only become high speed is the thing.

Next, the configuration of the second embodiment of the semiconductor memory device according to the present invention is shown in FIG. The semiconductor memory device according to the second embodiment is the same as the semiconductor memory device according to the first embodiment.
Spare column gate transistor circuit 29 and node SA
A circuit MO for providing an N-channel MOS transistor MOSR between the two, receiving the control signal SPECB to generate an inverted signal bar SPECB thereof, and sending the inverted signal bar SPECB to the gate of the transistor MOSR.
This is a new SX. Therefore, in the second embodiment, when the column line BLi (1≤i≤n) is selected (when the control signal SPECB is at the logic "1" level), the transistor MOS1 is turned on and the transistor MOSR is turned off. Therefore, the node SA is electrically connected to the selected column line BLi but is not connected to the spare column line RB.
It is electrically separated from L1, ..., RBLn ₁ . Further, when the spare column line RBLj (1 ≦ j ≦ n ₁ ) is selected, the transistor MOS1 is turned off and the transistor MOSR is turned on, so that the node SA is electrically connected to the selected spare column line RBLj. And the column line BL
, ... BLn are electrically separated from each other. This makes the second
This embodiment can also obtain the same effect as the first embodiment.

[0025]

According to the present invention, the column line and the spare column line are not charged at the same time, and the data read operation when the spare column line is selected can be performed at high speed.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a first exemplary embodiment of the present invention.

FIG. 2 is a graph illustrating the operation of the first embodiment.

FIG. 3 is a block diagram showing the configuration of a second embodiment.

FIG. 4 is a block diagram showing a configuration of a conventional semiconductor memory device.

5 is a circuit diagram of the conventional semiconductor memory device shown in FIG.

FIG. 6 is a graph illustrating the operation of the conventional semiconductor memory device.

[Explanation of symbols]

 21 row address buffer 22 row decoder 23 memory cell array 24 spare memory cell array 25 column address buffer 26 column decoder 27 spare column decoder 28 column gate transistor circuit 29 spare column gate transistor circuit 30 sense amplifier 31 output buffer MOS1 MOS transistor SA sense amplifier Detecting node of

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Kazuhisa Kanazawa 580-1, Horikawa-cho, Kawasaki-shi, Kanagawa Kanagawa Prefecture Semiconductor Semiconductor Technology Center (72) Inventor Yamamura Toshio Kawasaki, Kanagawa 580-1 Horikawa-cho, Saiwai-ku, Toshiba Corporation Semiconductor System Technology Center (72) Inventor Isao Sato 25-1 Kawasaki-ku, Kawasaki-ku, Kanagawa Prefecture

Claims (1)

[Claims] 1. A memory cell array in which a plurality of memory cells are arranged in m rows and n columns, a spare memory cell array having a spare memory cell column composed of m spare memory cells, and a memory of the memory cell column of the memory cell array. A column line from which cell data is read, a spare column line from which data of a memory cell in a spare memory cell column of the spare memory cell array is read, and a column line corresponding to this column address signal based on a column address signal are provided. A column decoder that outputs a first selection signal to be selected, and a second selection signal that selects one spare memory cell column based on a column address signal of a defective memory cell column of the memory cell array are output together with a control signal. A spare column decoder for outputting, a column gate circuit for selecting one corresponding column line based on the first selection signal, and the second selection signal A spare column gate circuit that selects one corresponding spare column line based on the sense amplifier, and a sense amplifier that amplifies the potential of the selected column line or the spare column line and compares it with a reference potential, and outputs according to the comparison result. When the spare column line is selected based on the control signal from the spare decoder, the connection is switched to electrically disconnect the defective column line corresponding to the spare column line from the sense amplifier and sense the spare column line. A semiconductor memory device comprising: a connection switching unit electrically connected to an amplifier.