KR920005154B1 - Nonvolatile semiconductor memory - Google Patents

Abstract

No content.

Description

Nonvolatile Semiconductor Memory

1 is a circuit diagram showing the configuration of a nonvolatile semiconductor memory device according to an embodiment of the present invention.

2 and 3 are timing charts of the circuit shown in FIG. 1, respectively.

4 is a circuit diagram showing the configuration of a conventional nonvolatile semiconductor memory device.

5 is a timing chart of the circuit shown in FIG.

6 is a waveform diagram of the circuit shown in FIG.

* Explanation of symbols for main parts of the drawings

MC11, MC12, ~, MC1n, ~, MCmn: memory cell

WL1, WL2, ~ WLm: word lines BL1, BL2, ..., BLn: bit lines

BT1, BT2, ~, BTn: Bit line selection transistor

11: Rinse decoder 12: Heat decoder

13 node 14 write selection transistor

15: power supply terminal 16: power conversion circuit

17: output node of the power conversion circuit 22: sense amplifier

23: output buffer

[Industrial use]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device capable of recording data using a nonvolatile memory cell having a double gate structure, and more particularly, to a nonvolatile semiconductor memory device capable of preventing miswriting of data.

[Traditional Technology and Problems]

4 is a circuit diagram showing a partial configuration of a conventional EPROM using a floating gate transistor as a memory cell. In the drawings, reference numerals MC11, MC12,... . MC1n,... And MCmn are memory cells, respectively, and WL1, WL2,... And WLm are word lines, and BL1, BL2,... Denotes a bit line, BT1, BT2,... Where BTn is a bit line selection transistor of a P channel, 11 is a row decoder, 12 is a column decoder, and 13 nodes are connected to a source of the bit line selection transistors BT1 to BTn, and 14 is a P channel recording. The power supply for the transistor 15 is connected to the source of the write transistor 14, and is supplied with a low potential power supply voltage Vcc in the data reading period and a high potential power supply voltage Vpp in the data writing period. The terminal 16 is a power supply conversion circuit, and 17 is an output node of the power supply conversion circuit 16. Here, the power conversion circuit 16 is composed of P channel MOS transistors 18 and 19 and N channel MOS transistors 20 and 21, and has a high potential Vpp according to the write data Din input in the data writing period. Alternatively, the ground potential Vss is output to the output node 17.

Each of the memory cells MC11, ..., MCln, ..., MCmn stores data using a change in the threshold voltage resulting from the injection of photoelectrons into the floating gate, i.e., no electrons are injected. The memory cell corresponds to data "1", and the memory cell into which electrons are injected corresponds to data "0".

In addition, when such electron injection is performed, the high potential for writing is applied to the drain and the gate of the corresponding memory cell, respectively. That is, in the case of writing data into the memory cell MC11, after selecting the word line WL1 with the row decoder 11, the potential of the word line WL1 is set to the high potential for writing and the column decoder ( The bit line BL1 is selected by conducting the bit line selection transistor BT1 through the output of 12).

When writing " 0 " data is executed at this time, the write select transistor 14 is in a conductive state, and the write select transistor 14 and the bit line select for the bit line BL1 are supplied from the power supply terminal 15 to the bit line BL1. The high potential by the power supply voltage Vpp is applied through the transistor BT1. Therefore, the memory cell MC11 is turned on so that a current flows between the source and the drain. At this time, the potential of the bit line BL1 is lower than that of Vpp due to the voltage drop in both transistors 14 and BT1, but the data read state Since the voltage is sufficiently high compared to the bit line potential at (hereinafter, referred to as Vpp '), the high potential is simultaneously applied to both the gate and the drain of the memory cell MC11, thereby draining the channel region between the source and drain. In the vicinity, photoelectrons are generated and injected into the floating gate, whereby data "0" is recorded.

On the other hand, when writing " 1 " data, the write select transistor 14 is in a non-conductive state, so that a high potential is not applied to the bit line BL1 at this time. Therefore, in the memory cell MC11, a high potential is applied to the gate, but only a low potential is applied to the drain, so that electron injection to the floating gate is not performed and data "1" is preserved. Also in the case of the " 0 " write described above, since only the drain cell and the gate have a high potential at the same time, only the memory cell MC11 is allowed to inject electrons into the floating gate from another memory cell. That is, data writing is performed only in the memory cell designated by the address.

However, the low power supply voltage Vcc is supplied to the power supply terminal 15 during the data reading period, but the high potential power supply voltage Vpp is supplied instead of the power supply voltage Vcc in the data writing period as described above. The data write operation is started by detecting the switching of the voltage supplied to the power supply terminal 15 with a voltage detection circuit (not shown).

)나 칩·이네이블신호(

)가 소정시간동안 "0"레벨로 설정된다. 그리고 이 기록제어신호에 동기되어 워드선의 전위가 Vcc에서 Vpp의 전위로 전환됨과 동시에 비트선의 전위가 그 기록상태가 "0"기록상태인가 또는 "1"기록상태인가에 따라서 Vpp'전위나 Vss 전위로 설정되게 된다.5 is a timing chart briefly showing the timing relationship in the data writing operation. When the data writing operation is executed, the power supply voltage supplied to the power supply terminal 15 is switched from Vcc to Vpp. After a predetermined time, a control signal input from the outside, for example, a program signal (

) Or chip enable signal (

) Is set to the "0" level for a predetermined time. In synchronism with the write control signal, the potential of the word line is switched from Vcc to Vpp, and at the same time the potential of the bit line is changed to Vpp 'potential or Vss potential depending on whether the recording state is "0" or "1" recording state. Will be set to.

In the timing chart shown in FIG. 5, T1 is a normal data reading period, and T2 or less corresponds to a data recording period. In particular, this data recording period is a recordable period T3 and a recording prohibition period T2, T4).

In this case, when the memory cell MC11 in Fig. 4 is selected by the address, and the circuit operation period is the write prohibition period which is the period T2 of the timing chart shown in Fig. 5, the power conversion circuit ( The Vpp potential is output from the node 16 to the node 17. Therefore, the write select transistor 14 is in a non-conductive state, so that a high potential is not applied to the bit line BL1.

However, considering the circuit operation when the voltage applied to the power supply terminal 15 is switched from Vcc to Vpp in this state and the period T2 starts, the potential of the node 17 when the period T2 starts. Vcc rises from Vcc to Vpp similarly to the power supply terminal 15. However, since the power conversion circuit 16 is configured using a feedback circuit as shown in FIG. 4, the potential rise of the node 17 causes the power supply terminal to rise. There is a possibility of being delayed compared to the potential rise of (15).

That is, when the write data Din is at " 0 " level, the N-channel MOS transistor 20 becomes non-conductive while the P-channel NOS transistor 18 is in a conductive state in the power conversion circuit 16. 17 is set to the potential Vcc of the power supply terminal 15 by the conducted transistor 18. In this state, when the voltage applied to the power supply terminal 15 rises from Vcc to Vpp as shown by the waveform a in FIG. 6, the node 17 is charged through the transistor 18. The potential rise at the node 17 is delayed compared to the waveform a as shown by the waveform b in FIG. When the on-potential potential difference ΔV becomes larger than the absolute value (| Vthp |) of the threshold voltage of the P-channel MOS transistor due to such a delay, the write select transistor 14 becomes conductive, so that the transistor 14 The bit line BL1 selected by the address is charged to the potential Vpp of the power supply terminal 15 through the conducting transistor 14 in the period T11 during the sixth period in which? In particular, even after the write transistor 14 returns to the non-conducting state because the difference between the potential Vpp of the power supply terminal 15 and the potential of the node 17 becomes smaller than | Since there is no path for discharging the line BL1, the bit line BL1 is charged with the recording high potential.

Although not shown, the column decoder 12 for generating the gate drive signal of the bit line selection transistors BT1 to BTn also uses the same feedback circuit as the power supply change circuit 16 described above. Similarly to the write select transistor 14, the bit line select transistors BT2 to BTn connected to the non-select bit line, which should be originally in a non-conductive state, may be temporarily turned on. Therefore, in the conventional circuit, there is a fear that all the bit lines are charged with the recording high potential, not just the selected bit lines.

Of course, since the word line potential is Vcc in the write prohibition period T2 in FIG. 5, no data is written in the memory cell even if the unselected bit line is charged to the high potential for writing. However, after that, the write control signal is lowered to the " 0 " level and performed in the recordable period (T3; Fig. 5), whereby the word line potential rises to the high potential of Vpp 'and when " 1 " When the word line potential becomes high potential because the bit lines that should not originally become high potential are charged in advance, there is a fear that " 0 " writing is performed for the corresponding memory cell.

That is, as described above, in the conventional nonvolatile semiconductor memory device, there is a possibility that a false recording in which data different from the data to be originally recorded is recorded.

[Purpose of invention]

Accordingly, the present invention has been made in view of the above circumstances, and an object thereof is to provide a nonvolatile semiconductor memory device capable of preventing the occurrence of data miswriting.

[Configuration of Invention]

A nonvolatile semiconductor memory device according to the present invention includes a nonvolatile memory cell having a source, a drain, and a gate, and a double gate structure in which a source is connected to a low potential, a bit line connected with a drain of the memory cell, and a data readout period. Is supplied with a first power supply voltage and one of a power supply terminal, a source, and a drain supplied with a second power supply voltage higher than the first power supply voltage in the data writing period is coupled to the bit line, and the other is connected to the power supply terminal. The first MOS transistor of the P channel, which is coupled and controlled in accordance with the recording data, and one of the source and the drain are coupled to the bit line, and the other is coupled to the low potential, thereby supplying at least a second power supply voltage to the power terminal. This configuration is provided with an N-channel second MOS transistor that is controlled to be in a conductive state temporarily at the start.

Further, in the nonvolatile semiconductor memory device according to the present invention, the conductance of the second MOS transistor is set to be larger than the conductance of any MOS transistor including the first MOS transistor inserted between the power supply terminal and the bit line.

[Action]

According to the present invention having the above-described configuration, when the supply of the second power supply voltage to the power supply terminal is started, the second power supply voltage is controlled by temporarily controlling the N-channel second MOS transistor inserted between the bit line and the low potential in a conductive state. After the start of supply of the bit line, the bit line charged with the second power supply voltage is discharged to low potential. At this time, the conductance of the second MOS transistor is set to be larger than the conductance of any MOS transistor including the first MOS transistor inserted between the power supply terminal and the bit line, so that the bit line potential is sufficient when the second MOS transistor is turned on. It is possible to lower to a low potential.

EXAMPLE

Hereinafter, an embodiment according to the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing the configuration of a part of the present invention when the present invention is implemented in an ERROM using a floating gate type nonvolatile transistor as a memory cell.

In Fig. 1, reference numerals MC11, MC12,... , MC1n,... And MCmn are floating-gate transistors and memory cells arranged in a matrix form. The sources of these memory cells MC11, MC12, ..., MC1n, ..., MCmn are grounded. The gates of the n memory cells arranged in the same row among the memory cells MC11, MC12, ..., MC1n, ..., MCmn are m word lines WL1, WL2, which are driven by the output of the row decoder 11. The drains of each of the m memory cells arranged in parallel in the same column and connected in one of the WLm are connected in parallel to the corresponding one of the n bit lines BL1, BL2, ..., BLn. It is.

Drains of the bit line selection transistors BT1, BT2, ..., BTn made of P-channel MOS transistors driven by the output of the column decoder 12 are connected to the n bit lines BL1, BL2, ..., BLn. Although the sources of these transistors BT1, BT2,..., BTn are commonly connected to the node 13. The node 13 is connected with a drain of a write select transistor 14 made of a P-channel MOS transistor. The transistor 14 is supplied with a low potential power supply voltage Vcc to the source during a data read period. In addition, during the data writing period, the power supply terminal 15 to which the high potential power supply voltage Vpp is supplied is connected, and the signal of the output node 17 of the feedback type power conversion circuit 16 is supplied to the gate thereof. .

The power conversion circuit 16 is composed of P-channel MOS transistors 18 and 19 and N-channel MOS transistors 20 and 21, and has a high potential Vpp based on the data Din input in the data writing period. Alternatively, the ground potential Vss is output to the output node 17. The node 13 is connected with a sense amplifier 22 that detects data by detecting the potential of the node 13 during a data reading period. The data detected by the sense amplifier 22 is output buffer 23. Is output as the output data Dout.

On the other hand, the reason for using the feedback type circuit as the above-described current conversion circuit 16 is as follows.

When the current conversion circuit 16 is not used as a feedback type circuit, the high-potential power supply voltage Vpp is supplied to the power supply terminal 15 because the "1" level of the write data Din is a Vcc potential lower than Vpp. At this time, even if the write data Din is at " 1 " level, the P-channel MOS transistor 18 in the power supply conversion circuit 16 is not brought into a non-conductive state.

However, when the current conversion circuit 16 is used as a feedback type circuit, when the write data Din at the " 1 " level is input, the N-channel MOS transistor 20 is turned on so that the node 17 moves to a low potential near Vss. In this case, the P-channel MOS transistor 19 is turned on by the potential of the node 17, and the potential of Vpp is supplied to the gate of the transistor 18, thereby bringing the transistor 18 into a non-conductive state. The N-channel MOS transistor 21 in the power conversion circuit 16 prevents the potential of the Vpp from being transferred to the write data Din when the gate potential of the transistor 18 is set to Vpp.

Furthermore, the respective drains of the bit line discharge transistors BD1 to BDn each consisting of N channel MOS transistors are connected to the bit lines BL1 to BLn, respectively, and the sources of these transistors BD1 to BDn are all grounded. In addition, the gate is connected in common and the reset signal RST is supplied. The conductance (gm value) of each of the bit line discharge transistors BD1 to BDn is a transistor 14 and a bit line selection transistor BT1 inserted in series between the power supply terminal 15 and each bit line. It is set so as to be larger than the conductance of any of ~ BTn).

In the circuit shown in FIG. 1, the bit line selection transistor is composed of one stage. However, this is for simplicity of explanation. The bit line selection transistor is connected in series of two or more stages depending on the number of bit lines. It is common to have an inverted tree structure along the bit line based on the node 13. In the case where the EPROM has a multi-bit configuration, a plurality of circuits as shown in FIG. 1 are provided as many as the bit components of the data to be written or read at a time. However, in this case, the row decoder 11 and the column are also provided. Only the decoder 12 is provided in common for all the bits.

Next, the operation of the EPROM having the above configuration will be described.

FIG. 2 is a timing chart for explaining the operation of the EPROM having the above-described configuration. In FIG. 2, T1 is a normal data reading period, and T2 or less is a data writing period. In particular, this recording period consists of a recordable period (T3), a record prohibition period (T2, T4), and a search period (T5) of the record data. In this search period, the recording is performed without changing the address immediately after data recording is executed. Data is read from the executed memory cell, and verification is made as to whether or not the recorded data matches the recorded data.

)나 칩이네이블신호(

)가 소정시간동안 "0"레벨로 설정되고, 또 그 기록제어신호에 동기되어 워드선의 전위가 Vcc에서 Vpp의 레벨로 전환됨과 동시에 비트선의 전위가 "0"기록상태인가 "1"기록상태인가에 따라서 Vpp 또는 Vss 전위로 설정되게 된다.When the data write operation is executed for the memory cell, the power supply voltage supplied to the power supply terminal 15 is switched from Vcc to Vpp as in the conventional case. After a predetermined time from the switching of the voltage, the write control signal, for example, the program signal (

) Or chip enable signal (

) Is set to the "0" level for a predetermined time, and in synchronization with the write control signal, the potential of the word line is switched from the level of Vcc to Vpp and the potential of the bit line is in the "0" recording state or "1" recording state. Depending on the voltage, Vpp or Vss potentials are set.

Here, when the memory cell MC11 of FIG. 1 is selected by the address, the circuit operation when the voltage applied to the power supply terminal 15 is switched from Vcc to Vpp to start the write prohibition period T2 of FIG. Consider.

When the write prohibition period T2 is started, when the write data Din at the " 0 " level is supplied as described above in the conventional circuit shown in Fig. 4, all the bit lines BL1 to BLn are connected to the transistor ( 14) it is possible to charge to the Vpp potential.

However, in the circuit according to the present embodiment, when the potential of the power supply terminal 15 is switched and the supply of the high potential power supply voltage Vpp is started to the bit lines BL1 to BLn, the bit line discharge transistors BD1 to ... The reset signal RST supplied to the common gate to the BDn is temporarily set to the " 1 " level as shown in, for example, (1) in FIG. 2 (the " 1 " level period of the reset signal RST at this time is the period ( By setting the same size as T2), the bit lines for discharging the transistors BD1 to BDn are turned on and the bit lines BL1 to BLn charged to the Vpp potential are grounded through these transistors BD1 to BDn. Discharged. Then, at the same time as the start of the writeable period T3 of FIG. 2 in which the write control signal is lowered to the " 0 " level, the reset signal RST is lowered to the " 0 " level so that the bit line discharge transistors BD1 to < RTI ID = 0.0 > BDn) all become non-conducting. Therefore, the word line potential becomes high, thereby making it possible to prevent the "0" writing from being accidentally performed on the memory cell.

On the other hand, in the writeable period T3, the potential of the output node 17 of the power conversion circuit 16 corresponding to the bit to which the write data Din at the "1" level is supplied is at the "0" level (Vss). ), The bit select transistor 14 becomes conductive. Therefore, the potential of the node 13 rises to the high potential of Vpp, so that the " 0 " write operation is normally executed at the corresponding bit.

)가 "0"레벨로 저하될때 개시되게 된다.In addition, the reset signal RST shown by 1 in Fig. 2 becomes a " 1 " level even in the period T4 thereafter, which reads the bit line to read the data from the memory cell in the subsequent search period T5. This is because it is necessary to set the low potential for travel. That is, even during the period T4, the bit line discharge transistors BD1 to BDn are turned on by the "1" level of the reset signal RST, so that the bit lines BL1 to BLn are discharged to the ground potential. The bit line selected by this is set to the low potential at the time of reading again by an unshown data reading load circuit provided in the sense amplifier 22. The search period T5 is an output enable signal (externally supplied).

) Is started when the level drops to the " 0 " level.

Instead of the reset signal RST of ①, a signal such as ② of FIG. 2 may be used. In the "1" level period of the reset signal RST, the voltage of the power supply terminal 15 is changed from Vcc to Vpp. Is set shorter than the period from the time of recording until the next recordable period T3 is started. In consideration of the retrieval operation in the period T5, the reset signal RST of (2) also lowers only the first predetermined period of the previous period T4 to the " 0 " level as indicated by the dotted line in the figure.

On the other hand, when the low-potential power supply voltage Vcc is supplied from the outside and the high-potential recording power supply voltage VPP is supplied to the power supply terminal 15, the timing chart shown in FIG. Similarly, the reset signal RST of 3) may be used, which is set to the "1" level for a predetermined period in synchronization with the rise of the power supply voltage Vcc.

)가 "1"레벨이면서 기록제어신호가 "0"레벨로 되어 있는 기간과, 전원전압(Vpp)이 공급되고 있는 기간에 출력이네이블신호(

)가 "0"레벨이면서 기록제어신호가 "1"레벨로 되어 있는 기간을 제외한 기간에서는 그 출력이 "1"레벨로 되도록 논리회로를 조합함으로서 발생시킬 수 있다.In addition, the reset signal RST of the above ① is an output enable signal (A) during a period in which the power supply voltage Vpp is being supplied.

) Is at the "1" level, the write control signal is at the "0" level, and the output enable signal (

Can be generated by combining logic circuits such that the output is at " 1 " level except for a period in which " 0 "

In addition, the reset signal RST in the above ② can be generated by using a circuit capable of detecting the rise of the potential to the power supply voltage Vpp in the same manner as in the normal address transition test circuit. The set signal RST can be generated by using a so-called power-on circuit that detects a rise in potential to the power supply voltage Vpp.

By the way, in many EPROMs, a search for discharging the bit line potential when transitioning from the recording mode (the operation mode in the period T3 during the second middle) to the search mode (the operation mode in the period T5 during the second middle) is performed. A reset transistor for each bit line is provided. Therefore, as shown in FIG. 1, it is also possible to use the reset transistor for searching without installing new transistors BD1 to BDn. That is, by supplying the reset signals RST of the above ①, ②, and ③ to the gates of the search reset transistor through the OR gate circuit, the search reset transistor causes the search reset transistor and the transistors BD1 to ... BDn), which can reduce the number of elements, thereby avoiding an increase in chip area in the case of direct circuit.

In addition, even when the search reset transistor serves both the transistors BD1 to BDn, the conductance of the transistor must be set sufficiently larger than that of the transistor 14 or the bit line selection transistors BT1 to BTn.

[Effects of the Invention]

As described above, in the nonvolatile semiconductor memory device according to the present invention, the N channel MOS transistor inserted between the bit line and the low potential is temporarily controlled to be in a conductive state when the high potential power supply ab is started to the power supply terminal. Since the electric potential is discharged to a low electric potential, it is possible to prevent the miswriting of data.

Claims (2)

Nonvolatile semiconductor memory cells MC11 to MCmn having a double gate structure having a source, a drain and a gate, and a source connected to a low potential, and bit lines BL1 to drains of the memory cells MC11 to MCmn connected. BLn), the power supply terminal 15 and the source supplied with the first power supply voltage Vcc during the data reading period and with the second power supply voltage Vpp having a higher potential than the first power supply voltage Vcc during the data writing period. A P-channel first MOS transistor 41 in which one of the drains is coupled to the bit lines BL1 to BLn while the other is coupled to the power supply terminal 15 and controlled to be conducting according to the write data Din. One of the source and the drain is coupled to the bit lines BL1 to BLn while the other is coupled to the low potential (ground potential), and at least the supply of the second power supply voltage Vpp is supplied to the power supply terminal 15. N-channel second MOS temporarily controlled to conduction state when starting Transistor (BD1 ~ BDn) non-volatile semiconductor memory device, characterized in that configured with a. The method of claim 1, wherein the conductance of the second MOS transistors BD1 to BDn includes the first MOS transistor 14 inserted between the power supply terminal 15 and the bit lines BL1 to BLn. A nonvolatile semiconductor memory device, characterized in that it is set larger than the conductance of a MOS transistor.

Images