JPH0660108A - Discrete cosine/inverse discrete cosine transformation device - Google Patents

Abstract

PURPOSE:To provide the discrete cosine/inverse discrete cosine transformation device whose circuit scale is reduced with respect to the discrete cosine/inverse discrete cosine transformation device used for a high efficiency coding device for a picture signal or the like. CONSTITUTION:In the discrete cosine/inverse discrete cosine transformation device provided with a 1st orthogonal transformation section 100 which employs a matrix [C] for orthogonal transformation coefficients and a transposed matrix [C]<t> for a matrix [f] for picture signals for each of plural blocks each comprising the prescribed number of picture elements in the horizontal and vertical directions and obtains a matrix [F] by applying discrete cosine transformation expressed in equation [F]=[C][f][C]<t> to the picture elements in the horizontal and vertical directions, with a 2nd orthogonal transformation section 300 which obtains the matrix [f] for picture signals by applying inverse discrete cosine transformation expressed in equation [f]]=[C] [F][C] to the matrix [F] in the horizontal and vertical directions, the sequence of the transformation in the horizontal and vertical directions is made symmetrical between the 1st orthogonal transformation section 100 and the 2nd orthogonal transformation section 300.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a discrete cosine / inverse discrete cosine converter used in a high-efficiency coding apparatus for image signals.

A high-efficiency coding method of an image signal using discrete cosine transform (hereinafter referred to as DCT transform) is, for example, dividing a pixel into blocks of 8 × 8 pixels and spatially converting the image signal of each block by DCT transform. This is a method of converting the coefficient into a frequency distribution coefficient, quantizing it with a threshold value adapted to the visual sense, and encoding the obtained quantized coefficient by a predetermined method. In this case, there is a demand for a discrete cosine / inverse discrete cosine converter capable of reducing the circuit scale.

[0003]

2. Description of the Related Art Now, assuming that an image signal (original signal) is [f], a converted signal is [F], and a conversion coefficient is [C], two-dimensional DCT conversion (hereinafter referred to as forward conversion) and inverse DCT conversion. (Less than,
The inverse transformation) is expressed as the following equation.

[F] = [C] [f] [C] ^t ... (1) (forward conversion) [f] = [C] ^t [F] [C] ... (2) (inverse conversion) ) Here, [C] ^t is a transposed matrix of [C].

When the DCT algorithm is realized by hardware, several methods are possible. Realize the conversion formula as it is.

The calculation results of DCT and IDCT are stored in a memory, and conversion is performed by a look-up table method. Performs calculations using high-speed algorithms.

In the standardized method of image coding, a DCT having 8 × 8 pixels as one unit is basically used, so that a two-dimensional D
In CT, a matrix operation of an 8 × 8 matrix, that is, two sets of product-sum operation circuits for 64 times are required, and the circuit scale becomes very large.

Therefore, it has been a world-wide need to reduce the circuit scale as much as possible, regardless of which method is used.

[0009]

DISCLOSURE OF THE INVENTION As described above,
Even if any of the above methods is adopted, there is a problem that the circuit scale must be reduced as much as possible.

Therefore, an object of the present invention is to provide a discrete cosine / inverse discrete cosine converter capable of reducing the circuit scale.

[0011]

The above problems are caused by the problems shown in FIGS.
It is solved by the circuit configuration shown in. In FIG. 1 showing the principle configuration of claim 1, the order of performing horizontal conversion and vertical conversion is symmetrical between the first orthogonal transformation unit 100 and the second orthogonal transformation unit 300.

In FIG. 2 showing the principle configuration of claim 2,
The first orthogonal transformation unit 100 according to claim 1, wherein the first matrix calculation module 110 outputs the matrix [f] of the image signal multiplied by the transposed matrix [C] ^t , and a first matrix. A first transposition conversion module 170 that transposes and outputs the output matrix of the calculation module, and a second matrix calculation module that outputs the matrix of the output of the first transposition conversion module by the transposed matrix [C] ^t 190 and a first transposed zigzag conversion module 250 that transposes the matrix of the output of the second matrix operation module and then performs zigzag conversion and outputs.

The second orthogonal transformation unit 30 according to claim 1.
0 is a second transposed zigzag conversion module 350 that zigzag-transforms the transformed matrix [F] and then transposes the transformed matrix [F], and outputs the matrix [C] to the output matrix of the second transposed zigzag transformation module. ] The third matrix operation module 460 which outputs by multiplying, the second transposition conversion module 530 which transposes and outputs the matrix of the output of the third matrix operation module, and the matrix of the output of the second transposition conversion module And a fourth matrix operation module 540 which outputs the matrix [C] by multiplying

[0014]

In FIG. 1, for example, when the first orthogonal transform unit 100 performs the horizontal transform first and the vertical transform second, the second orthogonal transform unit 300 performs the vertical transform 1 Perform second, and perform horizontal conversion second.

Next, the operation and effect obtained by the configuration shown in FIG. 2 will be described below. In FIG. 3, when the discrete cosine transform formula (1) is called a forward transform and the inverse discrete cosine transform formula (2) is called an inverse transform, the forward transform of the formula (1) and the formula (2) are called.
In the case of the reverse conversion of, the result is the same regardless of which of the horizontal conversion and the vertical conversion is performed first. Therefore, in the case where this arithmetic expression is directly subjected to matrix calculation and realized by hardware, there are four possible methods (a) to (d) shown in FIG.

Here, (a) and (d) are conversion systems in which forward conversion and inverse conversion are asymmetrical, and (b) and (c) are conversion systems in which forward conversion and inverse conversion are symmetrical. Now, consider the case where the forward transformation is fixed and the inverse transformation is symmetric and asymmetric, for example, (c) and (d). With this equation as it is, [f] (or [F]) is converted into the conversion coefficient [C].
Alternatively, there are cases where [C] ^t is applied from the left and when it is applied from the right, and the hardware becomes complicated. Therefore, conversion is performed as shown in FIG. Equation (1) 'in FIG. 4 is the forward transformation of (c) and (d) in FIG. 3, Equation (2)' is the inverse transformation of (c), and (2) '' is
It is the inverse transformation of (d).

Now, considering a matrix operation module for multiplying the original signal [f] by the matrix [C] of transform coefficients from the right and a module for transposing the matrix, equations (1) ', (2)',
The hardware configuration of (2) '' is as shown in FIG.

By the way, in the case of performing high-efficiency compression of an image signal, Huffman coding is often performed after performing orthogonal transformation such as DCT transformation. In order to efficiently perform this Huffman coding, it is convenient to rearrange two-dimensional DCT data one-dimensionally from low-frequency data to high-frequency data, that is, perform zigzag scanning. Further, considering that it is possible to perform two transpose transformations of a matrix and zigzag scan transformations at the same time, FIG. 5 becomes as shown in FIG.

As can be seen from FIG. 6, in the inverse transformation (2) 'and the inverse transformation (2)'', the former does not need to perform the transposition transformation in the second subsequent stage. Therefore, the inverse transform (2) ′ can be made smaller in circuit scale than the inverse transform (2) ″. The principle structure of this inverse transformation (2) 'is shown in FIG.
It is indicated by (2). The principle structure of the above formula (1) 'is shown by (1) in FIG.

[0020]

FIG. 7 is a block diagram (transmission side, part 1) showing a configuration of a DCT circuit according to an embodiment of the present invention.

FIG. 8 is a block diagram (transmission side, part 2) showing the configuration of the DCT circuit of the embodiment of the present invention. FIG. 9 is a configuration diagram of [f], [c], and [c] ^{t in} the embodiment.

FIG. 10 is a time chart for explaining the operation of the matrix calculation module of the embodiment. FIG. 11 is a diagram showing an input / output scanning method of the transposed raster scan conversion module in the embodiment.

FIG. 12 is a diagram showing an input / output scanning method of the transposed zigzag scan conversion module in the embodiment. FIG. 13 is a block diagram (reception side, part 1) showing the configuration of the DCT circuit of the embodiment of the present invention.

FIG. 14 is a block diagram (reception side, part 2) showing the configuration of the DCT circuit of the embodiment of the present invention. The same reference numerals denote the same objects throughout the drawings.

The matrix calculation module 11 on the transmission side shown in FIG.
In the circuit of FIG. 9, the input signal matrix [f] and the conversion coefficient matrices [c] and [c] ^t are configured as shown in FIG.
X2 matrix. The matrix [c] ^t obtained by transposing the matrix [c] is stored in the coefficient [c] ^t storage memory 2 in advance. Then, the data stored at the address designated by the read address generator 3 is read from the coefficient [c] ^t storage memory 2, and the multiplier 1 multiplies it with the matrix [f] of the input signal.
In this case, [f] is input to the multiplier 1 in synchronization with the clock (CK ₁ ) shown in FIG. 10 (1), and [c] ^t is input to the multiplier 1 in synchronization with the clock (CK ₂ ). CK ₁ is CK ₂ divided by half (see FIGS. 10 (1) and 10 (3)).

The multiplier 1 converts the conversion coefficient into the signal matrix [f].
Matrix [c]^tThe method of hanging from the right. And multiplication
Result X₁₁C₁₁Is temporarily stored in the work register 4 (see FIG. 10).
(See (6)). Next CK₂Multiplication result obtained at the timing of
Fruit X₁₁C_{twenty one}10 is temporarily stored in the work register 7.
(See (8)). Next CK₂Squared obtained at the timing
Calculation result X₁₂C₁₂And 2 temporarily stored in the work register 4
Multiplication result before clock X ₁₁C₁₁And add with adder 5
And the result (X₁₁C₁₁+ X₁₂C₁₂) To register 6
It is temporarily stored in (see FIG. 10 (10)).

Similarly, the next CK₂Obtained at the timing of
Multiplication result X₁₂C_{twenty two}And temporarily store it in the work register 7.
Multiplication result X two clocks before₁₁C_{twenty one}And are added by adder 8
And get the result (X₁₁C_{twenty one}+ X₁₂C_{twenty two}) Register
It is temporarily stored in 9 (see FIG. 10 (12)). And register
6 and the calculation result temporarily stored in the register 9 (in parallel
Data) is read alternately and parallel / serial conversion is performed.
Data (hereinafter referred to as P / S converter) 10 for serial data
And output it (see Fig. 10 (13)). In this way
The matrix calculation module 11 converts the input signal into a matrix [f].
Matrix of numbers [c] ^tFrom the right, and calculate the result
Output.

Next, the output of the matrix operation module 11 described above is added to the transposed raster scan conversion double buffer 12 in the transposed raster scan conversion module 17 shown in FIG. As shown in FIG. 11, the transposed raster scan conversion module is a module for outputting matrix elements input in the raster scan order in the transposed raster scan order.
Double buffer 12 for transposed raster scan conversion is internally 2
There are two memories (probably memories a and b), and the two memories are alternately written and read.

That is, first, the data input from the matrix operation module 11 is written into the address of the memory a designated by the write address generator 13. At the same timing, the data stored in the address of the memory b designated by the read address generator 14 is read. Selector 16 with read data
Via switch to switch 18. In this case, the reading is performed in the transposed order.

At the next timing, the address exchange 15 switches the address access destination, and the write address generator
Input data is written in the address of the memory b designated by 13 and the data stored in the address of the memory a designated by the read address generator 14 is read at the same timing. The read data is added to the switch 18 via the selector 16 as described above.

When transmitting audio data, the switch 18 switches to the B side and sends the above data to the transmission line as a one-dimensional conversion output. In this case, in order to transmit the image data, it is switched to the A side and the above data is sent to the matrix calculation module 19. The matrix calculation module 19 has the same circuit configuration as the matrix calculation module 11 shown in FIG. 7 and performs the same operation as described above, and therefore its description is omitted.

Next, the transposed zigzag scan conversion module 25 shown in FIG.
Add to double buffer 20 for zigzag scan conversion. The configuration of the transposed zigzag scan conversion module is the same as the transposed raster scan conversion module described above, except that the zigzag scan conversion double buffer 20 is different from the transposed raster scan conversion double buffer 12. The zigzag scan conversion double buffer 20 has two memories (probably memories c and d) therein.
The two memories are alternately written and read. In this case, the read address is set to the zigzag scan address (see FIG. 12).

That is, first, the data input from the matrix calculation module 19 is written into the address of the memory c designated by the write address generator 21. At the same timing, the data stored in the address of the memory d designated by the read address generator 22 is read. Selector 24 for read data
Is output to a circuit (not shown) in the subsequent stage as an output signal [F].

At the next timing, the address exchange 23 switches the address access destination, and the write address generator
Input data is written to the address of the memory d designated by 21 and the data stored at the address of the memory c designated by the read address generator 22 is read at the same timing. The read data is output as the output signal [F] via the selector 16 in the same manner as described above, and the circuit in the subsequent stage (not shown)
Send to.

In this way, on the transmitting side, the following formula of forward conversion [F] = [C] [f] [C] ^t = [{[f] [C] ^t } ^t [C] ^t ] ^t (1 ) 'Is given as [F], first, the matrix operation module 11 obtains [f] [C] ^t , and the transposed raster scan conversion module 17 produces {[f]
[C] ^t } ^t is obtained and {[f] [C] ^t } is calculated by the matrix calculation module 19.
^{Calculate t} [C] ^t . Then, the transposed zigzag scan conversion module 25 further obtains [F] in the equation (1) ′.

Next, on the receiving side, the signal [F] input from the circuit (not shown) in the preceding stage is added to the zigzag scan conversion double buffer 30 in the transposed zigzag scan conversion module 35 shown in FIG. The configuration of the transposed zigzag scan conversion module 35 is the same as that of the transposed zigzag scan conversion module 25 on the transmission side described above, and the operation thereof is also the same as that described above, and therefore the description thereof is omitted. The output of the transposed zigzag scan conversion module 35 is added to the multiplier 36 in the matrix calculation module 46.

The configuration of the matrix calculation module 46 is also the same as that of the matrix calculation module 11 (see FIG. 7) on the transmitting side except that the coefficient [C] storage memory 38 is different from the coefficient [C] ^t storage memory 2. Since it is the same as that, the description thereof is omitted. The output of the P / S converter 45 in the matrix operation module 46 is added to the transposed raster scan conversion double buffer 48 in the transposed raster scan conversion module 53 via the switch 47 shown in FIG.

The configuration of the transposed raster scan conversion module 53 is also the same as that of the transposed raster scan conversion module 17 (see FIG. 8) on the transmission side, and therefore its explanation is omitted. The output of the selector 52 in the transposed raster scan conversion module 53 is added to the matrix calculation module 54. The configuration of the matrix calculation module 54 is also the same as that of the matrix calculation module 46 (see FIG. 13) described above, and thus the description thereof will be omitted. Then, the output signal [f] is obtained from the matrix calculation module 54.

Thus, on the receiving side, the inverse transform is given by the following equation [f] = [C] ^t [F] [C] = {[F] ^t [C]} ^t [C] (2) '. First, the transposed zigzag scan conversion module 35 [F] ^t
The matrix calculation module 46 calculates [F] ^t [C], and the transposition calculation raster scan conversion module 53 calculates {[F] ^t [C]} ^t . Then, the matrix calculation module 54 further obtains [f] in the equation (2) to obtain the output.

When the one-dimensional conversion signal is input, the switch 47 (see FIG. 14) described above is switched to the D side, and in addition to the transposed raster scan conversion module 53, the audio data is further transmitted via the matrix calculation module 54. obtain.

As a result, the structure of the DCT conversion system is targeted for the forward conversion (transmission side) and the inverse conversion (reception side), and the zigzag conversion module and the transposition conversion module are combined into one module structure on the reception side to form a matrix. The circuit scale can be reduced by simultaneously performing the transpose conversion and the zigzag scan conversion.

Further, with the above configuration, conversion / inverse conversion of a one-dimensional signal (voice signal) is possible. Further, the above-described configuration is applicable not only to the discrete cosine transform, but also to other transform systems that perform matrix calculation (for example, Hadamard transform, Karhunen-Lobe transform, etc.).

[0043]

As described above, according to the present invention, the configuration of the discrete cosine / inverse discrete cosine transformer is made symmetrical by the forward transform and the inverse transform, and the zigzag transform module and the transpose transform module are set to one on the receiving side. The circuit scale can be reduced by adopting one module configuration and performing the transpose conversion and the zigzag scan conversion of the matrix at the same time.

Further, with the configuration of the present invention, conversion / inverse conversion of a one-dimensional signal (voice signal) is possible. Furthermore, the configuration of the present invention is applicable not only to the discrete cosine transform but also to other transform systems that perform matrix operations (for example, Hadamard transform, Karhunen-Lobe transform, etc.).

[Brief description of drawings]

FIG. 1 is a principle diagram of the invention of claim 1,

2 is a principle diagram of the invention of claim 2, FIG.

FIG. 3 is a diagram showing symmetry / asymmetry of a discrete cosine transform / inverse discrete cosine transform formula in the present invention,

FIG. 4 is a diagram showing an expression obtained by converting the expression of FIG.

5 is a hardware configuration diagram based on the formula of FIG. 4,

6 is a hardware configuration diagram in which a zigzag scanning function is added to FIG. 5,

FIG. 7 is a block diagram (transmission side, part 1) showing a configuration of a DCT circuit of an embodiment of the present invention,

FIG. 8 is a block diagram (transmission side, part 2) showing a configuration of a DCT circuit of an embodiment of the present invention,

FIG. 9 is a configuration diagram of [f], [c], and [c] ^{t in} the embodiment,

FIG. 10 is a time chart for explaining the operation of the matrix calculation module of the embodiment,

FIG. 11 is a diagram showing an input / output scanning method of the transposed raster scan conversion module in the embodiment.

FIG. 12 is a diagram showing an input / output scanning method of the transposed zigzag scan conversion module in the embodiment.

FIG. 13 is a block diagram (reception side, part 1) showing a configuration of a DCT circuit according to an embodiment of the present invention,

FIG. 14 is a block diagram (reception side, part 2) showing a configuration of a DCT circuit according to an embodiment of the present invention.

[Explanation of symbols]

100 is the first orthogonal transform unit, 300 is the second orthogonal transform unit, 11
0 is the first matrix operation module, 170 is the first transpose conversion module, 190 is the second matrix operation module, 250 is the first transposed zigzag conversion module, 350 is the second transposed zigzag conversion module, and 460 is the 3 is a matrix operation module, 530 is a second transposition conversion module, and 540 is a fourth matrix operation module.

Claims (2)

[Claims] 1. An original image is divided into a plurality of blocks each consisting of a predetermined number of pixels in the horizontal and vertical directions, and the orthogonal transformation coefficient of the orthogonal transformation coefficient is added to the obtained image signal matrix [f] of each block. Using the matrix [C] and the transposed matrix [C] ^t of the matrix [C], the formula (1) [F] = [C] [f] [C] ^t (1) is given in the horizontal and vertical directions. A first orthogonal transformation unit (100) for performing a discrete cosine transform to obtain a transformed matrix [F], and the matrix [C] and the transposed matrix [C] with respect to the transformed matrix [F]. ^The inverse discrete cosine transform given by equation (2) [f] = [C] ^t [F] [C] (2) is performed in the horizontal direction and the vertical direction using ^t , and the matrix [f] of the image signal is calculated. A discrete cosine / inverse discrete cosine transformer having a second orthogonal transform unit (300) for obtaining the horizontal transform and the vertical transform. The first orthogonal transformation unit order in which the conversion direction (100) and the second orthogonal transformation unit (300)
A discrete cosine / inverse discrete cosine converter characterized by symmetry with and. 2. The first orthogonal transformation unit according to claim 1.
(100) is a first matrix operation module (110) for multiplying the image signal matrix [f] by the transposed matrix [C] ^t , and transposing the output matrix of the first matrix operation module. And a first transposition conversion module (170) for outputting and a second matrix operation module for outputting the matrix of the output of the first transposition conversion module by the transposition matrix [C] ^t
(190) and a first transposed zigzag conversion module (250) that transposes the matrix of the output of the second matrix calculation module and then zigzag-converts and outputs the resulting matrix. The second orthogonal transformation unit (300) includes a second transposed zigzag transformation module (350) that zigzag-transforms the transformed matrix [F] and then transposes and outputs the matrix, and the second transposed zigzag transformation. A third matrix operation module (460) for multiplying the matrix [C] by the output matrix of the module, and a second transposition conversion module for transposing and outputting the matrix of the output of the third matrix operation module. (530) and a fourth matrix calculation module (54) for outputting the matrix of the output of the second transposition conversion module by multiplying the matrix [C] by the matrix [C].
0) and a discrete cosine / inverse discrete cosine converter characterized in that