JPH0659018B2 - PLL control device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention will be described in the following order.

A Industrial Field B Outline of the Invention C Prior Art (FIGS. 4 and 5) D Problems to be Solved by the Invention (FIG. 5) E Means for Solving Problems (FIG. 1) ) F action (Fig. 1) G embodiment (Figs. 1 to 3) H Effect of the invention A Industrial field of application The present invention relates to a PLL control device, and is applicable to, for example, a television receiver. .

B Outline of the Invention The present invention relates to a PLL control device for controlling a frequency division ratio of a PLL (phase looked loop) circuit by a microcomputer, by using a control data of a first format by a conventional dedicated microcomputer. An attempt to maintain compatibility between a conventional control system and a new control system by making it possible to control a PLL circuit configured to control by the control data of a different second format. Is.

C Conventional Technology For example, in a television receiver, by devising each component into an IC, it is suitable for mass production and a circuit board is downsized.

That is, in the conventional television receiver, as shown in FIG. 4, the channel broadcast wave received in the tuner circuit section 2 via the antenna 1 is amplified in the intermediate frequency circuit section 3, and then the video signal is received. The SV is supplied to the cathode ray tube 5 through the video circuit unit 4, and the audio signal SA is supplied to the speaker 7 through the audio circuit unit 6.

The tuner circuit unit 2 is provided with a PLL circuit 11, and the PLL circuit 11 is a PLL having a microcomputer configuration.
It is controlled by the control circuit 12. Here, the PLL circuit 1
1 is adapted to divide the oscillation signal of the VCO by the programmable frequency divider and give it to the phase comparison circuit, and thus controlling the frequency division ratio of the programmable frequency divider to output the output of the VCO. The frequency of the local oscillation signal can be controlled.

The PLL control circuit 12 is connected to the PLL bus line 13, and the tuning command circuit 1 is connected to the PLL bus line 13.
4 are connected. The channel selection command circuit 14 operates the channel channel selection switch 15 to input channel data having a dedicated format for the PLL circuit selected via the PLL bus line 13 to the PLL control circuit 12.

In addition, the tuning command circuit 14 receives the channel data selected by the remote control operation device 16 and receives the P data.
It can be supplied to the PLL control circuit 12 through the LL bus line 13.

The PLL control circuit 12 transfers the control data to the PLL circuit 11 via the PLL bus line 13 based on the tuning data supplied from the tuning command circuit 14, and thereby the PL
By controlling the frequency division ratio of the programmable frequency divider of the L circuit 11, the tuner circuit section 2 is operated in response to the state of receiving the selected channel.

A non-volatile memory 17 is coupled to the PLL bus line 13, and the non-volatile memory 17 can be used to store tuning command data when the power is off.

Here, the PLL bus line 13 is, as shown in FIG.
It comprises a latch line LAT, a clock line CLK, and a data line DAL.
The channel selection command circuit 1 while transmitting the clock signal to the clock line CLK for the data transmitted to the data line DAL
4, non-volatile memory 17, PLL control circuit 12 to PL
By transferring data to the L circuit 11 and sending a latch signal to the latch line LAT, the data line DAL
It is designed to latch the data in the destination.

In addition to the conventional configuration, recently, each circuit portion of a television receiver is integrated into an IC, and the integrated circuit portion is controlled by a central processing unit (CPU) having a microcomputer configuration. Is being considered.

For example, a configuration in which the intermediate frequency circuit unit 3 is composed of an IC composed of an IF processor, and an IC composed of a video processor is used as the video circuit unit 4 in the subsequent stage and an IC composed of an audio processor is used as the audio circuit unit 6. Can be considered. In this case, the tuner circuit unit 2 also includes the PLL circuit 11, the reception band switching circuit, the AGC.
It is conceivable to integrate circuits and the like into ICs.

In this way, if each circuit part can be integrated into an IC, the CPU can control the television receiver as a whole, so that the television receiver can be further downsized and adjustment of each circuit part at the time of manufacturing can be achieved. It is considered that the above can be easily performed using a CPU.

D. Problems to be Solved by the Invention Thus, as a method of controlling many devices such as microcomputers and ICs by one CPU, it is conceivable to use the I ² C bus (inner IC bus). This I ² C bus is composed of a clock bus line and a data bus line, adds a transfer destination address to the data and sends the data to the data bus line so that the device having the address fetches the data from the data bus line. Is configured.

However, by using such I ² C bus
However, in the case of controlling by using the conventional PLL circuit, there is a disadvantage that the conventional PLL circuit cannot be used as it is because the bus configuration and the data format do not match those of the PLL bus system which has been practically used for the conventional PLL circuit.

The present invention has been made in consideration of the above points, and it is an object of the present invention to make it possible to utilize a PLL circuit which has been practically used in a tuner circuit unit in a conventional control system of an I ² C bus system having a different data format. To do.

E Means for Solving the Problems In order to solve the problems, according to the present invention, the input terminals T1 to T3 connected to the bus line 32 including the data line DAL, the clock line CLK, and the latch line LAT, and the first Is connected to the input terminal T3 corresponding to the latch line LAT and the PLL circuit 42 in which the frequency division ratio of the programmable frequency divider is controlled in response to the data of the first format, and the data supplied from the bus line 32 is first.
Format determining means 60 for determining whether the data has a second format or a second format different from this, a memory circuit 52 for storing the data when the data is supplied from the bus line 32, and a memory. The format of the output data of the circuit 52 is controlled by the format conversion circuit 54 which converts the format of the second format into the first format and outputs it, and the format output of the format determining means 60, and is supplied from the bus line 32. When the discrimination output indicating that the data is the first format is obtained, the data of the input terminals T1 to T3 is directly sent to the PLL circuit 42, or the discrimination output indicating that the data is the second format is obtained. Then, the data of the input terminals T1 to T3 are input to the memory circuit 52, and PLL output data obtained in the conversion circuit 54 is converted into the first the format
A switch means (51, 55) for sending to the circuit 42 is provided.

The F-action format discriminating circuit 60 constantly monitors the signal on the latch line LAT of the bus line 32. When the latch signal does not arrive, the dedicated format for the PLL circuit 42, that is, the data of the first format is transferred through the bus line 32. Determine that it has come. At this time, the format discriminating means 60 operates the switching means (51, 55) to input the data taken in from the bus line 32 to the memory circuit 52, and at the same time, the format of the output data is converted into the second format in the format converting circuit 54. Dedicated first to PLL circuit 42 from format
Switch format (51, 5)
5) to send to the PLL circuit 42.

On the other hand, the format discriminating means 60 discriminates that the data of the second format has been transferred to the bus line 32 when the latch signal does not arrive. At this time, the format discriminating means 60 uses the switch means (51, 5).
5) is operated, whereby the data taken in from the bus line 32 is directly PLL-converted without conversion of the format.
It is sent to the circuit 42.

Thus, according to the above-mentioned PLL control device, the PLL circuit 4
In both cases, when the data having the first format dedicated to the data 2 arrives and the data having the second format different from the dedicated format arrives, the PLL circuit conventionally used. 42
Can be used to allow the PLL circuit 42 to be controlled even by data having a format different from its dedicated format.

G Embodiment One embodiment of the present invention will be described in detail below with reference to the drawings. FIG. 2 shows the entire structure of the television receiver, which is obtained in the tuner circuit section 2 which is integrated into an IC through the antenna 1 as shown in FIG. By supplying the intermediate frequency signal to the intermediate frequency circuit section 3 having the intermediate frequency processor configuration and supplying the video signal obtained at the output terminal thereof to the video circuit section 4 having the video signal processor configuration, the RGB signal obtained at the output terminal thereof. The cathode ray tube 5
Supply to. Further, the audio signal SA obtained at the output terminal of the intermediate frequency circuit section 3 is given to the audio circuit 6, and its audio output is supplied to the speaker 7.

Here, each circuit unit is coupled to the bus line 32 of the CPU 31, and is controlled by the CPU 31 as a whole.

An adjusting terminal 35 is connected to the bus line 32, and an adjusting device 36 having, for example, a computer configuration is connected to the adjusting terminal 35 at the time of factory shipment, and each circuit unit is based on the adjusting operation data supplied from the adjusting device 36. Can be set to a predetermined adjustment state.

In the configuration of FIG. 2, the bus line 32 of the CPU 31 is composed of an I ² C bus. The I ² C bus has a data line and a clock line, and the data line and the clock line are commonly used by the respective circuit parts 2, 3, 4, and 6 to exchange data with the CPU 31. Thus, under the control of the CPU 31, the bus line 32
The circuit part connected to is controlled as a whole.

In the data line of the bus line 32 which is the I ² C bus, the data having the format shown in FIG.
31 is transferred to each circuit portion. That is, the CPU 31
The address data D2 (comprising 8 bits) attached to the device to which the data is to be transferred is transmitted following the start bit D1, and the answer signal D3 of 1 bit is received from the device. Subsequently, data consisting of 8 bytes of data and 1 byte of 1-bit answer signal for 3 bytes in succession is transferred, thus ending the transfer of data to the device designated by the address data D2. It is designed to do.

When the data having the format shown in FIG. 3 is sent from the CPU 31 to the bus line 32, the address data D2 included in the sent data is taken into the device to which the data is assigned, whereby each circuit portion is loaded. On the other hand, using the bus line 32 provided in common, data for a plurality of devices are sequentially transferred in a self-divided manner.

In addition to the above configuration, the PLL circuit 1 of the tuner circuit unit 2
As shown in FIG. 1, a tuner interface circuit 41 composed of an IC is provided between the bus line 32 and the bus line 32, and data of the bus line 32 is transferred via the tuner interface circuit 41. , PLL circuit 42, band switching circuit 43, AGC voltage generation circuit 4
4, supplied to the AGC detection circuit 45.

Here, the band switching circuit 43 fetches band switching data from the bus line 32 via the tuner interface circuit 41, and the tuner is selected for the band to which the selected channel belongs (that is, VHF low band or high band, UHF band). The resonance constant of the resonance circuit provided in the tuner is changed and controlled so as to exhibit a predetermined frequency characteristic.

Further, the AGC detection circuit 45 detects the signal level of the intermediate frequency signal obtained at the output side of the tuner, passes through the tuner interface circuit 41, and further the bus line 32.
To the CPU 31 via. At this time, the CPU 31
Sends AGC voltage control data to the bus line 32. This AGC voltage control data is supplied to the AGC voltage generation circuit 44 via the tuner interface circuit 41, and this AGC voltage generation circuit 44 generates an AGC voltage to be fed back at the input terminal side of the tuner.

The interface circuit 41 for the tuner has a PLL control circuit 50, and connects the bus line 32 to the memory circuit 52 via the input terminals T1 to T3 of the PLL control circuit 50 and further via the switch circuit 51. Once the data is taken into the memory circuit 52, the processing in the interface circuit 41 for the tuner is executed based on the taken data. When data is transferred from the tuner interface circuit 41 to the CPU 31, the data is temporarily taken into the memory circuit 52 and then the data is transferred to the CPU 3 via the bus line 32.
Send to 1.

In the case of this embodiment, the bus line 32 to the memory circuit 52
As described above with reference to FIG. 3, the data taken in by the data has a format peculiar to the I ² C bus, and its address data D2 is read by the timing control circuit 53, and each circuit 42, 43, 44, Timing signals AD1, AD2, AD3, AD4 corresponding to 45 are generated. The timing signal AD1 is supplied to the format conversion circuit 5
4 and the data stored in the memory circuit 52 is taken into the format conversion circuit 54 when the timing signal AD1 is supplied, and the PLL circuit 42 can operate in response to the dedicated format, that is, the first format.
Convert to format data of. Thus, the data D1 obtained by conversion in the format conversion circuit 54
Is supplied to the PLL circuit 42 from the tuner interface circuit 41 through the switch circuit 55.

Similarly, the address of the data fetched into the memory circuit 52 is the band switching circuit 43 and the AGC voltage generating circuit 4.
4, when the AGC detection circuit 45, the timing control circuit 53, the timing signal AD2, AD3, AD
4 is supplied to the band switching control circuit 49, the digital / analog conversion circuit 56, and the analog / digital conversion circuit 57, and the corresponding data is supplied from the memory circuit 52 to the band switching circuit 43 and the AGC voltage generation circuit 44.
Alternatively, the detection signal detected by the AGC detection circuit 45 is taken into the memory circuit 52 and transferred to the bus line 32.

Timing control circuit 53 and CP of PLL control circuit 50
The vertical synchronizing signal VSYNC generated from the video signal processor 4 (FIG. 2) is applied to U31, and the CP is controlled while the received video signal is in the vertical synchronizing period.
Data is transferred from the U31 to the tuner interface circuit 41 via the bus line 32, and in synchronization with this, the timing control circuit 53 causes the timing signal AD1.
By sending AD4 to AD4, each circuit of the tuner circuit unit 2 executes the data fetching operation or the data sending operation in synchronization with the vertical synchronizing signal VSYNC, thus controlling each circuit of the tuner circuit unit 2. , Can be executed during the vertical synchronization section. As a result, the tuner circuit unit 2 can prevent an unnecessary beat signal component from being mixed in while the minute video signal is being processed.

In addition to the above configuration, the tuner interface circuit 41 has a format determining circuit 60, and the PLL circuit 4
2 is supplied from the bus line 32, the data of a dedicated format for which the 2 can be operated in response to this is judged and the format is directly converted into the PLL circuit 42 without conversion processing.
To be able to supply.

The format discrimination circuit 60 divides the oscillation output pulse to the oscillation circuit 61 by the frequency divider 62, and counts the divided output pulse by the counter 63. Counter 63
Is connected to the latch line LAT that constitutes the bus line 32, and when a latch signal arrives from the latch line LAT, the latch signal is received by the count enable terminal to start the counting operation. Here, the counter 63 is set so as to send out the carrier signal in a time shorter than the rising width of the latch signal coming from the latch line LAT, and generates the switching control signal SWC based on the carrier signal, and the switch control signal SWC is generated. Give to.

When the switching control signal SWC is not generated, the switch circuit 51 inputs the signals input from the data line DAL, the clock line CLK, and the latch signal line LAT through the input terminals T1, T2, and T3 to the memory circuit 52 through the contact a. To do. At this time, the switch circuit 55 similarly supplies the conversion output D1 of the format conversion circuit 54 to the PLL circuit 42 through the contact a.

On the other hand, when the switching control signal SWC is generated, the switch circuits 51 and 55 switch from the contact a side to the contact b side, whereby the signals input through the input terminals T1, T2, T3 are switched. Are sequentially transmitted to the PLL circuit 42.

In the above configuration, when the I ² C bus is used as the bus line 32, the bus line 32 transfers the data using the data line DAL and the clock line CLK, and accordingly, the tuner interface circuit 41. The data transferred to the second transfer terminal has a second format that the PLL circuit 42 cannot operate in response to.

In this state, since the latch signal does not arrive at the latch signal line LAT, the format discriminating circuit 60 discriminates this. That is, the counter 63 maintains the state in which the switching control signal SWC is not generated by not starting the counting operation. Accordingly, the switch circuits 51 and 55 have the contact a.
, So that the data line DAL and the clock line C are connected through the input terminals T1 and T2.
The data and clock signals coming from LK are stored in the memory circuit 52.

At this time, the data stored in the memory circuit 52 is converted into a second format in which the PLL circuit 42 can operate in response to the format conversion circuit 54, and then supplied to the PLL circuit 42 through the switch circuit 55.

Thus, the PLL control circuit 50 uses the bus line 32 to
When the data of the second format in which the PLL circuit 42 cannot operate in response is received, it can be operated in response to the second data.
By converting the data into the above format and supplying it to the PLL circuit 42, the PLL circuit 42 can be applied as it is even to a bus system using data having different formats.

In this state, other circuits that configure the tuner circuit unit 2 using the data stored in the memory circuit 52,
That is, the band switching circuit 43 and the AGC voltage generating circuit 4
4. A system capable of controlling the AGC detection circuit 45, and thus controlled by a common CPU using a bus line commonly provided for many devices, such as an I ² C bus. The PLL circuit 42 can be adapted.

On the other hand, when data having a dedicated format arrives at the PLL circuit 42 through the bus line 32 as described above with reference to FIG.
When a latch signal arrives at the input terminal T3 from AT (FIG. 5), the counter 6 of the format discrimination circuit 60 is
3 counts and generates a switching control signal SWC.

At this time, the switch circuits 51 and 55 are connected to the input terminal T1,
The data arriving from T2 and T3 can be directly sent to the PLL circuit 42, and accordingly, also in this case, the PLL circuit 42 can be operated in response.

Therefore, if the PLL control circuit 50 having the configuration of FIG. 1 is used,
The PLL circuit 42 is configured not only when using a bus system that supplies control data having a dedicated format for the PLL circuit 42 but also when using a bus system which supplies control data having other formats. It is possible to have compatibility so that it can be shared without modification.

Incidentally, when the PLL circuit 42 is controlled by the control data having a dedicated format for the PLL circuit 42, another circuit of the tuner circuit section 2, that is, the band switching circuit 43,
The control of the AGC voltage generation circuit 44 and the AGC detection circuit 45 is executed using dedicated control circuits.

In the above, the case where the present invention is applied to the PLL circuit of the television tuner circuit is described, but the applicable range is not limited to this, and the point is to control the frequency division ratio of the programmable frequency divider. It can be widely applied to a PLL circuit adapted to control the frequency of the oscillation output.

H Effect of the Invention As described above, according to the present invention, the PLL circuit is not only operated in response to control data having a dedicated format, but is also operated in response to control data having another format different from the dedicated format. As a result, the PLL circuit can be easily adapted to a system having a bus line using the data of the different format.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a PLL control device according to the present invention, FIG. 2 is a block diagram showing a configuration of a television receiver using the PLL control device of FIG. 1, and FIG. FIG. 4 is a schematic diagram showing the format of data transferred through the bus line in the figure, FIG. 4 is a block diagram showing a conventional television receiver, and FIG. 5 is a schematic diagram showing the structure of the bus line 13. 2 ... China circuit part, 11 ... PLL circuit, 31 ...
CPU, 32 ... Bus line, 41 ... China interface circuit, 42 ... PLL circuit, 43 ... Band switching circuit, 44 ... AGC voltage generation circuit, 45 ... A
GC detection circuit, 51, 55 ... Switch circuit, 52 ...
Memory circuit, 53 ... Timing control circuit, 54 ... Format conversion circuit, 49 ... Band switching control circuit, 5
6 ... Digital / Analog circuit, 57 ... Analog /
Digital circuit, 60 ... Format determination circuit.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Kenichiro Kumamoto Inventor Kenichiro 6-35 Kita-Shinagawa, Shinagawa-ku, Tokyo Within Sony Corporation (56) References JP-A-58-87944 (JP, A) JP-A-SHO 57-39613 (JP, A) JP-A-56-61838 (JP, A) JP-A-58-136128 (JP, A)

Claims (2)

[Claims] 1. An input terminal connected to a bus line composed of a data line, a clock line, and a latch line, and a PLL circuit which controls a frequency division ratio of a programmable frequency divider in response to data of a first format. , Connected to the input terminal corresponding to the latch line,
When the data supplied from the bus line has a format determining means for determining whether the data supplied from the bus line has the first format or a second format different from the first format. A memory circuit for storing the data and a format of output data of the memory circuit are stored in the second circuit.
That the data supplied from the bus line is the first format, which is controlled by the format conversion circuit for converting and outputting the format from the first format to the first format, and the determination output of the format determining means. When the discrimination output is obtained, the data of the input terminal is directly sent to the PLL circuit,
Alternatively, when a discrimination output representing the second format is obtained, the data of the input terminal is input to the memory circuit and the output data obtained by being converted into the first format in the format conversion circuit is obtained. And a switch means for sending to the PLL circuit. 2. A timing control circuit for receiving a vertical synchronizing signal of a television signal is inserted on the output side of the format converting circuit, and the output of the format converting circuit is passed through the switch means during the vertical synchronizing period. P above
The first aspect of the present invention is configured to supply to the LL circuit.
Item 2. The PLL control device according to the item.