JPH0658998A - Semiconductor integrated circuit and designing method therefor - Google Patents

Abstract

PURPOSE:To perform power supply current test with reduced number of input signals while fixing the input logics of all macrocells without increasing the number of signal pads. CONSTITUTION:A signal pad 12 is connected with a control circuit 5 provided in a basic cell region 3. The control circuit 5 includes a plurality of registers 15 each comprising basic cells. The plurality of registers 15 form a shift register. Test mode signal lines 6 and control signal lines 7 are wired, respectively, from the control circuit 5 and the register 15 to the basic cells in order to transmit test mode signals and test data. The test mode signal allows power supply current test and fixing of logic is performed at each macrocell based on the test data.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit and a method for designing the same, and more particularly to a master structure of a CMOS gate array, which is one of the test items of the CMOS gate array and which can easily carry out a power supply current test, The present invention relates to a macro cell structure and a layout method.

[0002]

2. Description of the Related Art FIG. 17 shows a master structure of a conventional CMOS gate array. The master cell 1 of the CMOS gate array has a basic cell region 3 for constructing a logic circuit.
And an input / output buffer area 2 surrounding this.

A basic cell row 4 is formed in the basic cell region 3, and a VDD potential and a GND potential are applied to each basic cell row 4 by internal wirings 8 and 9, respectively. Internal wiring 8 and 9 are V
Power supply pads 10 and 11 for applying a DD potential and a GND potential
Are connected.

A signal is externally applied to each of the basic cells in each of the basic cell rows 4 via the signal pad 12.

FIG. 18 is an enlarged view of a part of the basic cell array 4. In the basic cell column 4, a Pch transistor region 13 and an Nch transistor region 14 necessary for constructing a logic circuit are formed.

In FIG. 19, 2N is shown as an example of a macro cell structure.
An AND logic circuit 30 is shown. This can be expanded to the transistor level as shown in FIG. Such a macro cell has the Pch transistor region 1 of the basic cell row 4.
3 and Nch transistor region 14. In FIG. 21, the 2NAND logic circuit 30 is Pc.
h transistor region 13 and Nch transistor region 1
4 shows a macrocell layout diagram configured in FIG.

FIG. 22 shows a conceptual diagram in which various macro cells are arranged in the basic cell row 4 provided on the chip 1 and connected to the internal wirings 8 and 9. FIG. 22 shows 2N
AND logic circuits 30a and 30b and inverter 19a,
The state where 19b is connected is illustrated.

As a method of testing the CMOS gate array configured as described above, the logic state of the internal circuit is fixed and the potential between the VDD potential and the GND potential (hereinafter referred to as "VDD / GN").
There is a power supply current test method for measuring the current flowing in the “D”).

The principle of this power supply current test method will be described with reference to FIGS. 23 to 25 by taking the 2NAND circuit 30 as an example. The inputs A and B are given to the input terminals 58 and 59 of the 2NAND circuit 30, respectively, and the output C from the output terminal 60.
Is obtained.

First, consider the case where the output terminal 60 of the 2NAND circuit 30 is a good product which is not short-circuited to either the VDD potential or the GND potential as shown in FIG.
In this case, the characteristic of the CMOS circuit is VDD / GN.
The current Iddq does not flow between D. That is, the input terminals 58 and 5
Input 9 to A, B (logical value "1" or "0")
Even if is given, if any of the Pch transistors 61 and 62 is turned on, the Nch transistors 63 and 64 are turned on.
Is turned off and the output terminal 60 is not connected to the GND potential. When both Pch transistors 61 and 62 are turned off, the output terminal 60 is not connected to the VDD potential.
This is summarized in Table 1 as a correspondence table of the logical state of the non-defective input / output terminals of the 2NAND circuit 30 and the current Iddq flowing between VDD / GND.

[0011]

[Table 1]

However, in a defective product, as shown in FIG. 24, for example, at least one of the Pch transistors 61 and 62 is short-circuited, so that the output terminal 60 may be short-circuited with the internal wiring 8. In this case, the inputs A and B applied to the input terminals 58 and 59 are both "1".
In the logic state of, Nch transistors 63 and 64 are turned on
Since the output terminal 60 is also connected to the GND potential, V
The current Iddq will flow between DD and GND ('1' fixation failure). This is summarized in Table 2 as a correspondence table of the logical state of the input / output terminal of the defective state of the 2NAND circuit 30 and the current Iddq flowing between VDD / GND.

[0013]

[Table 2]

Further, as shown in FIG. 25, the output terminal 60 may be short-circuited with the internal wiring 9 by short-circuiting both the Nch transistors 63 and 64. In this case, when at least one of the inputs A and B applied to the input terminals 58 and 59 is in the logic state of "0", P
Since the ch transistors 61 and 62 are turned on and the output terminal 60 is also connected to the VDD potential, the current Iddq flows between VDD / GND ('0' fixation failure). This is summarized in Table 3 as a correspondence table of the logical state of the input / output terminal of the defective state of the 2NAND circuit 30 and the current Iddq flowing between VDD / GND.

[0015]

[Table 3]

Therefore, as shown in Tables 1 to 3,
Even if the logic states of inputs A and B are both fixed to "0",
Even if both are fixed to “1”, if the current Iddq does not flow between VDD / GND, the 2NAND circuit 30 can be determined as a good product. If the current Iddq flows, it can be determined that the product is defective.

Utilizing this principle, when measuring the power supply current of the CMOS gate array, the logic states of the input terminals of the various macro cells mounted are fixed under some conditions, and VD
Measuring the current flowing between D / GND is one of the very important test items.

To perform this test in a conventional CMOS gate array having the master structure illustrated in FIG. 17, first, a logic simulated input signal is input to the signal pad 12 on the master chip 1 to determine the logic state of the internal circuit. Input (logical state). This input signal is
All the logic states of the input terminals of the mounted macro cells to be tested (for example, the inverters 19 and 2 NAND circuit 30) are fixed to "1" or "0". Then, after fixing the logic state, the current flowing between VDD / GND is measured.

These operations are repeated at least once for all the input terminals of the mounted macro cell until they are fixed to "1" and "0".

[0020]

However, in recent years, the degree of integration has been improved even with the same chip size due to the improvement of the fine technology of the semiconductor process of the semiconductor integrated circuit device, and particularly in the CMOS gate array, the number of macro cells that can be mounted has greatly increased. It was Therefore, the number of input / output terminals of the macro cell mounted on one gate array reaches hundreds of thousands.

On the other hand, when performing the power supply current test, it is necessary to apply a predetermined input signal to the signal pad to fix the logic state of the input terminal of the specific internal macro cell. In other words, in order to fix the logic states of the input terminals of all the macro cells, many combinations of input signals are required, and the signals to be input become redundant, which requires a considerable measurement time.

In addition, the size of the semiconductor integrated circuit device itself does not become so large, even though the number of macro cells has greatly increased. Therefore, the number of signal pads (external input / output terminals) is at most about 1000 pads due to various problems such as testing and assembly. Therefore, due to the limited number of signal pads, there are macro cells in which the logic of the input terminal cannot be fixed only by an external input signal, and there is a possibility that some macro cells may leak from the power supply current test. There was a point.

The present invention has been made to solve the above problems, and controls the input terminals of all mounted macro cells with a small number of input signals without increasing the number of signal pads (fixed logic). Then, it is an object of the present invention to obtain a semiconductor integrated circuit and a designing method thereof which can easily perform a power supply current test of a CMOS gate array in a short time.

[0024]

SUMMARY OF THE INVENTION A semiconductor integrated circuit according to the present invention is a logic fixing means for fixing an input logic of an logic circuit by interposing an input terminal, a logic circuit, and the input terminal and the logic circuit. And a macro cell having. This macro cell is a target of a power supply current test for measuring the current consumed while fixing the logic of the input of the logic circuit. Further, the semiconductor device further includes a control circuit for giving to the macro cell a test mode signal for controlling whether or not to perform a power supply current test, and test data for determining the logic fixed by the logic fixing means.

Preferably, the macro cell further has an open / short circuit controlled by a test mode signal. The open / short circuit transmits the output of the logic circuit of the macro cell to the next stage when the power supply current test is not performed, and transmits the output of the logic circuit of the macro cell to the next stage when the power supply current test is performed. Do no action.

The semiconductor integrated circuit designing method according to the present invention lays out macro cells in a master structure. Here, the macro cell includes an input terminal, a logic circuit,
It has a logic fixing means interposed between the input terminal and the logic circuit to fix the logic of the input of the logic circuit, and is the target of the power supply current test. Further, the master structure has a plurality of control signal lines for transmitting test data that determines the logic to which the input of the logic circuit is fixed. The power supply current test is a test for measuring the current consumed after fixing the logic of the input of the logic circuit.

The method of designing this semiconductor integrated circuit is as follows:
(A) a step of performing a logic simulation on the macro cell to extract the logic state of the input terminal; (b) a step of obtaining a power supply current measurement condition file; and (c) a logic state extracted by the step (a). A step of comparing the power supply current measurement condition file obtained in step (b) and collecting macro cells that do not cause a logic state collision even if inputs are fixed to the same logic to obtain a predetermined group; (D) laying out the macro cells belonging to the same predetermined group so that the logic fixing means included in the macro cells belonging to the same predetermined group are connected to the same control signal line. Here, the power supply current measurement condition file is set according to the function of the macro cell, and specifies the condition for performing the power supply current test.

Preferably, (e) the method further comprises the step of adding an open / short circuit to the macro cell in the preceding stage of the macro cell which does not belong to the predetermined group. Here, the open / short circuit transmits the output of the logic circuit of the macro cell to the next-stage macro cell when the power supply current test is not performed, and outputs the output of the logic circuit of the macro cell when the power supply current test is performed. Is not transmitted to the next-stage macro cell.

[0029]

The logic fixing means of the present invention individually fixes the logic state of the input of the logic circuit for each macro cell. The control circuit controls whether or not the logic state is fixed by the logic fixing means and the type of the logic state. The open / short circuit avoids collision of logic states when fixing the logic states.

Since the test data for determining the fixing of the logic state is extracted based on the logic simulation of the macro cell, it is possible to obtain in advance information about in which macro cell there is a possibility of the logic state collision. Yes, there is no redundant data.

[0031]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows an embodiment of a master structure of a CMOS gate array according to the present invention. The master chip 100 of the CMOS gate array is provided with a basic cell area 3 for constructing a logic circuit and an input / output buffer area 2 surrounding the basic cell area 3. A basic cell row 4 is formed in the basic cell region 3, and V is provided in each of the basic cell rows 4.
Internal wiring 8 for applying the DD potential and the GND potential,
9 is laid and the power supply pads 10 and 1 connected to these
1 is provided. A large number of signal pads (including wiring) 12 which are external input / output terminals for applying signals to each of the basic cell rows 4 from the outside are arranged between the power supply pads 10 and 11.

The signal pad (including wiring) 12 is connected to the control circuit 5 provided in the basic cell region 3. The control circuit 5 includes a plurality of registers 15 constructed from basic cells. These multiple registers 1
Reference numeral 5 forms a shift register.

From the control circuit 5, the test mode signal line 6
However, the control signal line 7 is wired from each of the registers 15 to the basic cell.

FIG. 2 shows the enlarged gate region of the basic cell row 4. The Pch transistor region 13 required for constructing the logic circuit and the Nch transistor region 14 required for constructing the logic circuit constitute the basic cell row 4 as shown in FIG. Here, the structure in which the test mode signal line 6 and the control signal line 7 are pre-wired for each of the four Pch transistors and Nch transistors (4 gates) is illustrated.

FIG. 3 shows the details of the control circuit 5. A terminal 17 to which a clock signal CL for operating the shift register is input is connected to all the registers 15 configuring the control circuit 5. Further, the test data Sn given to the register 15 is inputted to the terminal 16. Test data S
The content of n is supplied to the basic cell row 4 via the control signal line 7, and fixes the logic of the input terminal of the macro cell as described later.

A test mode signal R for controlling whether to perform a test or a normal operation is applied to the terminal 18. The test mode signal R is supplied to the basic cell column 4 via the test mode signal line 6. Each of these terminals is connected to the signal pad 12 and serves as an external input terminal.

In the present invention, means for fixing the input terminal of the macro cell to a predetermined logic is provided for each macro cell based on the test data Sn and under the control of the test mode signal R. This will be described by taking the inverter 19 as an example in FIGS.

FIG. 4 shows a block diagram of a macro cell including the inverter 19. The potential fixing circuit 21 is the inverter 19
, The logic input A, the fixed data S which is a unit forming the test data Sn, and the test mode signal R are received at the terminals 35, 36 and 37, respectively. The output is given as the input of the inverter 19, and the output C is obtained as the output of the inverter 19.

FIG. 5 shows a diagram in which the macro cell is developed at the transistor level. The potential fixing circuit 21 includes Nch transistors 23a, 2 that receive the test mode signal R in common.
3b, and an Nch transistor 24 and a Pch transistor 25 that commonly receive the fixed data S. These transistors 23a, 24, 25, 23b are arranged in this order from the internal wiring 8 (VDD potential) to the internal wiring 9 (GND potential).
Potential) in series.

The logic input A is applied to the connection point where the transistors 24 and 25 are connected in series. On the other hand, the input of the inverter 19 is connected to this connection point.

When the macro cell is operated normally (potential fixed circuit disconnection mode), the test mode signal R is set to "0" and the transistors 23a and 23b are turned off.
Then, regardless of the value of the fixed data S, the logical input A may be given to the input of the inverter 19.

On the other hand, when the power supply current test is performed on this macro cell (potential fixed mode), the test mode signal R is set to "1". As a result, the transistors 23a,
Since 23b is turned on, when the value of the fixed data S is "1", the transistor 24 is turned on and the transistor 25 is turned on.
After FF, the input of the inverter 19 is fixed to the VDD potential. Alternatively, when the value of the fixed data S is "0", the transistor 24 is turned off and the transistor 25 is turned on, so that the input of the inverter 19 is fixed to the GND potential.

By thus providing the potential fixing circuit 21, a power supply current test for detecting a "0" fixing defect or a "1" fixing defect can be executed. Moreover, since the 1-bit fixed data SS is required to fix the logic state of the input terminal of one macro cell, the logic state of the input terminal of one macro cell must be determined unless the logic states of all external terminals are determined as in the conventional case. There is no such thing as being unable to fix the state. Therefore, less data is needed to fix the logic state.

Table 4 shows the expected state of a non-defective product as an inverter power supply current measurement condition file. The input A in the normal operation is also shown for reference so that there is no contradiction in the logic state in the fixed potential mode.

[0046]

[Table 4]

By creating such a file for each macro cell, it is possible to understand what control signal can be used to perform the power supply current test, and as will be described later, measurement leakage may occur during macro cell layout. Can be prevented.

Depending on the logic of the logic input A, the logic of the input of the inverter 19 fixed by the potential fixing circuit 21 may be different. This is a case where the output logic of the preceding macro cell that determines the logic of the logic input A and the logic that should fix the input of the test target macro cell collide (do not match).
In such a case, it is necessary to cut off the output of the preceding macro cell in the potential fixing mode. In other words, in order to avoid the collision of the logic states in the next stage, it may be necessary to provide the signal transmission means which is opened / closed by the test mode signal R as the output means of the macro cell.

In FIG. 6, this is shown by taking a macro cell provided with an inverter 19 as an example. An open / short circuit 26 is provided after the inverter 19, and its opening / closing is controlled by the test mode signal R.

FIG. 7 shows a diagram in which the macro cell shown in FIG. 6 is expanded to the transistor level. The open / short circuit 26 is composed of a Pch transistor 28, and the test mode signal R is input to its gate. One of the current electrodes of the Pch transistor 28 is connected to the output of the inverter 19.

When the test mode signal R is "1", the potential fixing circuit 21 is in the potential fixing mode as described above.
In the open / short circuit 26, the Pch transistor 28 is turned off (open mode for preventing the influence of the next stage), so that the collision of the logic states in the next stage can be avoided. When the test mode signal R is "0", the potential fixing circuit 21 is in the potential fixing circuit cut-off mode as described above, and the Pch transistor 28 in the open / short circuit 26 is turned on (normal operation short mode) to cause the inverter 19 to operate. The output can be transmitted to the next stage.

In this way, potential fixing circuits, cells with open / short circuits, and power supply current measuring condition files are prepared in advance for all macro cells. However, which of the macro cells needs the open / short circuit 26 can be determined by a macro cell layout method described later.

Similarly, even when the macro cell has the 2NAND circuit 30, the logic of the input terminal can be fixed by the fixed data S and the test mode signal R.

FIG. 8 shows a block diagram of a macro cell having the 2NAND circuit 30. The potential fixing circuit 32 is 2 NAN
In front of the D circuit 30, the logic inputs A, B, the fixed data S, and the test mode signal R are supplied to the terminals 38, 39, 3 respectively.
Received at 6,37. And the output is 2 NAND
An output C is provided as an input of the circuit 30 and an output of the 2NAND circuit 30 is obtained.

FIG. 9 shows a diagram in which the macro cell is expanded to the transistor level. The potential fixing circuit 32 includes Nch transistors 23a, 2 that receive the test mode signal R in common.
3b and Nch transistors 24a and 24b, which receive fixed data S in common, and Pch transistors 25a and 25.
b and. These transistors 23
a, 24a, 25a, and 23b are the internal wiring 8 (V
DD potential) to the internal wiring 9 (GND potential) in series. The transistors 24b and 25b are connected in series and then connected in parallel to the series connection of the transistors 24a and 25a.

The logic input A is the transistors 24a, 25
a is given to the connection point where it is connected in series. The logic input B is applied to the connection point where the transistors 24b and 25b are connected in series. 2 NANDs at these connection points
The inputs of the circuit 30 are connected.

When this macro cell is normally operated (potential fixed circuit disconnection mode), the test mode signal R is set to "0" and the transistors 23a and 23b are turned off.
2 NAND circuit 3 regardless of the value of fixed data S
The logical inputs A and B may be given to the 0 input.

On the other hand, when the power supply current test is performed on this macro cell (potential fixed mode), the test mode signal R is set to "1". As a result, the transistors 23a,
23b is turned on. When the value of the fixed data S is "1", the transistors 24a and 24b are turned on, the transistors 25a and 25b are turned off, and the 2NAND circuit 30
Both inputs are fixed to the VDD potential. Alternatively, when the value of the fixed data S is “0”, the transistor 24
a and 24b are OFF, and transistors 25a and 25b are O
N, the two inputs of the 2NAND circuit 30 are both fixed to the GND potential.

By thus providing the potential fixing circuit 32, it is possible to execute a power supply current test for detecting a "0" fixing defect or a "1" fixing defect. The fact that less data is required to fix the logic state is the same as when the potential fixing circuit 21 is used.

The expected state for a non-defective product is 2 NAND
Table 5 shows the power supply current measurement condition file. Inputs A and B in the normal operation are also shown for reference so that there is no contradiction in the logic state in the fixed potential mode.

[0061]

[Table 5]

The logic of the logic inputs A and B may differ from the logic of the input of the 2NAND circuit 30 fixed by the potential fixing circuit 32. In such a case, it is necessary to cut off the output of the preceding macro cell that determines the logic of the logic inputs A and B in the potential fixing mode. In other words,
In order to avoid the collision of the logic states in the next stage, it may be necessary to provide a signal transmission means that opens and closes by the test mode signal R as the output means of the macro cell.

In FIG. 10, this is shown by taking a macro cell provided with the 2NAND circuit 30 as an example. The open / short circuit 26 is provided after the 2NAND circuit 30, and its opening / closing is controlled by the test mode signal R.

FIG. 11 shows a diagram in which the macro cell shown in FIG. 10 is expanded to the transistor level. The open / short circuit 26 is composed of a Pch transistor 28, and the test mode signal R is input to its gate.
One side of the current electrode of the Pch transistor 28 is 2N
It is connected to the output of the AND circuit 30.

The operation of the open / short circuit 26 is shown in FIG.
The operation is the same as that described by using, and when the test mode signal R is “1”, the next-stage influence prevention open mode is
When it is '0', the normal operation short mode is entered, so in the potential fixing mode, collision of logic states in the next stage is avoided, and in the potential fixing circuit cutoff mode, the 2 NAND circuit 3
The output of 0 can be transmitted to the next stage.

FIG. 12 illustrates the layout of the above macro cell on the master structure. FIG. 12 corresponds to FIG. 22, and includes inverters 19a and 19b and 2 NANDs.
The circuits 30a and 30b are connected in the same logic state as in FIG.

Test data Sn and a test mode signal R are applied to the control circuit 5 via terminals 16 and 18, respectively. For convenience of explanation, registers constituting the control circuit 5 will be referred to as registers 15a, 15b, 15c, ... Control signal lines 7a, 7b, 7c, ... Are laid from the registers 15a, 15b, 15c ,.
On the other hand, test mode signal lines 6a, 6b, 6c, ... Are paired with the control signal lines 7a, 7b, 7c ,. The manner in which these control signal lines and test mode signal lines form a pair and are laid in the basic cell row 4 is as already shown in FIG. By obtaining such an arrangement as a master structure in advance, the macro cell and the test mode signal line 6 and the control signal line 7 can be arranged when the macro cell is laid out in this master structure without paying particular attention to the power supply current test. Connection is secured.

The control circuit 15 includes registers 15a, 15b,
Since it has a shift register consisting of 15c, ...
The test data Sn is arranged as an array of the fixed data S at the terminal 16
Will be given to. Therefore, it is possible to control the logical states of the input terminals of a large number of mounted macro cells from a small number of external terminals.

In the upper basic cell array 4, there are two NAND circuits 3 in which potential fixing circuits 32a and 21a are respectively placed in front.
0a, a macro cell including an inverter 19a, and a potential fixing circuit 21 in the lower basic cell row 4 respectively.
A macro cell including an inverter 19b in which b and 32b are placed in front and a NAND circuit 30b is provided respectively.

If there is no problem in controlling the inputs of a plurality of macro cells with the same logic, they are connected to the same test mode signal line 6 and control signal line 7. In FIG. 12, it is assumed that the macro cell including the 2NAND circuit 30a and the macro cell including the inverter 19b can be controlled by the same logic, and these macro cells are connected to the common test mode signal line 6a and control signal line 7a.

However, if there is a problem by controlling the inputs of a plurality of macro cells with the same logic, they are connected to the separate test mode signal line 6 and control signal line 7.
In FIG. 12, the macro cell including the 2NAND circuit 30b is
Since the macro cell including the inverter 19a receives the output of the macro cell including the inverter 19b, the macro cell including the inverter 19a has a different input logic state. Therefore, the test mode signal line 6b and the control signal line 7b are connected to the macro cell including the inverter 19a,
A test mode signal line 6c and a control signal line 7c are connected to the macro cell including the 2NAND circuit 30b.

By making the above connection, the power supply current test can be performed by setting the test mode signal R to "1" and supplying the test mode signal Sn when measuring the power supply current.

A method of measuring the power supply current test will be described with reference to the flowchart of FIG. First, a logic "1" is given to the terminal 18 as the test mode signal R, and a logic "1" is sent to the control terminal 37 (see FIGS. 4 and 8) of the voltage fixing circuits 21b and 32a via the control signal line 6a. Set to the fixed potential mode. Similarly, logic "1" is applied to the control terminal 37 of the voltage fixing circuit 21a via the control signal line 6b and to the control terminal 37 of the voltage fixing circuit 32b via the control signal line 6c. become.
(Step 50).

Next, the registers 15a, 15b, 15c, ...
In order to give the fixed data S in the shift register consisting of, the test data Sn is given to the terminal 16 (step 51). Here, the registers 15a, 15b, 15c, ...
'1', '1', as fixed data S for each
Since "0", ... Is given, "110 ..." is given as the test data Sn. However, since it is necessary to detect both the '0' fixed defect and the '1' fixed defect, it is necessary to separately provide "001 ..." As the test data Sn. How to extract the value of such fixed data S is determined in advance at the stage of laying out macro cells. The specific method will be described later.

The value of the test mode signal R is "1",
Since the value of the fixed data S is given, the logic of the input terminal of each macro cell is fixed according to the fixed data S as described with reference to FIGS. 5 and 9 (step 52).

The power supply current of each macrocell, that is, VD
Measure the current flowing between D / GND (Step 5)
3). As illustrated in the macro cell including the 2NAND circuit 30b, by fixing the logic state of the input terminal of the macro cell of the next stage, the output of the macro cell to which the connection that may cause the collision of the logic states occurs, An open / short circuit 26 is provided. Therefore, the power supply current test can be simultaneously performed on all macro cells, and the test time can be shortened.

If the power supply current is flowing, the test result is Fai.
If it is l, it is determined to be a defective product (step 5).
6). If the power supply current is not flowing, the test result is Pass
And proceeds to step 54.

If the test data Sn remains, steps 51 to 53 are repeated again, and if the power supply current still does not flow, it is judged as a good product (step 5).
5).

14 to 16 are flowcharts showing the layout method according to the present invention.

First, the logic state of the input of the logic circuit of each mounted macro cell is obtained from the logic simulation result (extraction of the logic state), and the power supply current measurement condition file corresponding to each macro cell (exemplified in Tables 4 and 5). Compared with the above), the mounted macro cells are grouped by grouping macro cells that do not cause a collision of logic states even if they are fixed with the same logic ('1', '0') (step 40).

Since the macro cells grouped in this way may fix the inputs of the logic circuits they have to the same logic state, the terminals 36 of the potential fixing circuit are connected to the same control signal line. The macro cell is laid out (step 41).

Macro cells that have already been laid out do not need to be laid out again. For the confirmation, the input state of each macro cell is collated with the input state of the power supply current measurement condition file, and if they match, the file is deleted (step 42).

In this way, if a macrocell of a certain group is laid out, it is checked whether or not another group of macrocells to be laid out remains (step 43). The layout procedure (steps 41 and 42) is repeated.

Even when the group does not remain in this way, there are cases where unassigned macro cells remain. The presence / absence can be confirmed by the presence / absence of the power supply current measurement condition file (step 44), whereby the macro cell leaking from the measurement can be eliminated.

The remaining unplaced macro cells (residual macro cells) are macro cells etc. for which a logic simulation result has been obtained that fixing the logic state of the input terminal causes a collision of the logic states. Therefore, an open / short circuit is added to the preceding macro cell so that the output from the preceding stage of this macro cell is not transmitted. That is, the macro cell with the open / short circuit is replaced (step 4).
5).

Then, the potential fixing circuit of the remaining macro cell is connected to the control signal line according to the power supply current measurement condition file,
Lay out (step 46).

With such a flow, the layout is completed (step 47).

Thereafter, the fixed data S is obtained according to the logic state of each laid out macro cell, and the test data S is obtained.
n is extracted (step 48), and the test data extraction is completed (step 49).

As described above, the layout as illustrated in FIG. 12 is performed, and the test mode signal R and the fixed data S given from the control circuit 5 are given to each macro cell to perform the power supply current test. You can

[0090]

As described above, according to the present invention, each macro cell has logic fixing means for fixing the input logic of each macro cell, and the test mode signal and test data for controlling the operation of the macro cell are provided. Obtained from the control circuit.
Therefore, the input logics of all macro cells can be fixed, and the input logics of the macro cells can be fixed with a small amount of test data.

Further, since the open / short circuit blocks the transmission of the signal to the next stage during the measurement of the power supply current test, it is possible to perform the measurement for all the macro cells at once.

Since the test data for determining the fixation of the logic state is extracted on the basis of the logic simulation for the macro cell, it does not become redundant data and the measurement time is shortened.

[Brief description of drawings]

FIG. 1 is a block diagram of a master structure of a CMOS gate array which is an embodiment of the present invention.

FIG. 2 is an enlarged view showing details of a basic cell row.

FIG. 3 is a block diagram showing details of a control circuit.

FIG. 4 is a block diagram of a macro cell including an inverter.

FIG. 5 is a circuit diagram of a macro cell including an inverter.

FIG. 6 is a block diagram of a macro cell including an inverter.

FIG. 7 is a circuit diagram of a macro cell including an inverter.

FIG. 8 is a block diagram of a macro cell including a 2NAND circuit.

FIG. 9 is a circuit diagram of a macro cell including a 2NAND circuit.

FIG. 10 is a block diagram of a macro cell including 2 NAND circuits.

FIG. 11 is a circuit diagram of a macro cell including a 2NAND circuit.

FIG. 12 is a configuration diagram showing an embodiment of the present invention.

FIG. 13 is a flowchart illustrating measurement of a power supply current test.

FIG. 14 is a flowchart of a layout method according to the present invention.

FIG. 15 is a flowchart of a layout method according to the present invention.

FIG. 16 is a flowchart of a layout method according to the present invention.

FIG. 17 is a block diagram of a master structure of a conventional CMOS gate array.

FIG. 18 is an enlarged view of a conventional basic cell array.

FIG. 19 is a block diagram of a conventional macro cell structure.

FIG. 20 is a circuit diagram of a conventional macro cell structure.

FIG. 21 is a configuration diagram of a conventional macro cell structure.

FIG. 22 is a configuration diagram showing a conventional technique.

FIG. 23 is a circuit diagram illustrating the principle of a power supply current test.

FIG. 24 is a circuit diagram illustrating the principle of a power supply current test.

FIG. 25 is a circuit diagram illustrating the principle of a power supply current test.

[Explanation of Codes] 5 Control Circuits 21, 21a, 21b, 32, 32a, 32b Voltage Fixing Circuit 26 Open / Short Circuit R Test Mode Signal Sn Test Data S Fixed Data

[Procedure amendment]

[Submission date] December 18, 1992

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be corrected] Claim 3

[Correction method] Change

[Correction content]

[Procedure Amendment 2]

[Document name to be corrected] Drawing

[Name of item to be corrected] Figure 1

[Correction method] Change

[Correction content]

[Figure 1]

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification number Office reference number FI technical display location H01L 27/118 21/82 27/04 T 8427-4M H03K 19/00 B 8941-5J 19/173 9383-5J 8225-4M H01L 21/82 T

Claims (4)

[Claims] 1. An input terminal of the logic circuit, comprising: an input terminal, a logic circuit, and logic fixing means interposed between the input terminal and the logic circuit for fixing the logic of the input of the logic circuit. The macro cell that is the target of the power supply current test for measuring the current consumed after fixing the logic of the, the test mode signal for controlling whether to perform the power supply current test, and the logic fixed by the logic fixing means. A test circuit for determining, and a control circuit for giving the macro cell to the macro cell,
A semiconductor integrated circuit including. 2. The macro cell further includes an open / short circuit controlled by the test mode signal, and the open / short circuit includes the logic circuit included in the macro cell when the power supply current test is not performed. 2. The semiconductor integrated circuit according to claim 1, wherein when the power supply current test is performed, the output of the above is transmitted to the next stage, and the output of the logic circuit of the macro cell is not transmitted to the next stage. 3. An input terminal, a logic circuit, and logic fixing means which is interposed between the input terminal and the logic circuit to fix the logic of the input of the logic circuit. The control circuit has a plurality of control signal lines for transmitting test data that determines the logic to which the input of the logic circuit is fixed, to the macro cell that is the target of the power supply current test for measuring the current consumed after fixing the input logic. A method of designing a semiconductor integrated circuit for laying out in a master structure, comprising: (a) performing a logic simulation on the macro cell to extract a logic state at an input of the logic circuit; and (b) having the macro cell. Set according to function,
A step of obtaining a power supply current measurement condition file that specifies conditions for performing the power supply current test; and (c) a logic state extracted in step (a) and a power supply current measurement condition file obtained in step (b). And a step of obtaining a predetermined group by grouping the macro cells that do not cause a logic state collision even if the inputs are fixed to the same logic, and (d) the macro cells belonging to the same predetermined group. Laying out the macro cells belonging to the same predetermined group so that the logic fixing means included in the same are connected to the same control signal line, and a method for designing a semiconductor integrated circuit. 4. (e) When the power supply current test is not performed on the macro cell in the preceding stage of the macro cell which does not belong to the predetermined group, the output of the logic circuit included in the macro cell in the preceding stage is applied to the predetermined group. When the power supply current test is performed, the open / short circuit is added to perform an operation of not transmitting the output of the logic circuit of the preceding macro cell to the macro cell not belonging to the predetermined group. The method for designing a semiconductor integrated circuit according to claim 3, further comprising a step.