JP2991994B2 - Semiconductor circuit system, inspection method of semiconductor integrated circuit, and method of generating inspection sequence - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an MT-CMOS semiconductor circuit system including a semiconductor integrated circuit on which MOS transistors having different thresholds are mounted, an inspection method of the semiconductor integrated circuit, and a method of generating the inspection sequence.

[0002]

2. Description of the Related Art In recent years, in order to reduce the size and increase the degree of integration of semiconductor devices, there has been a demand for lower power semiconductor integrated circuits.
To reduce the power, it is effective to reduce the power supply voltage. However, there is a problem that when the power supply voltage is reduced, the operation speed of the transistor is reduced. Therefore,
As one of the semiconductor integrated circuits constituted by the CMOS semiconductor devices, the MOS transistors mounted are a MOS transistor having a low threshold voltage (low threshold MOS transistor) and a MOS transistor having a high threshold voltage ( MT-CMOS (Multi-Threshold (Multi-Thre
Shold) CMOS) semiconductor integrated circuits have been proposed.

As an example of a conventionally proposed MT-CMOS semiconductor integrated circuit, there is a technique disclosed in, for example, IEICE: IEICE Technical Report ICD93-107 (1993-10). Less than,
A conventional MT-CMOS semiconductor integrated circuit will be described with reference to FIG.

FIG. 13 is an electric circuit diagram schematically showing a configuration of the MT-CMOS semiconductor integrated circuit, and a part of the configuration is extracted. As shown in the figure, a large number of low threshold transistors (hereinafter abbreviated as LVth-Tr) are provided between a power supply terminal 100 for supplying the operating voltage VDD and a ground terminal 101 for supplying the ground potential VGN. ) Are interposed. A p-channel high threshold transistor 91 (hereinafter abbreviated as HVth-Tr) is provided between the power supply terminal 100 and the logic gate 99, and an n-channel HV is provided between the logic gate 99 and the ground terminal 101.
th-Tr 92 is interposed. That is, since each of the transistors 93 to 96 in the logic gate 99 has a low threshold value, the operation speed is high and high-speed operation is possible. On the other hand, since the leakage current is large, there is a possibility that wasteful power consumption increases. Therefore, HVth-Tr 9 is applied between the logic gate 99 and the power supply terminal 100 and the ground terminal 101.
1, 92 are interposed.

The operation of the circuit shown in FIG. 1 will be specifically described below. Logic gate 99 and p-channel HVth-Tr 9
1 is a virtual power supply potential VDDV, and the potential of a node 98 between the logic gate 99 and the n-channel HVth-Tr 92 is a virtual ground potential VGNV.
By turning on the HVth-Tr 91 and 92 during the operation of the logic gate 99, a node 97 serving as a virtual power supply terminal is provided.
Charge is supplied to a node 98 serving as a virtual ground terminal, and L
The logic gate 99 composed of Vth-Tr 93 to 96
It operates at high speed. Conversely, H during standby
By turning off Vth-Tr 91, supply of voltage from the power supply terminal 100 to the logic gate 99 is cut off.
When the HVth-Tr 92 is turned off, the logic gate 99 is turned off.
Leakage current from the ground terminal 101 to the ground terminal 101 is suppressed. Therefore, the leakage from the power supply terminal 100 to the ground terminal 101 is kept very small.

[0006]

However, in the conventional MT-CMOS semiconductor integrated circuit, when each transistor fails, the following problems may occur. For example, it is assumed that the HVth-Trs 91 and 92 are not turned off due to a failure. In this case, when there is an operation command for the logic gate 99, H
Since Vth-Tr 91 and 92 are ON, the logic gate 99 operates normally. On the other hand, when there is a standby command for the logic gate 99, the HVth-Tr 91, 92 remain ON. That is, HVth-Tr 91, 92
Even if is not turned off due to a failure, each element in the logic gate 99 operates correctly,
It does not adversely affect the operation of. However, if the HVth-Trs 91 and 92 are not turned off during standby, the leakage current flowing from the power supply terminal 100 to the ground terminal 101 via the logic gate 99 increases. in this way,
If the leakage current during standby increases,
There is no point in providing Vth-Tr, and the advantage of the MT-CMOS semiconductor integrated circuit that high-speed operation is possible and power consumption is small cannot be exhibited.

However, in the conventional MT-CMOS semiconductor integrated circuit, such HVth-Tr 91, 92
Cannot detect a failure that does not turn off in response to a standby command, and thus cannot effectively prevent an increase in leakage off current.

[0008] The above problems are caused not only by the operation of the HVth-Tr, but also by the wiring and elements between the power supply terminal and the logic gate and the wiring and elements between the logic gate and the ground terminal and the members such as the elements. Also occurs when a short circuit occurs at

A first object of the present invention is to provide a conventional MT-CM
In the OS semiconductor integrated circuit, there is no means for distinguishing and detecting a fault in the logic circuit of the MT-CMOS semiconductor integrated circuit and a fault outside the logic circuit, that is, a fault due to an HVth-Tr operation failure or a wiring short. Focusing on the fact that the above-mentioned problems were inherent, and taking measures to distinguish and detect faults in the logic circuit and faults outside the logic circuit, a function capable of high-speed operation and low power consumption It is an object of the present invention to provide a semiconductor circuit system including an MT-CMOS semiconductor integrated circuit and a method for inspecting a semiconductor integrated circuit, which can surely exhibit the above.

A system for automatically generating a sequence for checking a logical fault of a current signal line is a conventional CMO.
It is intended for failure of only the output signal line or input signal line of the logic gate in the S semiconductor integrated circuit. Therefore, even if an attempt is made to check whether the logic circuit is normal or abnormal using the current test sequence generation system, it is not possible to distinguish between a state in which HVth-Tr should operate and a state in which HVth-Tr should not operate. Even if the test sequence generation system described above is used as it is, the test sequence in the logic circuit cannot be automatically generated.

A second object of the present invention is to provide a method for automatically generating a test sequence in a logic circuit while utilizing a currently used test method of a CMOS semiconductor integrated circuit.
An object of the present invention is to provide a method of generating a test sequence for a CMOS semiconductor integrated circuit.

[0012]

Means for Solving the Problems In order to achieve the first object, the means taken by the present invention is to provide a function for controlling the on / off of HVth-Tr in accordance with the type of a test signal. is there. Specifically, means relating to the semiconductor circuit system described in claims 1 to 8, and claim 9
To 11 relating to the method of inspecting a semiconductor integrated circuit.

According to a first aspect of the present invention, there is provided a semiconductor circuit system having inspection instruction means for issuing an instruction to inspect whether the semiconductor integrated circuit is normal or abnormal inside or outside the semiconductor integrated circuit. The semiconductor integrated circuit includes a first terminal for supplying a high-potential-side voltage, a second terminal for supplying a low-potential-side voltage, and a circuit between the first terminal and the second terminal. An intervening at least one logic circuit configured by arranging a plurality of low-threshold transistors, between at least one of the first terminal and the second terminal and the logic circuit; A high-threshold transistor for switching the logic circuit between an operating state and a standby state by switching on and off; a first terminal, a second terminal, a logic circuit, and a high-threshold transistor Tiger A logic circuit outside the wiring for connecting the register, upon receiving a test command from the test command means,
A state control unit that controls on / off of the high threshold transistor in accordance with the type of the inspection command.

This makes it possible to check the current when the high threshold transistor in the MT-CMOS semiconductor circuit system is turned on and off and the operating state of the logic circuit, and to determine whether a fault has occurred in the logic circuit and whether the logic circuit has been damaged. , That is, a failure due to a short circuit of the wiring outside the logic circuit or a malfunction of the high-threshold transistor can be distinguished and inspected.

According to a second aspect of the present invention, in the semiconductor circuit system according to the first aspect, when the state control unit receives a test command for the external logic circuit wiring and the high threshold transistor from the test command means, The high threshold transistor is controlled to be turned off.

Thus, when the current in the path between the first terminal and the second terminal is examined at the time of inspecting the wiring outside the logic circuit and the high-threshold transistor, it is possible to determine whether the wiring outside the logic circuit is short-circuited or high. It is possible to determine whether or not useless power is consumed due to a malfunction of the threshold value transistor. Therefore, by excluding a semiconductor integrated circuit in which wasteful power is consumed, a high leakage current in an off state can be obtained while a high speed operation in a logic circuit including low threshold transistors is ensured. The disadvantage of the threshold transistor can be reliably covered. That is, the function of the MT-CMOS semiconductor integrated circuit in which the low threshold transistor and the high threshold transistor are provided can be secured.

According to a third aspect of the present invention, in the semiconductor circuit system according to the second aspect, a plurality of the logic circuits are provided.
And the second terminal are shared by all of the logic circuits, and the state control unit controls the high threshold transistors connected to all of the logic circuits to be turned off. Things.

According to a fourth aspect of the present invention, in the semiconductor circuit system according to the second aspect, a plurality of the logic circuits are provided.
Terminal and the second terminal are shared by one or a plurality of logic circuits of all the logic circuits, and the state control unit causes the inspection command means to output the wiring outside the logic circuit and the height. When a test command for the threshold transistor is received, the high threshold transistor connected to the logic circuit between the common first terminal and the second terminal is controlled to be turned off.

According to the third or fourth aspect, even when the arrangement relationship between the first and second terminals and the logic circuit changes depending on the type of voltage, the type of logic circuit, and the like, the operation of the first aspect can be ensured. Will be obtained.

According to a fifth aspect of the present invention, in the semiconductor circuit system according to the first aspect, the high-threshold transistor is connected between the first terminal and the logic circuit and between the second terminal and the logic circuit. Respectively.

Thus, at the time of inspection, it is possible to check whether the logic circuit is disconnected from both the high-potential-side voltage and the low-potential-side voltage. Therefore, wasteful power consumption can be more reliably avoided.

According to a sixth aspect of the present invention, there is provided a semiconductor circuit system according to the second, third, fourth or fifth aspect, wherein the first terminal and the second terminal are connected to each other.
A current detecting means for detecting a current flowing between the terminals of the current detecting means, a storage means for storing in advance a set value for a pass / fail judgment with respect to a detection value of the current detecting means, Connected, at the time of the inspection, while the detection value of the current detection means is determined to be rejected when the detection value is equal to or more than the set value, while the detection value of the current detection means is determined to be passed when the detection value is less than the set value, Display means for displaying the result of the determination by the determination means.

As a result, it is possible to obtain an inspection apparatus capable of easily and quickly detecting a malfunction of the high threshold transistor in the MT-CMOS type semiconductor integrated circuit or a short circuit of the wiring outside the logic circuit.

According to a seventh aspect of the present invention, in the semiconductor circuit system according to the first aspect, when the state control unit receives a test command in the logic circuit from the test command means,
The high threshold transistor connected to the logic circuit to be inspected among the logic circuits is turned on.

This makes it possible to check whether the operation of the logic circuit is proper or not with the high threshold transistor turned on.

In a semiconductor circuit system according to an eighth aspect of the present invention, there is provided the semiconductor circuit system according to the seventh aspect, wherein: a means for inputting a test signal to the logic circuit; An expected value storage means for storing an expected value in advance; and a logic value of the output signal, which is connected to the expected value storage means, compares the logic value of the output signal from the logic circuit with the expected value, and performs the logic of the output signal at the time of the inspection. A determination unit that determines that the value is acceptable when the logical value of the output signal does not match the expected value when the value matches the expected value, and a display that displays a determination result of the determination unit when the logical value of the output signal does not match the expected value. Means.

Thus, an inspection apparatus capable of easily and quickly inspecting a malfunction in a logic circuit in an MT-CMOS semiconductor integrated circuit can be obtained.

According to a ninth aspect of the present invention, there is provided a method for testing a semiconductor integrated circuit, comprising: a first terminal for supplying a high-potential-side voltage; a second terminal for supplying a low-potential-side voltage; At least one logic circuit interposed between the terminal and the second terminal and configured by arranging a plurality of low-threshold transistors; and at least one of the first terminal and the second terminal. One of which is interposed between the logic circuit and
A high-threshold transistor for switching the logic circuit between an operation state and a standby state by switching on and off, and connection between the first terminal, the second terminal, the logic circuit, and the high-threshold transistor A method for inspecting a semiconductor integrated circuit, comprising: a wiring outside the logic circuit;
A second step of detecting a current flowing between the first terminal and the second terminal, and determining that the current value is a failure when the detected value is equal to or greater than a set value, while determining that the current value is less than the set value. A third step of determining a pass when

According to this method, when the logic circuit in the MT-CMOS semiconductor integrated circuit is on standby, a semiconductor integrated circuit in which useless current is generated due to a malfunction of the high-threshold transistor or a short circuit of wiring outside the logic circuit is surely rejected. Can be excluded. That is, only MT-CMOS semiconductor integrated circuits having good characteristics can be selected.

According to a tenth aspect of the present invention, in the semiconductor integrated circuit inspection method according to the ninth aspect, a plurality of the logic circuits are provided.
The first terminal and the second terminal are shared by all the logic circuits, and in the second step, the high threshold transistors connected to all the logic circuits are turned off. How to

According to an eleventh aspect of the present invention, in the semiconductor integrated circuit inspection method according to the ninth aspect, a plurality of the logic circuits are provided.
The first terminal and the second terminal are shared by one or a plurality of logic circuits of all the logic circuits, and in the second step, the common first terminal-
This is a method of turning off the high threshold transistor connected to the logic circuit between the second terminals.

According to the method of claim 10 or 11, the MT-
In a CMOS semiconductor integrated circuit, even when the arrangement relationship between the first and second terminals and the logic circuit changes depending on the type of voltage, the type of logic circuit, and the like, a faulty semiconductor integrated circuit is reliably detected and eliminated. It is possible to do.

In order to achieve the second object,
Means taken by the present invention is to add a description relating to the state of the wiring supplying the power supply voltage in addition to the conventional test sequence. Specifically, means for generating a test sequence for a semiconductor integrated circuit according to the twelfth to fourteenth aspects is provided.

According to a twelfth aspect of the present invention, there is provided a method for generating a test sequence for a semiconductor integrated circuit, comprising: a first terminal for supplying a high potential side voltage; a second terminal for supplying a low potential side voltage;
At least one logic circuit interposed between the first terminal and the second terminal and configured by arranging a number of elements including a plurality of low threshold transistors; A high threshold transistor interposed between at least one of the second terminals and the logic circuit for switching the logic circuit between an operating state and a standby state by switching on and off; An external logic circuit wiring connecting the first terminal, the second terminal, the logic circuit and the high threshold transistor, and a state control for outputting a control signal for controlling on / off of the high threshold transistor Generating a test sequence of a semiconductor integrated circuit having a portion, wherein a partial circuit relating to a connection state between the respective elements in a logic circuit to be tested out of the at least one logic circuit. And the first step in creating a predicate,
On the basis of the partial circuit description created in the first step, a second test sequence is created which includes a description of an input / output relationship for determining an appropriate state of operation in the logic circuit to be inspected. A step, in which the control signal output from the state control unit is in a mode in which the high threshold transistor connected to the logic circuit to be tested is turned on in the test sequence. And a third step of creating a new series and adding it to the test series created in the second step.

According to this method, the operation of the logic circuit in the MT-CMOS semiconductor integrated circuit can be checked only by adding a new sequence to the test sequence generated by the conventional CMOS semiconductor integrated circuit test method. It is possible to generate a test sequence that can be used for a test.

According to a thirteenth aspect of the present invention, in the method of generating a test sequence for a semiconductor integrated circuit according to the twelfth aspect, the high threshold transistor is connected to at least one of the first terminal and the second terminal. In the case where a plurality of high threshold transistors connected in parallel with each other between the logic circuit and a plurality of high threshold transistors connected in parallel are configured as high threshold transistors dedicated for inspection. In the third step, the control signal output from the state control unit turns on only the high-threshold transistor dedicated to inspection out of the plurality of high-threshold transistors connected in parallel. This is a method of creating a new series that becomes a mode.

According to a fourteenth aspect of the present invention, in the method for generating a test sequence for a semiconductor integrated circuit according to the twelfth aspect, the high-threshold transistor connected to the logic circuit to be tested includes a logic circuit test. The third step is such that the control signal input from the outside activates the logic circuit to be inspected in the third step. This is a method of creating a new series in a mode enabling the state and adding it to the test series created in the second step.

According to this method, an MT-CMO having a structure directly controlled by a control signal input from the outside.
Also for the S semiconductor integrated circuit, a test sequence for checking the operation of the logic circuit can be generated.

[0039]

BEST MODE FOR CARRYING OUT THE INVENTION

(First Embodiment) First, a first embodiment will be described. FIG. 1 shows an MT-CMOS according to the first embodiment.
It is an electric circuit diagram of a semiconductor circuit system.

The semiconductor integrated circuit 8 shown in FIG.
A plurality of logic blocks 7 constituted by CMOS semiconductor devices
a to 7x are provided. These logical blocks 7a to 7
x has a power supply terminal 1 for supplying the operating potential VDD.
Between 0 and the ground terminal 11 for supplying the ground potential VGN, logic circuits 5a to 5x each including a large number of low threshold transistors (LVth-Tr) are provided. A p-channel high-threshold transistor, pH, is provided between each of the logic circuits 5a to 5x and the power supply terminal 10.
Vth-Tr 1a to 1x, and nHVth-Tr 2a to 2x which are n-channel type high threshold transistors are interposed between the logic circuits 5a to 5x and the ground terminal 11, respectively. Each pHVth-Tr 1a to 1x and each logic circuit 5a
The potential of the first nodes 3a to 3x between the logic nodes 5a to 5x is the virtual power supply potential VDDV, and the potential of the second nodes 4a to 4x between the nHVth-Tr 2a to 2x and the logic circuits 5a to 5x is the virtual ground. This is the potential VGNV. In addition, the semiconductor integrated circuit 8
Are members outside the logic circuits 5a to 5x, that is, each HVth-T
When a test signal Sdt for testing r and wiring is received, each of the logic circuits 5a to 5x in the logic blocks 7a to 7x to be tested is disconnected from the power supply terminal 10 and the ground terminal 11 to make a test. A state control unit 6 incorporating a control unit 6a is provided. The state control unit 6
A normal control unit 6b for controlling the operation of the LVth-Tr in the logic block 7a according to a normal control signal input from inside the semiconductor integrated circuit 8 is provided therein. That is, in the present embodiment, a common power supply terminal 10 and a common ground terminal 11 are provided for each of the logic blocks 7a to 7x, and the test control unit 6a in the state control unit 6 controls each of the logic blocks 7a during inspection. All pHVth within ~ 7x
Tr 1a to 1x and nHVth-Tr 2a to 2x are controlled to be simultaneously turned off. The normal control unit 6b controls the HVth-Trs to be turned on when the respective logic blocks 7a to 7x are operating, and to be turned off during the standby mode, according to the normal control signal.

The semiconductor integrated circuit 8 configured as described above
Will be described with reference to FIGS. 2 and 3. FIG.

FIG. 2 is a block diagram schematically showing a configuration of a tester 13 which is a semiconductor integrated circuit inspection apparatus used in each embodiment of the present invention. As shown in the figure, the tester 13 includes probes 14a and 14b for contacting both ends of a part of the semiconductor integrated circuit 8, and each probe 1
An ammeter 15 connected to 4a, 14b, a storage device 16 in which a set value is stored in advance, a determination circuit 17 for determining pass / fail, and a pass / fail indication based on a pass / fail signal of the determination circuit 17 is displayed. And a display device 18. When the semiconductor integrated circuit 8 is inspected, the probes 14a and 14b are applied to any part between the terminal 10 and the terminal 11, so that a failure of each HVth-Tr can be inspected. .

FIG. 3 is a flowchart showing the procedure of the inspection according to this embodiment. First, in step ST11, when the inspection signal Sdt is turned on, the test control unit 6a causes the pHVth-Tr 1 in each of the logic blocks 7a to 7x to be set.
a to 1x and nHVth-Tr2a to 2x are controlled to be turned off. That is, each pHVth-Tr 1a ~
If 1x and nHVth-Tr 2a to 2x are normally off, each of the logic circuits 5a to 5x should be in a standby state disconnected from the power supply terminal 10 and the ground terminal 11.

Next, in step ST12, the current in the path is measured. This may be performed on the power supply terminal 10 side or the ground terminal 11 side.

Next, in step ST13, the current (leak current value) when the inspection signal Sdt is in the OFF state.
It is determined whether or not the detected value Idt is smaller than a predetermined set value Is. If Idt <Is, it is determined to pass, and if Idt ≧ Is, it is determined to be reject. However, the set value Is is specifically set as follows.

That is, assuming that the current flowing in a normal state is I, the set value Is is set to Is = I + K1 (where K1 is a constant that allows for variations in characteristics in the manufacturing process). Then, the set value Is
Is stored in the storage device 16 in advance.

As described above, according to the present embodiment, MT
A determination as to whether a logic block in a CMOS semiconductor integrated circuit has shifted to a standby state during inspection, that is, MT
-Defective products resulting from "malfunction of high threshold transistor of CMOS semiconductor integrated circuit, short circuit of wiring, etc." can be effectively detected. However, the short-circuit of the wiring detected by this inspection refers to a short-circuit of the wiring outside the logic circuits 7a to 7x, for example, pHVth-Tr (for example, 1) connected to the same logic circuit (for example, 7a).
a) between the source-side terminal of nHV-Tr (for example, 2a) and the source-side terminal of nHV-Tr or each HVth-Tr in the case where HVth-Tr is provided in only one of them.
This is a short circuit between the source and the drain in Tr.

By eliminating defective products in such a manufacturing process, only MT-CMOS semiconductor integrated circuits having good characteristics can be selected and put on the market.

In the present embodiment, the MT-CMOS including a plurality of logic blocks constituted by MT-CMOS semiconductor devices is used.
Although the CMOS semiconductor integrated circuit has been described, the MT-C
Needless to say, the present invention can be similarly applied to an MT-CMOS semiconductor integrated circuit including only one logic block constituted by a MOS semiconductor device.

In this embodiment, the state control unit 6 is provided outside each of the logical blocks 7a to 7x. However, a state control unit may be provided in each of the logical blocks 7a to 7x.

In the present embodiment, the test signal Sdt, which is an input to the test control unit 6a of the state control unit 6, is configured to be directly supplied from outside the semiconductor integrated circuit 8, but the test signals Sdt of the logic blocks 7a to 7x are not supplied. The same effect can be obtained even if the configuration is made to generate internally. Further, in the present embodiment, the normal control signal is generated inside the semiconductor integrated circuit 8, but the normal control signal may be input from outside the semiconductor integrated circuit 8, that is, from outside the semiconductor chip.

(Second Embodiment) Next, a second embodiment will be described with reference to FIGS. FIG.
FIG. 5 is an electric circuit diagram schematically showing a configuration of the MT-CMOS semiconductor integrated circuit 21 according to the second embodiment, and FIG. 5 is a flowchart showing a procedure of inspection of the semiconductor integrated circuit.

The semiconductor integrated circuit 21 shown in FIG.
A plurality of logic blocks 7 constituted by CMOS semiconductor devices
a to 7x and a plurality of test signals Sdt1 to Sdti at the time of testing, and the pHVth in one or more logical blocks (hereinafter, referred to as a logical block subset) to be tested in the logical blocks 7a to 7x. -Tr and nHVth-Tr
Is provided with a state control unit 22 that controls to turn off the switch. However, the inspection signal Sdt1 is stored in the state control unit 22.
.. Sdti, a decoder 22b for receiving a normal control signal, and a selector 22c for selecting an output of each of the decoders 22a and 22b.
pHVth-T in the logical block subset to be inspected in the logical blocks 7a to 7x according to the combination of dti
It is configured to output a signal for turning off r and nHVth-Tr. The selector 22c is configured to select and output either the inspection signal or the normal control signal in accordance with a mode switching signal indicating the inspection mode or the normal control mode.

Further, for each of the logical blocks 7a to 7x,
Power supply terminals 10a to 10x and ground terminals 11a to 11x are provided. However, the configuration in each of the logical blocks 7a to 7x is the same as in the first embodiment.

Next, the configuration of the inspection apparatus is basically the same as the configuration shown in FIG. 2 in the first embodiment.
However, the current value is detected by bringing the two probes 14a and 14b shown in FIG. 2 into contact with an external pin or the like. The set value Is is set as Is = I + Kk (where Kk is a constant taking into account the variation in characteristics in the manufacturing process of each logic block). Further, it is assumed that the potential of each of the ground terminals 11a to 11x is 0.

Next, the inspection procedure will be described with reference to the flowchart of FIG.

First, in step ST 21, a combination of check signals specifying a logical block subset to be checked is input to the decoder 22 a of the state control unit 22. In this embodiment, it is assumed that the logical block 7a is specified. As a result, the logical block subset 7a to be inspected is
When the pHVth-Tr 1a or the nHVth-Tr 2a operates normally, the connection to the power terminal 10a or the ground terminal 11a is cut off and the device enters a standby state.

Next, in step ST22, the current value Idta in the logical block subset 7a is measured. However, the portion where the current value is measured is the power terminal 1
It may be either the 0a side or the ground terminal 11a side.

Next, in step ST23, it is determined whether or not the current value Idta detected in step ST22 is smaller than the set value Is. Then, if Idta <Is, it is determined to pass, while if Idta ≧ Is, it is determined to be reject.

When another logical block, such as the logical block 7x, is designated as the logical subset to be checked, the current value is measured in the same manner as described above, and the pHVth-Tr 1x or the logical block subset 7x is measured. nHVth-T
Check if r2x is working properly. That is, the current value Idtx is measured, and the detected current value Idtx is measured.
It is determined whether or not x is smaller than the set value Is. Then, if Idtx <Is, it is determined to be acceptable, while Idtx
If ≧ Is, it is determined to be rejected.

In the present embodiment, as in the first embodiment, it is possible to reliably determine whether the MT-CMOS semiconductor integrated circuit is normal or abnormal. In particular, there is an advantage that the pass / fail judgment can be reliably performed even when the power supply voltage is different for each logical block subset.

In this embodiment, each MT-CMOS
Although the power supply terminal 10 and the ground terminal 11 are provided one by one in each of the logic blocks 7a to 7x configured by the semiconductor device, a plurality of power supply terminals and the ground terminal may be provided in one logic block, for example, 7a. Even when a common power supply terminal and a common ground terminal are provided for a plurality of logical blocks belonging to the same logical block subset, the same effect as in the present embodiment can be obtained.

Further, in the present embodiment, the state control unit 22 is configured outside the logical blocks 7a to 7x, but may be configured in each logical block.

In this embodiment, the test signals Sdt1 to Sdti are supplied to the decoder 22a of the state control unit 22 from outside the semiconductor integrated circuit 8. However, the logic blocks 7a to 7x inside the semiconductor integrated circuit 8 are provided. It may be configured to be generated within. In the present embodiment, the normal control signal is supplied from outside the semiconductor integrated circuit 8. However, the normal control signal may be generated outside the semiconductor integrated circuit 8, that is, inside the semiconductor chip.

(Third Embodiment) Next, a third embodiment relating to a method for generating a test sequence for a semiconductor integrated circuit will be described. FIG. 6 is an electric circuit diagram showing a configuration of the MT-CMOS semiconductor integrated circuit 41 according to the present embodiment.

As shown in FIG. 6, the configuration of the semiconductor integrated circuit 41 is basically the same as that of the first embodiment shown in FIG.
Has the same configuration as the semiconductor integrated circuit 8 shown in FIG. In the present embodiment, the state control signal MODE is set to 1 when the logic circuit is inspected.
, A state control unit having a built-in test control unit 42a for controlling the entire logic circuit group 43 including the logic circuits 5a to 5x in the logic blocks 7a to 7x to be inspected so as to be connected to the power supply terminal 10 and the ground terminal 11 A portion 42 is provided. Here, in the present embodiment, the state control signal MO
When DE is 1, it means that the operation of the logic circuit group 43 is ON. It should be noted that the normal control unit 42b that controls the normal operation of the logic circuit group 43 according to the normal control signal is provided in the state control unit 42, as in the above embodiments.

FIG. 7 is a block circuit diagram showing an example of the configuration of the logic circuit group 43. As shown in FIG.
A flip-flop DFF, two AND circuits, an OR circuit, and an inverter INV are arranged as circuit elements between .about.D and the output pin OUT. And
The identification names, input pin names, output pin names, and wiring net names of the respective circuit elements are named as shown in FIG.

FIG. 8 is a block circuit diagram showing a configuration of the state control unit 42. As shown in FIG. The state control unit 42 is configured by an OR circuit that generates a logical sum of the normal control signal and the state control signal MODE as input signals. Then, when the HVth-Tr control signal output from the state control unit 42 is 1, each HVth-Tr is controlled to be turned on. That is, in the present embodiment, the function of the test control unit 42a and the function of the normal control unit 42b shown in FIG.
Built into the circuit.

The functions of the test control unit 6a and the normal control unit 6b (see FIG. 1) in the first embodiment can be realized by one OR circuit with the configuration shown in FIG.

A method of generating a test sequence for a semiconductor integrated circuit configured as described above will be described with reference to the flowchart of FIG.

In step ST31, a netlist shown in Table 1 below is created as a circuit description of the logic circuit group 43 to be inspected.

[0072]

[Table 1]

Here, sample1 indicates the name of this logic circuit, and input indicates the external input pins A, B, C, D
, Output indicates the external output pin OUT, and the wire declaration indicates that net1 to net4 are wiring nets between cells. DFF, AND, OR, and INV are cell names registered in the library, and io to i4
Is an instance name for identifying each cell. ne
t1 to net4 represent wiring nets between cells. In the above Table 1, for example, the description regarding AND is “element i1 which is the AND element AND registered in the library.
, The input pin A is connected to the wiring net net4, the input pin B is connected to the external input pin D, and the output pin Y is connected to the wiring net net2. "

As described above, in the circuit description of the semiconductor integrated circuit constituted by the conventional CMOS semiconductor device, the information on the signal propagation between the elements is described, but the description on the power supplied to each element is described. There is no. This is because supply of power is premised because no high-threshold transistor for disconnecting the power supply from the logic circuit is provided. Also in this embodiment, at the time of inspection, assuming that power is supplied to each of the logic circuits 5a to 5x in the logic circuit group 43 composed only of the low threshold transistors to be inspected, the logic circuit group 43 Can be regarded as a conventional CMOS circuit, and can be described as a netlist as described above.

Next, in step ST 32, the netlist created in step ST 31 is compared with the conventional C
A test sequence is generated using the same means as that of the MOS semiconductor integrated circuit. Table 2 below shows a test sequence for detecting a 0 stuck-at fault in the Q output of a flip-flop DFF generated by using a conventional CMOS semiconductor integrated circuit test method, based on the circuit description shown in Table 1 above. Is shown.

[0076]

[Table 2]

In Table 2, 0 and 1 indicate input signals, H indicates that the expected value is 1, and X indicates don't care.

Next, in step ST33, a sequence for controlling the state control unit is added to the test sequence shown in Table 2 generated in step ST32. Table 3 below
Shows a test sequence obtained by adding a new sequence relating to the state control signal MODE to the test sequence shown in Table 2 above.

[0079]

[Table 3]

In the above Table 3, the state control signal MODE
Is output, a signal for controlling each HVth-Tr to be turned on is output, and a test of the logic circuit group 43, in this example, a test for a stuck-at fault of the Q output of the flip-flop DFF is performed.

As described above, the test sequence of the MT-CMOS semiconductor integrated circuit can be generated by using the conventional method.

FIG. 14 is a block diagram schematically showing a configuration of an inspection apparatus used for inspecting logic circuit group 43. In FIG.
The tester 70 includes an input sequence storage device 71 for storing an input sequence and an expected value storage device 72 for storing an expected value of an output corresponding to the input sequence. The sequence input device 73 transmits signals in a sequence (for example, the sequence shown in Table 3) according to the stored contents of the input sequence storage device 71 via the input side probe 76a to the logic circuit group 43 of the semiconductor integrated circuit device. From the external input pins A, B, C, and D (see FIG. 6). further,
The determination circuit 75 compares the logical value of the output signal output from the external output pin OUT via the output side probe 76b with the expected value (logical value) stored in the expected value storage device 72, and If they match, it is determined to pass, and if they do not match, it is determined to fail. This judgment result is
It is displayed on the display device 75.

In this embodiment, a plurality of MT-CMs
Although a semiconductor integrated circuit including a logic block constituted by an OS semiconductor device has been described, the present invention can be similarly applied to a semiconductor integrated circuit including a logic block constituted by one MT-CMOS semiconductor device.

Further, in the present embodiment, the state control section is provided outside the logical block. However, the same effect can be obtained by configuring the state control section in each logical block.

Further, in the present embodiment, the state control signal which is an input of the state control unit is configured to be supplied from outside the semiconductor integrated circuit. A similar effect can be obtained by adding a series for setting a set of logic circuits to an operating state in step ST33.

(Fourth Embodiment) Next, a description will be given of a fourth embodiment in which the state control unit is formed of a sequential circuit and there are a plurality of output signals from the state control unit. FIG.
0 is a logic circuit diagram showing a configuration of the state control unit 50 according to the present embodiment. Such a state controller 50 can be applied to, for example, an MT-CMOS semiconductor integrated circuit having a configuration as shown in FIG. That is, the HV of each logical block
This is the case where the control signal is sent to th-Tr. However, for ease of explanation, in the present embodiment, it is assumed that a logic circuit group 43 having the configuration shown in FIG. 7 is provided in the logic blocks i and j.

As shown in FIG. 10, a flip-flop 51, an inverter 52, an OR
A circuit 53 is provided. Then, the state control signal M
By controlling the Q output of the flip-flop 51 in the state control unit to 1 using ODE1 and CLK, the HVth-Tr control signal for the logic block i becomes 1 and the output of the inverter 52 becomes 0. Further, when the state control signal MODE2 becomes 1, the output of the OR circuit 53 becomes 1. In this way, control is performed so that HVth-Tr in all the logic blocks i and j in which the logic circuit group is disposed is turned on. Although not shown, the normal control signal includes a flip-flop 51, an inverter 52, and an O.
It is configured to pass through the state control unit 50 without passing through the R circuit 53 and be input to the logic circuit group 43.

Table 4 below shows the MT-CMOS of this embodiment.
4 shows an example of a test sequence for a semiconductor integrated circuit.

[0089]

[Table 4]

That is, in the same procedure as the flowchart shown in FIG. 9 in the third embodiment, a net list is created (step ST31), and a test sequence for the net list is generated (step ST32). The test sequence generated using the conventional method in step ST32 is the portion up to A, B, D, and OUT in the lower two stages in Table 4 (see Table 1 above). And step ST
At 33, by adding the series of the state control signals MODE1, MODE2 and CLK, the HVth-Tr of all the logic blocks in which the logic circuit group is arranged can be controlled to the ON state, and the operation of the logic circuit group can be controlled. Inspection can be performed. Note that a tester 70 as shown in FIG. 14 can be used as the inspection device.

As described above, even when the state control unit is constituted by a sequential circuit or when there are a plurality of output signals from the state control unit, all the logic blocks in which the logic circuit group to be inspected is provided are provided. By providing a state in which an output for supplying power is obtained in the state control unit, a conventional method can be used.

In this embodiment, the logical blocks i,
j is assumed to be a single one. However, for a configuration in which an HVth-Tr control signal is output for each of the logical block groups i and j including a plurality of logical blocks, generation of the test sequence in the present embodiment is also possible. Method can be applied.

Further, in the present embodiment, the state control unit is provided outside the logical block, but the same effect can be obtained by configuring the state control unit in each logical block.

Further, in this embodiment, the state control signal which is the input of the state control unit is configured to be supplied from outside the semiconductor integrated circuit. A similar effect can be obtained by adding a series for setting a part so that a logic circuit group to be inspected is in an operating state.

(Fifth Embodiment) Next, a fifth embodiment according to an example in which an HVth-Tr control signal is directly applied from the outside without providing a state control unit in a semiconductor integrated circuit will be described. FIG. 11 is a block diagram illustrating a configuration of a state control unit and a signal input unit in a semiconductor integrated circuit according to the fifth embodiment.

As shown in FIG. 11, in this embodiment, the state control section 60 is provided in an external device (for example, a tester), and an input pin for receiving a state control signal from the outside is provided in the semiconductor integrated circuit. Only 61 are provided. When the state control signal MODE is input from the state control unit, the state control signal MODE is directly input to the HVth-T
r Output as control signal.

Table 5 below shows a test sequence according to the present embodiment.

[0098]

[Table 5]

As can be seen from Table 5, in this embodiment, a test sequence is generated in the same procedure as in FIG. 9 in the third embodiment. Further, also in the present embodiment, a tester 70 as shown in FIG. 14 can be used.

As described above, even when a logic element is not provided in the status control unit and a status control signal is externally supplied,
By simply adding a state control signal MODE for controlling HVth-Tr to the test sequence generated by the conventional method,
A test sequence for an MT-CMOS semiconductor integrated circuit can be generated.

In this embodiment, a plurality of MT-CMs
Although a semiconductor integrated circuit including a logic block constituted by an OS semiconductor device has been described, the present invention can be similarly applied to a semiconductor integrated circuit including a logic block constituted by one MT-CMOS semiconductor device.

In the first to fourth embodiments, the state control unit may be provided outside the semiconductor chip (semiconductor integrated circuit).

(Sixth Embodiment) Next, a high-threshold transistor dedicated to inspection and a high-threshold transistor for normal control are connected between each logic circuit of each logic circuit block and a power supply terminal and a ground terminal. A sixth embodiment relating to a method for generating a test sequence of a semiconductor integrated circuit in which each is interposed will be described.

FIG. 12 shows an MT-CMO according to this embodiment.
FIG. 2 is an electric circuit diagram showing a configuration of an S semiconductor integrated circuit 41.

As shown in FIG. 12, the semiconductor integrated circuit 41
Is basically the same as the configuration of the semiconductor integrated circuit 41 shown in FIG. 6 in the third embodiment described above. However, in the present embodiment, for each of the logical blocks 7a to 7x, the pHVth-Tr1a to 1x and nHVth dedicated to inspection are used.
-Apart from Tr 2a to 2x, pHVth dedicated to normal control-
Tr 1a'-1x 'and nHVth-Tr 2a'-2x'
Are provided between the virtual power supply terminals 3a to 3x and the power supply terminal 10 of each of the logic circuits 5a to 5x and between the virtual ground terminal 4a and the ground terminal 11 in parallel with each other. ing. Then, the test controller 42a in the state controller 42 adjusts the pH according to the test signal MODE.
On / off of Vth-Tr 1a to 1x and nHVth-Tr 2a to 2x is controlled, while the normal control unit 42b in the state control unit 42 controls the pHVth-T according to the normal control signal.
It is configured to control on / off of r1a 'to 1x' and nHVth-Tr2a 'to 2x'.

The configuration of the logic circuit group 43 composed of the logic circuits 5a to 5x may be, for example, as shown in FIG. 7, and when the test signal MODE is 1, pHVth-Tr 1
Turn on a ~ 1x and nHVth-Tr 2a ~ 2x,
Inspection of the presence or absence of a failure in the logic circuit group 43 and a method of generating a test sequence can be performed in the same manner as in the third embodiment. Further, also in the present embodiment, a tester 70 as shown in FIG. 14 can be used.

According to this embodiment, the same effect as in the third embodiment can be exhibited.

In the third to fifth embodiments, similarly to this embodiment, a high threshold transistor dedicated to inspection and a high threshold transistor dedicated to normal control are used.
They can be arranged in parallel between the power supply terminal and the ground terminal and each logic circuit.

[0109]

According to the first to eighth aspects, the MT-CMOS
As a semiconductor circuit system including a semiconductor integrated circuit, a high threshold transistor is provided between at least one of a high-potential power supply and a low-potential power supply and a logic circuit. Since the on / off of the high-threshold transistor is controlled in accordance with the type, a fault in the logic circuit in the MT-CMOS semiconductor integrated circuit and a fault outside the logic circuit, that is, a short circuit of the wiring or a high threshold value Inspection can be performed while distinguishing the failure caused by the malfunction of the transistor, and the MT-C having good characteristics can be inspected.
It is possible to provide a MOS semiconductor integrated circuit.

In particular, according to claim 6, in addition to the above configuration, means for detecting a current in a part of a path from the first terminal to the second terminal, and a set value for pass / fail determination are set in advance. Means for storing, a means for determining whether or not the current is greater than or equal to a set value, and a display for displaying the determination result are further provided.
It is possible to provide a function of quickly selecting a MOS semiconductor integrated circuit.

According to the seventh or eighth aspect, when a command for testing a logic circuit is received, the high threshold transistor is controlled to be turned on.
It is possible to check whether the operation of the logic circuit arranged in the OS semiconductor integrated circuit is normal or abnormal.

According to the ninth to eleventh aspects, the MT-CMOS
As a test method of a semiconductor integrated circuit, a current in a part of a path from a first terminal to a second terminal is detected in a state where a high threshold transistor is turned off, and a detected value of the current is set to a set value. In the above case, it is determined to be rejected, while when the detected value of the current is less than the set value, it is determined to be passed. A semiconductor integrated circuit can be obtained.

According to claims 12 to 14, the MT-CMO
As a method of generating a test sequence for an S semiconductor integrated circuit, a test sequence including a description of an input / output relationship is prepared after creating a partial circuit description relating to a connection state between the above-described elements of a logic circuit to be tested. Since a new series for turning on the high threshold transistor connected to the logic circuit to be inspected is added to the series, the conventional CMOS semiconductor integrated circuit inspection method can be used as it is. A test sequence of the MT-CMOS semiconductor integrated circuit can be generated, and thus, the cost required for developing new software can be reduced.

[Brief description of the drawings]

FIG. 1 is an electric circuit diagram of an MT-CMOS semiconductor integrated circuit according to a first embodiment.

FIG. 2 is a block diagram schematically showing a configuration of an inspection device according to the first embodiment.

FIG. 3 is a flowchart illustrating an inspection procedure according to the first embodiment.

FIG. 4 is an electric circuit diagram of an MT-CMOS semiconductor integrated circuit according to a second embodiment.

FIG. 5 is a flowchart illustrating an inspection procedure according to the second embodiment.

FIG. 6 is an electric circuit diagram of an MT-CMOS semiconductor integrated circuit according to a third embodiment.

FIG. 7 is a block diagram illustrating a configuration of a logic circuit group in an MT-CMOS semiconductor integrated circuit according to a third embodiment.

FIG. 8 is a block diagram illustrating a configuration of a state control unit in an MT-CMOS semiconductor integrated circuit according to a third embodiment.

FIG. 9 is a flowchart illustrating an inspection procedure according to the third embodiment.

FIG. 10 is a block diagram illustrating a configuration of a state control unit in an MT-CMOS semiconductor integrated circuit according to a fourth embodiment.

FIG. 11 is a block diagram illustrating a configuration of a state control unit in an MT-CMOS semiconductor integrated circuit according to a fifth embodiment.

FIG. 12 is an electric circuit diagram of an MT-CMOS semiconductor integrated circuit according to a sixth embodiment.

FIG. 13 is an electric circuit diagram showing a basic configuration of a conventional MT-CMOS semiconductor device.

FIG. 14 is a block diagram schematically showing a configuration of an inspection device according to a third embodiment.

[Explanation of symbols]

Reference Signs List 1 pHVth-Tr (p-channel high threshold transistor) 2 nHVth-Tr (n-channel high threshold transistor) 3 virtual power terminal 4 virtual ground terminal 5 logic circuit 6 state controller 7 logic block 8 semiconductor integrated circuit 10 power supply Terminal 11 Ground terminal 13 Tester 14 Probe 15 Ammeter 16 Storage device 17 Judgment circuit 18 Display device 21 Semiconductor integrated circuit 22 State control unit 41 Semiconductor integrated circuit 42 State control unit 43 Logic circuit group

Continuation of front page (58) Field surveyed (Int.Cl. ⁶ , DB name) G01R 31/28-31/3193

Claims (14)

(57) [Claims] 1. A semiconductor circuit system having an inspection commanding means for instructing whether or not the semiconductor integrated circuit is normal or abnormal inside or outside the semiconductor integrated circuit, wherein the semiconductor integrated circuit has a high potential side. A first terminal for supplying a voltage, a second terminal for supplying a low-potential-side voltage, and a plurality of low voltage terminals interposed between the first terminal and the second terminal. At least one logic circuit having a threshold transistor disposed therein, and at least one of the first terminal and the second terminal interposed between the logic circuit and an on / off switch. A high-threshold transistor for switching the logic circuit between an operating state and a standby state by switching, and a logic circuit connecting the first terminal, the second terminal, the logic circuit and the high-threshold transistor. Arrangement And a state control unit that controls on / off of the high threshold transistor according to the type of the test command when receiving a test command from the test command unit. Semiconductor circuit system. 2. The semiconductor circuit system according to claim 1, wherein said state control section receives said high threshold when said inspection command is issued from said inspection command means for said external logic circuit wiring and said high threshold transistor. A semiconductor circuit system for controlling a value transistor to be turned off. 3. The semiconductor circuit system according to claim 2, wherein a plurality of said logic circuits are provided, and said first terminal and said second terminal are shared by all said logic circuits. And a state control unit that controls the high threshold transistors connected to all the logic circuits to be in an off state. 4. The semiconductor circuit system according to claim 2, wherein a plurality of said logic circuits are provided, and said first terminal and said second terminal are one or more of said all logic circuits. When the state control unit receives a test command for the extra-logic-circuit wiring and the high-threshold transistor from the test command unit, the state control unit uses the common first terminal- A semiconductor circuit system, wherein the high threshold transistor connected to a logic circuit between the second terminals is controlled to be turned off. 5. The semiconductor circuit system according to claim 2, wherein said high threshold transistor is interposed between said first terminal and said logic circuit and between said second terminal and said logic circuit, respectively. A semiconductor circuit system, which is provided. 6. The semiconductor circuit system according to claim 2, wherein said current detecting means detects a current flowing between said first terminal and said second terminal. A storage means for storing a set value for pass / fail determination with respect to the detected value in advance; connected to the current detection means and the storage means, and when the detection value of the current detection means is equal to or more than the set value during the inspection, On the other hand, when the current value of the current detecting means is less than the set value, the apparatus further comprises a determining means for determining a pass, and a display means for displaying a determination result of the determining means. Semiconductor circuit system. 7. The semiconductor circuit system according to claim 1, wherein said state control unit receives a test command in said logic circuit from said test command means, and outputs a logic signal to be tested in said logic circuit. A semiconductor circuit system, wherein the high threshold transistor connected to a circuit is turned on. 8. The semiconductor circuit system according to claim 7, wherein: a means for inputting a test signal to the logic circuit; and an expected value of a logic value output when the logic circuit is normal with respect to the test signal. An expected value storage means for storing in advance, connected to the expected value storage means, and comparing the logic value of the output signal from the logic circuit with the expected value, and at the time of the inspection, the logic value of the output signal and the When the expected value matches, the judgment is made as pass, while when the logical value of the output signal does not match the expected value, judgment means judges as reject, and display means for displaying the judgment result of the judgment means. A semiconductor circuit system further provided. 9. A first terminal for supplying a high-potential-side voltage, a second terminal for supplying a low-potential-side voltage, and an intermediate terminal between the first terminal and the second terminal. And at least one logic circuit having a plurality of low-threshold transistors disposed therein and interposed between at least one of the first terminal and the second terminal and the logic circuit. A high threshold transistor for switching the logic circuit between an operating state and a standby state by switching on and off; a first terminal, a second terminal, a logic circuit, and a high threshold transistor A method for inspecting a semiconductor integrated circuit, comprising: an external logic circuit wiring connecting between the first terminal and the second terminal; To detect the current flowing through And a third step of judging rejection when the detected value of the current is equal to or greater than a set value, and determining that the test is acceptable when the detected value of the current is less than the set value. An inspection method for a semiconductor integrated circuit. 10. The method for testing a semiconductor integrated circuit according to claim 9, wherein a plurality of the logic circuits are provided, and the first terminal and the second terminal are common to all the logic circuits. Wherein the high threshold transistors connected to all the logic circuits are turned off in the second step. 11. The method for testing a semiconductor integrated circuit according to claim 9, wherein a plurality of said logic circuits are provided, and said first terminal and said second terminal are one of said logic circuits. One or a plurality of logic circuits, and in the second step, the common first terminal-second
Wherein the high threshold transistor connected to the logic circuit between the terminals is turned off. 12. A first terminal for supplying a high potential side voltage, a second terminal for supplying a low potential side voltage,
At least one logic circuit interposed between the first terminal and the second terminal and configured by arranging a number of elements including a plurality of low threshold transistors; A high threshold transistor interposed between at least one of the second terminals and the logic circuit for switching the logic circuit between an operating state and a standby state by switching on and off; An external logic circuit wiring connecting the first terminal, the second terminal, the logic circuit and the high threshold transistor, and a state control for outputting a control signal for controlling on / off of the high threshold transistor Generating a test sequence of a semiconductor integrated circuit having a portion, wherein a partial circuit relating to a connection state between the respective elements in a logic circuit to be tested out of the at least one logic circuit. A first step of creating a description, and a description of an input / output relationship for determining an appropriate state of operation in the logic circuit to be inspected based on the partial circuit description created in the first step A second step of creating a test sequence consisting of: a control signal output from the state control unit includes, in the test sequence, the high threshold transistor connected to the logic circuit to be tested; And a third step of creating a new series to be in a mode for turning on and adding the new series to the test series created in the second step. Generation method. 13. The method of generating a test sequence for a semiconductor integrated circuit according to claim 12, wherein said high threshold transistor is connected to at least one of said first terminal and said second terminal and said logic circuit. A plurality of high-threshold transistors connected in parallel with each other, and a part of the plurality of high-threshold transistors connected in parallel is configured as a high-threshold transistor dedicated to inspection. In the step, the control signal output from the state control unit is set to a mode for turning on only the high-threshold transistor dedicated to inspection out of the plurality of high-threshold transistors connected in parallel. A method for generating a test sequence for a semiconductor integrated circuit, wherein a new sequence is created. 14. The method of generating a test sequence for a semiconductor integrated circuit according to claim 12, wherein the high threshold transistor connected to the logic circuit to be tested is externally supplied when testing the logic circuit. In the third step, the control signal input from the outside sets the logic circuit to be tested to an operable state in the third step. Create a new series that will be a mode to do
A test sequence generation method for a semiconductor integrated circuit, wherein the test sequence is added to the test sequence created in the second step.