JPH065874A - Manufacture of nonvolatile semiconductor memory - Google Patents

Abstract

PURPOSE:To readily control the roundness of shape of the floating gate and the end part of various electrodes of a transistor by heat-treating the electrodes of the floating gate and control gate as well as gates of peripheral circuits. CONSTITUTION:A resist film 73 is applied to cover a drain region 56. Arsenic ions are implanted using the resist film as a mask together with a control electrode 55 and a floating gate 52, followed by vertical implantation of phosphorus to the substrate. A heat treatment is performed to form an n-type source region 57. The surface of the substrate is oxidized in a dry oxygen atmosphere at 950 deg.C for more than ten minutes; the temperature higher than 900 deg.C brings about controlled diffusion reaction to round the edges of the floating gate 52. When the floating gate is formed, both anisotropic and isotropic etching steps are employed to give round edges to it.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a nonvolatile semiconductor memory device capable of electrically writing and erasing, and more particularly to a method of manufacturing a flash memory.

[0002]

2. Description of the Related Art A flash memory is known as a nonvolatile semiconductor memory device in which data can be freely written and the written information charges can be electrically erased.

FIG. 18 is a block diagram showing a general structure of a flash memory. Referring to FIG. 18, the flash memory includes a memory cell matrix 100 arranged in a matrix, an X address decoder 200, a Y gate 300, a Y address decoder 400, an address buffer 500, and a write circuit 600. , Sense amplifier 700
Input / output buffer 800 and control logic 9
00 and. Memory cell matrix 100
Has a plurality of memory cell transistors arranged in a matrix therein. Memory cell matrix 100
Address decoder 20 for selecting rows and columns of
0 and the Y gate 300 are connected. Y gate 30
0 is a Y address decoder 40 that gives column selection information.
0 is connected. An address buffer 500 for temporarily storing address information is connected to each of the X address decoder 200 and the Y address decoder 400. The Y gate 300 has a write circuit 600 for performing a write operation at the time of data input, and a sense amplifier 700 for determining “0” and “1” from the value of a current flowing at the time of data output.
Are connected. Write circuit 600 and sense amplifier 70
An input / output buffer 800 for temporarily storing input / output data is connected to 0. Address buffer 50
A control logic 900 for controlling the operation of the flash memory is connected to 0 and the input / output buffer 800. The control logic 900 performs control based on the chip enable signal, the output enable signal and the program signal.

FIG. 19 is a block diagram of the memory selma shown in FIG.
FIG. 6 is an equivalent circuit diagram showing a schematic configuration of the trick 100.
In the figure, a plurality of word lines WL extending in the row direction₁,
WL ₂, ..., WL_iAnd a plurality of
Line BL₁, BL₂・ ・ ・, BL_jAnd are orthogonal to each other
To form a matrix. Each word
Floating at the intersection of each bit line and each bit line
Memory cell transistor Q having a gate_{1 1}, Q_{1 2}
... Q_ijAre arranged. Each memory cell transaction
The drain of the transistor is connected to each bit line. Me
The source of the memory cell transistor is each source line S₁, S
₂,···It is connected to the. Memories belonging to the same row
Sources of transistors are interconnected as shown
Has been done.

FIG. 20 is a partial cross-sectional view showing the cross-sectional structure of one memory cell transistor constituting the above flash memory. The flash memory shown in FIG. 20 is called a stack gate type flash memory. FIG. 21 is a sectional structural view of a conventional flash memory. The structure of a conventional flash memory will be described with reference to FIGS.

A p-type semiconductor substrate 1 having a main surface and a matrix of m rows and n columns are arranged on the main surface of the p-type semiconductor substrate 1 with an insulating film 2 made of SiO ₂ interposed therebetween (m
× n) charge storage electrodes (floating gate electrodes)
3 are arranged. Adjacent two of the charge storage electrodes 3
Element isolation region (not shown) for each row across the rows
Are formed. Further, on the charge storage electrode 3, Si
M word lines (control gate electrodes) 6 formed in each row are formed through an insulating film 5 made of O ₂ or the like.

An impurity concentration of 5 × 10 ¹⁹ / cm ³ , which extends from the main surface of the semiconductor substrate 1 in a region surrounded by an element isolation region (not shown) and the charge storage electrode 3 to a predetermined depth.
An n-type drain region 7 having a sheet resistance of 80Ω · □ is formed. Further, the drain region 7 impurity concentration from the outer region of the main surface of semiconductor substrate 1 to a prescribed depth of the charge storage electrodes 3 sandwiching the 1 × 10 ^{2 1} / cm ^3, the n-type formed of sheet resistance 50 [Omega · □ The source region 8 is formed.

A third insulating film 9 is formed so as to cover the charge storage electrode 3 and the word line 6 and partially overlap the drain region 7.

The drain region 7 is formed on the drain region 7 along the side wall of the third insulating film 9.
A first conductive layer 10 of polysilicon electrically connected to the first conductive layer 10 is provided. In this first conductive layer 10,
Further, a second conductive layer 11 made of a refractory metal material such as tungsten (W) is provided so as to extend upward. The second conductive layer 11 is connected to each of the n bit lines 13 through the interlayer insulating film 12 deposited so as to cover the third insulating film 9 and the first conductive layer 10.

The operation of the flash memory configured as described above will be described with reference to FIG.

First, in the writing operation, a voltage V _{D of} about 5 to 7 V is applied to the n-type drain region 7, and a voltage V _{G of} about 10 to 12 V is applied to the control gate electrode 6. Further, the n-type source region 8 and the p-type semiconductor substrate 1 are kept at the ground potential. At this time, a current of several 100 μA flows through the channel of the memory transistor. Among the electrons flowing from the source to the drain, the electrons accelerated near the drain are
In this vicinity, electrons having high energy, that is, channel hot electrons are generated. Some of these electrons cross the energy barrier at the interface between the oxide film and the silicon substrate and are injected into the charge storage electrode (floating gate electrode) 3 as shown by the arrow in the figure. When electrons are stored in the charge storage electrode 3 in this way, the threshold voltage V _th of the memory transistor increases. A state in which the threshold voltage V _th is higher than a predetermined value is written, which is called "0".

Next, in the erase operation, a voltage V _{s of} about 10 to 12 V is applied to the n-type source region 8 and the control gate electrode 6 and the p-type semiconductor substrate 1 are held at the ground potential. Further, the n-type drain region 7 is opened.
Due to the electric field generated by the voltage V _s applied to the n-type source region 8, the electrons in the charge storage electrode 3 pass through the thin gate oxide film 2 by the tunnel phenomenon as shown by the arrow in the figure. In this way, the electrons in the charge storage electrode 3 are extracted, so that the threshold voltage V _th of the memory transistor is lowered. A state in which the threshold voltage V _th is lower than a predetermined value is called an erased state, “1”. Since the sources of the memory transistors are connected as shown in FIG. 19, all memory cells can be collectively erased by this erase operation.

Further, in the read operation, the control
The voltage V of about 5V is applied to the gate electrode 6. _{G 1}, N-type drain
The voltage V of about 1 to 2 V in the area 7_{D 1}Is applied. this
Current flows through the channel region of the memory transistor
Whether the memory transistor is on
Depending on whether it is in the off state, the above "1" and "0" can be judged.
Be seen.

[0014]

The above-mentioned flash memory has the following problems. That is, the source regions of the plurality of memory cells are electrically connected due to the structure. Then, an electric field applied between the charge storage electrode 3 and the source region 8 at the time of erasing causes electrons to be extracted from the charge storage electrode 3 by a tunnel phenomenon. Here, the shape of the end portion (edge portion) of the charge storage electrode 3 becomes uneven due to the crystal (drain) of polycrystalline silicon that is the material of the charge storage electrode 3 when the charge storage electrode 3 is processed. Therefore, when a voltage is applied to the source region common to the plurality of memory cells, the electric field concentration is caused by the uneven shape of the edge portion of the charge storage electrode 3. As a result, the strength of the electric field varies between the charge storage electrode 3 and the source region 8 among the plurality of memory cells, and as a result, the erase characteristic also varies. That is,
Among a plurality of memory cells erased at the same time, the earliest erased memory cell has a problem that it causes a so-called over-erased state in which the threshold voltage V _th becomes negative.

The drain regions 7 of the memory cells located on the same bit line structurally are electrically connected. Therefore, a voltage of about 5 to 7 V is applied as the drain voltage V _D at the time of writing to the drain region 7 of the non-selected memory cell on the same bit line as the memory cell selected for the write operation. As a result, electrons are extracted from the charge storage electrode 3 to the drain region 7 by the tunneling phenomenon. At the same time, holes generated by the application of the voltage V _D close to the junction breakdown voltage of the drain region 7 are injected into the charge storage electrode 3 and combine with the electrons in the charge storage electrode 3 to erase the information. This phenomenon is called drain disturb.

Among the causes of the above-described drain disturbance, the extraction of electrons from the charge storage electrode 3 to the drain region 7 by tunneling is likely to occur due to the concentration of charges due to the uneven shape of the end portion of the charge storage electrode 3. .

Therefore, conventionally, as shown in FIG. 21, the surface of the semiconductor substrate 1 is wet-oxidized after the control gate 6 and the charge storage electrode 3 are formed,
A method for reducing the uneven shape of the end of the charge storage electrode 3 has been proposed.

However, in the proposed wet oxidation treatment method, the thickness of the insulating film 5 located between the charge storage electrode 3 and the control gate 6 is partially increased (gate bird's beak). There was a problem that it would end up.
That is, there is a problem that the insulating film 5 in the vicinity of the end portion (edge portion) of the control gate 6 and the charge storage electrode 3 becomes thicker than other portions. As a result, there is a problem that the electric capacitance between the control gate 6 and the charge storage electrode 3 is reduced, and a high voltage is required in the operating state.

Further, the insulating film 2 between the charge storage electrode 3 and the source region 8 also has a disadvantage that the edge portion through which electrons actually pass is partially thickened. As a result, there is a problem that a higher source voltage is required at the time of erasing data as compared with the case where no oxidation treatment method is applied.

Further, in the peripheral circuit region, the gate oxide film (not shown) located between the gate electrode (not shown) of the MOS transistor forming the peripheral circuit and the semiconductor substrate 1 is also partially formed at the edge portion. However, there is a problem in that a thick film is generated. As a result, there is a problem that the transistor characteristics are deteriorated.

The present invention has been made in order to solve the above problems, and raises the operating voltage of a memory cell caused by oxidizing the surface of a semiconductor substrate and the transistor of a transistor forming a peripheral circuit. An object of the present invention is to provide a method for manufacturing a non-volatile semiconductor memory device that can effectively prevent characteristic deterioration.

[0022]

A method of manufacturing a non-volatile semiconductor memory device according to claims 1 and 2 comprises a step of forming a first insulating film in a memory cell region on a main surface of a semiconductor substrate, and a first insulating film. A step of forming a first conductive film on the first direction at a predetermined distance, a step of forming a second insulating film on the first conductive film, and a peripheral circuit region on the main surface of the semiconductor substrate. A peripheral circuit is formed by forming a third insulating film, forming a second conductive film on the second insulating film and the third insulating film, and patterning the second conductive film in the peripheral circuit region. Forming a gate electrode of the transistor, a step of forming a resist on the second conductive film in the memory cell region at a predetermined interval in a second direction substantially orthogonal to the first direction, and a mask of the resist As a pattern of the first conductive film and the second conductive film. Forming a floating gate electrode and a control gate electrode by dry etching, a step of dry-oxidizing the floating gate electrode, the control gate electrode and the gate electrode in the peripheral circuit region under a temperature condition of 900 ° C. or higher; And a step of forming a nitride film on the oxide film.

[0023]

In the method for manufacturing a nonvolatile semiconductor memory device according to the first and second aspects, after the floating gate electrode, the control gate electrode and the gate electrode in the peripheral circuit region are formed, they are dried under a temperature condition of 900 ° C. or higher. Since the film is oxidized, the film thickness of the film to be oxidized is easily controlled, and the interface between silicon and the oxide film becomes a diffusion rate-controlled reaction in the course of the oxidation and the interface shape becomes smooth. Further, since the oxide film is formed on the entire surface after the dry oxidation is performed under the temperature condition of 900 ° C. or more and the nitride film is further formed on the oxide film, the nitride film prevents the passage of the oxidizing species.

Further, by using anisotropic etching and isotropic etching together when forming the control gate and the floating gate, the uneven shape of the sidewall portion of the floating gate is flattened. As a result, variations in erase characteristics and the occurrence of drain disturb are effectively prevented.

[0025]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a sectional structural view of a memory cell according to an embodiment of the present invention. FIG. 2 is a plan view of a memory cell array based on the present invention, and a cross-sectional view taken along the line XX of FIG. 2 is a cross-sectional structural view shown in FIG.

Referring to FIGS. 1 and 2, p ^-- type well region 50 is formed on the main surface of single crystal silicon.
(M × n) charge storage electrodes (floating gates) 52 arranged in a matrix of m rows and n columns are arranged on the main surface of the p ⁻ type well region 50 via an insulating film 51 made of SiO _2. Has been done.

An element isolation region 53 is formed between each row of the charge storage electrodes 52 extending over two adjacent rows. In addition, m control gates 55 formed in each row are formed on the charge storage electrode 52 via an insulating film 54 made of SiO ₂ or the like.

Element isolation region 53 and charge storage electrode 52
An n-type drain region 56 is formed to a predetermined depth from the main surface of the p ⁻ type well region 50 surrounded by. P at a predetermined distance from the drain region 56
^- n from the main surface of the type well region 50 to a prescribed depth
A source region 57 of the mold is formed. Further, a third insulating film 58 is formed so as to cover the charge storage electrode 52 and the control gate 55 and partially overlap the drain region 56 and the source region 57.

On the drain region 56, a polysilicon film or a composite film in which a refractory metal is laminated on the polysilicon, which is electrically connected to the drain region 56 and is along the side wall of the third insulating film 58, is formed. One conductive layer 59 is provided. An oxide film 81 is formed so as to cover the entire surface, and a nitride film 82 is formed so as to cover the oxide film 81. A second conductive layer 60 made of a refractory metal such as tungsten (W) is electrically connected to the first conductive layer 59 so as to extend further upward. The second conductive layer 60 is the third insulating film 5 described above.
8 and the first conductive layer 59 are respectively connected to n bit lines 62 via an interlayer insulating film 61 deposited so as to cover the first conductive layer 59.

FIG. 3 is a partially enlarged view of the memory cell structure of the embodiment shown in FIG. Referring to FIG. 3, in the memory cell structure of the present embodiment, the edges of control gate 55 and floating gate 52 are curved. Therefore, electric field concentration is less likely to occur. On the other hand, in the memory cell structure of the present embodiment, the surface height of the source region 57 and the drain region 56 and the channel region 8 are
It can be seen that the surface height of No. 3 is almost equal to that of No. 3 and is hardly oxidized.

Next, referring to FIGS. 4 to 17, the first to twelfth steps of the manufacturing process of the above embodiment will be described.

First, the p ^-- type well region 50 is formed in the memory cell region on the upper surface of the p-type silicon substrate and in the n-channel region of the peripheral circuit. Then, the element isolation region 53 is formed for each column. Boron is implanted into the p ⁻ type well region 50 only for the purpose of channel cutting with energy (about 300 KeV) having a range approximately equal to the thickness of the oxide film in the element isolation region 53. Then, in the memory cell region, boron for controlling _Vth of the memory cell is set to 50 Ke.
Inject under V, 5 × 10 ¹² / cm ² . In addition,
This step may be omitted.

Next, a first insulating film 51 made of an oxide film having a thickness of about 100Å is formed on the active region. Here, as the first insulating film 51, an oxide film having a thickness of about 100 Å subjected to a nitriding treatment may be used, or a film subjected to a nitriding treatment and then an oxidization treatment may be used. Next, a polysilicon layer (floating gate layer) 52 is deposited on the upper surfaces of the element isolation region 53 and the first insulating film 51 to a film thickness of about 1000Å. A resist film 70 patterned at a predetermined pitch is formed on the upper surface of the polysilicon layer 52.
To form. Then, anisotropic etching is performed using the resist film 70 as a mask to pattern the polysilicon layer 52 to have a predetermined pitch. As a result, the planar structure shown in FIG. 4 is completed.
FIG. 5 is a cross-sectional structural view taken along the line YY in FIG.
FIG. 6 is a sectional view taken along the line XX of FIG. Instead of the polysilicon layer 52, a low resistance polysilicon or amorphous silicon is formed by depositing phosphorus on the amorphous silicon layer or a polysilicon or amorphous silicon layer to which impurities are not added and diffusing at a high temperature. You may use. Also, CV
It is also possible to use so-called doped polysilicon in which impurities are already added at the time of deposition by flowing a gas containing impurities such as phosphorus and arsenic at the time of deposition using the D method.

Next, the resist film 70 is removed, and the second insulating film 54 is formed on the entire upper surface of the P-type silicon substrate. The second insulating film 54 is a laminated film of three layers, and an oxide film 54a having a film thickness of about 100Å, a nitride film 54b having a film thickness of about 100Å formed thereon by a CVD method, and further, It is composed of an oxide film 54c having a film thickness of about 100Å formed on the nitride film 54b. The second insulating film 54 is the oxide film 5 on the upper surface in the peripheral circuit (not shown).
4c and the predetermined portion of the nitride film 54b are removed. And
Boron implantation for controlling _{Vth of} the MOS transistor forming the peripheral circuit is performed. After that, the oxide film 54a in the peripheral circuit region is removed. The above steps are repeated when forming two or more kinds of MOS transistors existing in the peripheral circuit. In addition to boron, arsenic may be used together as the ions to be implanted. After that, the gate oxide film (not shown) of the peripheral MOS transistor is formed by the required film thickness (for example, two types of gate oxide film of 300Å and gate oxide film of 150Å).

Next, M on the second insulating film 54 and on the peripheral circuits.
A second polysilicon layer 55 having a film thickness of about 2000 Å to 3000 Å is formed on the gate oxide film (not shown) of the OS transistor in the same step. A third insulating film 58 is formed on the second polysilicon layer 55. The second polysilicon film 55 is formed of polysilicon doped with an n-type impurity such as phosphorus, or a composite film in which a refractory metal layer is laminated on polysilicon doped with an n-type impurity. After that, a patterned resist (not shown) is formed in a region where a gate electrode of a MOS transistor forming a peripheral circuit is formed. By performing anisotropic etching using this resist as a mask, the third
The insulating film 58 and the second polysilicon layer 55 are sequentially patterned. As a result, the gate electrode (not shown) of the peripheral MOS transistor is formed. Next, impurities are implanted in a self-aligned manner using the resist and the gate electrode, which are opened only in the necessary portions for forming the low concentration region of the LDD structure of the MOS transistor of the peripheral circuit, as a mask. When there are two or more types of MOS transistors in the peripheral circuit area, the above steps are repeated.

Then, a patterned resist film 71 for forming a control gate and a floating gate is formed in the memory cell region. In this way, the structure shown in FIG. 7 is completed. In the state of FIG. 7, the peripheral circuit region is entirely covered with the resist film 71.

Next, anisotropic etching is performed using the resist film 71 as a mask to form the third insulating film 58, the second polysilicon layer 55, the second insulating film 54, and the first polysilicon layer 52. Are sequentially etched. As a result, the control gate 55 and the floating gate 52 are formed as shown in FIG. After that, isotropic etching is performed to slightly etch the side surface portion of the floating gate 52. After that, the resist film 71 is removed.

Next, as shown in FIG. 8, a resist film 72 is formed on the substrate to be the source region. Resist film 7
2. Arsenic (As) 35 is self-aligned using the control gate 55 and the floating gate 52 as a mask.
Ion implantation is performed in the direction perpendicular to the substrate under the conditions of KeV and 5 × 10 ¹⁴ / cm ² . Immediately after the implantation of arsenic, boron is either completely perpendicular to the substrate or at an angle of 40 ° or less from the vertical line of the boron, 50 KeV, 3 × 10 ¹³
Ion implantation under the condition of / cm ² . Then, by the subsequent heat treatment, the concentration is 5 × 10 ¹⁹ / cm ³ , and the sheet resistance is 8
A drain region 56 made of an n-type impurity region of 0Ω · □ is formed. Immediately after implanting boron, BF ₂ may be ion-implanted under the conditions of about 30 KeV and 1 × 10 ¹³ / cm ² . After that, the resist film 72 is removed.

Next, as shown in FIG. 9, the drain region 5
The surface of 6 is covered with a resist film 73. Resist film 73, control gate 55 and floating gate 52
Arsenic (As) 35 Ke in a self-aligned manner using
Ion implantation is performed under the conditions of V and 5 × 10 ¹⁵ / cm ² .
Immediately after the implantation of arsenic, phosphorus was further ion-implanted completely perpendicularly to the substrate under the conditions of 50 KeV and 5 × 10 ¹⁴ / cm ² , and a concentration of 1 × 10 ^{2 1} /
A source region 57 composed of an n-type impurity region having a cm ³ and a sheet resistance of 50Ω · □ is formed. After this, the resist film 73
To remove. Then, the substrate surface is dry-oxidized for about 10 minutes while supplying oxygen under the temperature condition of 950 ° C.

Next, as shown in FIG. 10, an oxide film 63 is formed on the entire surface of the substrate. Then, the oxide film 63 is etched by anisotropic etching. As a result, the third insulating film 58 shown in FIG. 11 is completed.

Next, as shown in FIG. 12, polysilicon 64 is deposited on the entire surface of the silicon substrate. A resist film 74 patterned into a predetermined shape is formed on the upper surface of the polysilicon 64. Here, the polysilicon 64 is
It is formed of polysilicon doped with an n-type impurity such as phosphorus or a composite film in which a refractory metal layer is laminated on polysilicon doped with an n-type impurity. Next, using the resist film 74 as a mask, the polysilicon 64a is etched by anisotropic etching to electrically connect to the drain region 56 at the bottom thereof as shown in FIG. 13 and to the side wall of the third insulating film 58. First conductive layer 59 along
To form.

Next, as shown in FIG. 14, an oxide film 81 is formed with a thickness of about 1500Å. Then, the oxide film 81
A nitride film 82 is formed thereon with a thickness of about 500Å. Interlayer insulating film 6 made of a BPSG film or the like on the entire surface of nitride film 82.
1 is formed. After performing wet reflow at about 900 ° C. for 30 minutes, etch back is performed. As a result,
An interlayer insulating film 61 having a shape as shown in 5 is formed.

Next, as shown in FIG. 16, the interlayer insulating film 6 is formed.
A resist film 74 having a hole pattern is formed above the drain region 56. The contact hole 65 is formed by anisotropically etching using the resist film 74 as a mask.

Next, as shown in FIG. 17, a second conductive layer 60 made of a refractory metal such as tungsten is formed inside the contact hole 65. After that, the bit line 62 made of aluminum or aluminum containing silicon, lead or the like is formed. As a result, the nonvolatile semiconductor memory device according to the present invention is completed. Here, the second conductive layer 60 formed inside the contact hole 65 is CV
It may be used as a wiring layer by patterning after being formed on the entire surface by the D method. Further, a passivation film may be formed thereabove.

As described above, in the present embodiment, by performing dry oxidation at 900 ° C. or higher in the process shown in FIG. 9, a diffusion-controlled reaction that rounds the end of the floating gate 52 is caused. As a result, it is possible to suppress the gate bird's beak that occurs when the conventional wet oxidation is used. Further, the dry oxidation at 900 ° C. or higher oxidizes the leak path existing near the end portion between the control gate 55 and the floating gate 52. As a result, the leak path can be changed from conductive to non-conductive, and as a result, the charge retention characteristic of the floating gate 52 is improved. Further, when the floating gate 52 is formed, the end of the floating gate 52 is rounded by using not only anisotropic etching but also isotropic etching, so that variations in erase characteristics and drain disturb due to electric field concentration can be effectively performed. Can be prevented. Further, since the end portion of the gate electrode in the peripheral circuit region is also rounded, it is possible to effectively prevent the deterioration of the transistor characteristics in the peripheral circuit region.

By forming the nitride film 82, the oxidizing species pass directly below the interlayer insulating film 61 during the sintering process for flattening the interlayer insulating film 61 made of the BPSG film formed on the nitride film 82. Is effectively prevented. Thereby, the controllability of the above-mentioned dry oxidation at 900 ° C. or higher can be improved.

In this embodiment, after the source region 57 and the drain region 56 in the memory cell region and the source and drain regions of the transistor in the peripheral circuit region are formed, dry oxidation is performed under a temperature condition of 900 ° C. or higher. However, the present invention is not limited to this, and 900 ° C. may be formed before forming the source region 57 and the drain region 56 of the memory cell region and the source region and the drain region of the peripheral circuit region.
Dry oxidation may be performed under the above temperature conditions. By performing the dry oxidation before forming the source region and the drain region in this manner, it is possible to effectively prevent the surface of the source region and the drain region from being oxidized during the dry oxidation.

Further, after forming only the drain region 56 of the memory cell, dry oxidation may be performed under a temperature condition of 900 ° C. or higher. Thereby, only the oxide film located on the drain region 56 can be thickly formed, and the drain disturb can be effectively prevented without increasing the erase voltage.

Further, after the oxide film 63 is formed in the step shown in FIG. 10, dry oxidation may be performed under a temperature condition of 900 ° C. or higher. If you do this,
The surface of the substrate is not oxidized, and the diffusion-controlled reaction occurs only at the edge portion of the floating gate 52. As a result, only the end of the floating gate 52 can be rounded.

[0050]

According to the inventions of claims 1 and 2,
After forming the floating gate electrode and the control gate electrode on the semiconductor substrate, the floating gate electrode, the control gate electrode, and the gate electrode in the peripheral circuit region are dry-oxidized under a temperature condition of 900 ° C. or higher to remove the floating gate electrode. The round shape formed at the end and the end of the gate electrode of the transistor in the peripheral circuit region can be easily controlled to a predetermined shape. As a result, it is possible to effectively prevent the characteristics of the transistors in the peripheral circuit region from being deteriorated, and it is possible to effectively reduce the increase in voltage at the time of erasing data in the memory cell. Further, the drain disturb phenomenon at the time of writing data can be effectively prevented, and the charge retention characteristic of the memory cell can be improved. Also,
By forming the nitride film after performing dry oxidation under the temperature condition of 900 ° C. or higher, even if a high temperature heat treatment is performed in a later step, the infiltration of oxidizing species is prevented by the nitride film, so that the floating film is formed. It is possible to effectively prevent the edge portion of the gate and the edge portion of the gate electrode in the peripheral circuit region from being oxidized again.

Further, when the floating gate electrode and the control gate electrode are formed, by using anisotropic etching and isotropic etching together, it is possible to make unevenness on the side wall portion of the floating gate electrode flat. . This also makes it possible to effectively reduce the variation in the erase characteristic of data and the drain disturb phenomenon at the time of writing data.

[Brief description of drawings]

FIG. 1 is a sectional structural view of a memory cell of a flash memory according to an embodiment of the present invention.

2 is a plan view of a memory cell array including the memory cell shown in FIG. 1. FIG.

FIG. 3 is a partially enlarged view of a memory cell portion shown in FIG.

FIG. 4 is a first manufacturing process of the memory cell shown in FIG.
It is a top view for explaining a process.

5 is a cross-sectional structural view of the memory cell shown in FIG. 4 taken along the line YY.

6 is a cross-sectional structural view of the memory cell shown in FIG. 4, taken along the line XX.

FIG. 7 is a second manufacturing process of the memory cell shown in FIG.
FIG. 9 is a cross-sectional structure diagram for explaining a step.

FIG. 8 is a third manufacturing process of the memory cell shown in FIG.
FIG. 9 is a cross-sectional structure diagram for explaining a step.

9 is a fourth manufacturing process of the memory cell shown in FIG. 1. FIG.
FIG. 9 is a cross-sectional structure diagram for explaining a step.

10 is a cross-sectional structural view for explaining a fifth step of the manufacturing process of the memory cell shown in FIG.

FIG. 11 is a cross-sectional structural view for explaining a sixth step of the manufacturing process of the memory cell shown in FIG.

12 is a cross-sectional structure diagram for explaining a seventh step of the manufacturing process of the memory cell shown in FIG.

13 is a cross-sectional structure diagram for illustrating an eighth step of the manufacturing process of the memory cell shown in FIG.

FIG. 14 is a cross-sectional structural view for explaining the ninth step of the manufacturing process of the memory cell shown in FIG.

15 is a cross-sectional structure diagram for illustrating the tenth step of the manufacturing process of the memory cell shown in FIG.

16 is a cross-sectional structure diagram for explaining the eleventh step of the manufacturing process of the memory cell shown in FIG.

17 is a cross-sectional structure diagram for explaining the twelfth step of the manufacturing process of the memory cell shown in FIG.

FIG. 18 is a block diagram showing a general configuration of a flash memory.

FIG. 19 is a memory cell matrix 10 shown in FIG.
It is an equivalent circuit schematic which shows schematic structure of 0.

FIG. 20 is a partial cross-sectional view showing the cross-sectional structure of one memory cell transistor that constitutes a flash memory.

FIG. 21 is a cross-sectional structural view showing a memory cell in which a conventionally proposed semiconductor substrate surface is subjected to wet oxidation treatment.

[Explanation of reference numerals] 50: p ^- type well region 51: insulating film 52: charge storage electrode (floating gate) 54: insulating film 55: control gate 56: n-type drain region 57: n-type source region 58: no. Insulating film 59 of No. 3 59: 1st conductive layer 60: 2nd conductive layer 61: Interlayer insulating film 62: Bit line 81: Oxide film 82: Nitride film In addition, the same code | symbol shows the same or corresponding part in each figure.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Yukichi Kunosato 4-1-1 Mizuhara, Itami City, Hyogo Prefecture Mitsubishi Electric Co., Ltd. LSE Research Laboratory (72) Inventor Atsushi Fukumoto 4-Mizuhara, Itami City, Hyogo Prefecture No. 1 Mitsubishi Electric Corporation LSI Research Center

Claims (2)

[Claims] 1. A method of manufacturing a non-volatile semiconductor memory device having a memory cell region and a peripheral circuit region, the method comprising: forming a first insulating film in the memory cell region on a main surface of a semiconductor substrate; Forming a first conductive film on the first insulating film at a predetermined distance in a first direction; forming a second insulating film on the first conductive film; and a main surface of the semiconductor substrate. Forming a third insulating film in the upper peripheral circuit region, forming a second conductive film on the second insulating film and the third insulating film, and forming a second conductive film in the peripheral circuit region Forming a gate electrode of a transistor that forms a peripheral circuit by patterning the second conductive film on the second conductive film in the memory cell region at a predetermined interval in a second direction substantially orthogonal to the first direction. Resist to form a resist, and Forming a floating gate electrode and a control gate electrode by patterning the first conductive film and the second conductive film using a strike as a mask, and forming the floating gate electrode, the control gate electrode and the peripheral circuit region. Gate electrode 900 ℃
Manufacture of a non-volatile semiconductor memory device including a step of dry oxidation under the above temperature conditions, a step of forming an oxide film on the entire surface of the semiconductor substrate, and a step of forming a nitride film on the oxide film Method. 2. The step of forming the floating gate electrode and the control gate electrode is performed by using anisotropic etching and isotropic etching together.
The method for manufacturing a nonvolatile semiconductor memory device according to claim 1, comprising a step of patterning a conductive film and the second conductive film.