JPH065741B2 - Planar type semiconductor device manufacturing method - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a planar semiconductor device, and more particularly to a method for manufacturing a planar semiconductor device capable of increasing the breakdown voltage of a junction.

[Prior art]

Conventional pnpn 4-layer structure planar type thyristor and np
First, a schematic view of the main junction portion of an n3 layer structure transistor is shown.
FIG. 2 shows the impurity concentration distribution in the ab-c section in FIG. 1.

In a normal planar type thyristor or transistor, a pn junction 4 with a double planar structure is formed by impurity diffusion.
The surface of the semiconductor substrate 1 on which 0 and 50 are formed is covered with an insulating film (not shown) made of a silicon oxide film or the like to achieve high reliability. However, the pn junction 40,
When a reverse voltage is applied to 50, the electric conductivity of the surface of the semiconductor substrate in or on the insulating coating causes a change in conductivity or a conductivity type inversion phenomenon, which causes problems such as a decrease in breakdown voltage and an increase in leakage current. Sometimes. Since such a problem is more likely to occur as the impurity concentration on the surface of the pace layer 2 is lower, the base layer 2 is usually formed by, for example, boron diffusion without outward diffusion, and its impurity concentration distribution is the second. As shown in the figure, the concentration is highest near the surface, and the concentration decreases from the surface to the inside. With respect to the main junction 50 of the brener structure having the base layer 2 having such an impurity concentration distribution, it is easy to obtain a stable junction breakdown voltage with less inversion of conductivity type, but on the other hand, a pn junction between the emitter layer 3 and the base layer 2 (hereinafter There is a problem that the reverse breakdown voltage of the EB junction) 40 is usually as low as several volts. Particularly in a gate turn-off thyristor (hereinafter referred to as GTO), a reverse bias is applied to the EB junction 40 to turn it off, but the maximum anode current that can be turned off is proportional to the reverse breakdown voltage of the EB junction 40.
In order to increase the current capacity, it is necessary to increase the EB junction breakdown voltage. Further, if the EB junction breakdown voltage can be increased, there are advantages that the turn-off time can be shortened and the gate turn-off charge can be reduced. Also in the transistor, a reverse bias may be applied between the EB junctions in order to turn them off at a high speed, and the EB junction breakdown voltage has never been higher.

Thus, in the conventional planar semiconductor device, E
There is a drawback in that the B device has a low withstand voltage and cannot sufficiently meet the requirements for characteristics. On the other hand, in order to increase the EB junction breakdown voltage, there is also a method in which the impurity concentration of the base layer 2 has a maximum concentration inside the surface as shown in FIG. 3, but the impurity concentration on the surface of the base layer 2 is low. When the conductivity type of the surface layer is inverted, the blocking characteristic of the main junction 50 between the base layer 2 and the collector layer 1a is impaired in the case of the planar junction.

As described above, in the conventional planar semiconductor device,
There is a problem that it is difficult to simultaneously satisfy the blocking characteristics of the main junction 50 between the base layer 2 and the collector layer 1a and the EB junction 40.

[Object of the Invention]

The object of the present invention is to solve the above problems and to solve the problems of main joining and EB.
An object of the present invention is to provide a method for manufacturing a planar semiconductor device having excellent interjunction blocking characteristics.

[Outline of Invention]

The feature of the method for manufacturing a planar semiconductor device of the present invention is that a layer of a first conductivity type semiconductor substrate having a first opening on which a second conductivity type impurity is easily passed and a layer overlaid thereon are provided. And a step of forming a first insulating film made of a layer that does not easily pass the second electric type impurity, and guiding the second conductive type impurity into the semiconductor substrate through the first opening of the first insulating film. A step of forming a first conductivity type second semiconductor region, and forming a layer through which impurities easily pass through the first opening of the first insulating film and a layer overlying the layer of second conductivity type through which impurities hardly pass A step of covering the entire main surface of the semiconductor substrate with a second insulating film composed of a layer through which impurities of the second conductivity type easily pass and a layer overlying the layer of which impurities of the second conductivity type do not pass easily The semiconductor substrate with impurities of the second conductivity type in the first semiconductor region. Heating at a temperature sufficient to disperse, a step of forming a second opening in the second insulating film that exposes a portion of the first semiconductor region, and a semiconductor substrate having a second conductivity in the first semiconductor region. Again at a temperature sufficient to diffuse the impurity of the second type, whereby the impurity of the second conductivity type is outwardly diffused from the second opening and the maximum impurity concentration of the portion exposed in the second opening of the first semiconductor region. A step of retracting the position of the semiconductor substrate from one main surface to the inside, and after removing the second insulating film, form a third insulating film on the entire one main surface of the semiconductor substrate through which impurities of the first conductivity type cannot pass easily. And a step of forming a third opening smaller than the second opening at substantially the same position as the second opening of the third insulating film, and a step of forming a third opening of the semiconductor substrate through the third opening of the third insulating film. By guiding impurities of the first conductivity type into one semiconductor region, In that it and forming a substantially second semiconductor region of a first conductivity type having the same depth as the large impurity concentration position.

The reason why the conventional planar semiconductor device shown in FIG. 1 has a low EB junction breakdown voltage (hereinafter abbreviated as V _EB ) is considered as follows. That is, V _EB is determined by the impurity concentration of the base layer 2 at the position of the EB junction 40 (hereinafter abbreviated as NJ _EB ), and the larger N _{J EB} is, the lower V _EB is. When the impurity concentration of the base layer 2 is higher as it approaches the surface as in the conventional case, NJ _EB becomes larger at a position closer to the surface among the points of the EB junction 40. V
_{Since EB} can be located at a high position near NJ _EB near the surface, V _EB becomes low.

On the other hand, NJ _EB in the flat portion of the EB junction 40 parallel to the main surface of the semiconductor substrate is one of the important factors that affect the on and off characteristics of the device and is determined according to the required characteristics.

Therefore, according to the present invention, since the value of N _JEB at points other than the flat portion of the EB junction is less than that of the flat portion, V _EB
Can be maximized within the range of satisfying other required characteristics.

By the way, one of the other important factors that affect the on / off characteristics
One of them is the sheet resistance of the base layer (hereinafter abbreviated as ρs _B ), and it is necessary to precisely control ρs _B in order to manufacture a device having uniform characteristics with high yield. Especially in the GTO, which has a turn-off function as well as a turn-on by a gate signal, which is different from a normal thyristor,
The design tolerance of ρs _B is extremely small, and high-precision control of ρs _B is extremely important. From the viewpoint of facilitating the control of ρ s _B , the impurity concentration distribution of the base layer has a maximum impurity concentration value near the depth corresponding to the depth of the emitter layer or at a position deeper than that as shown in FIG. Have,
It is desirable that the impurity concentration decreases as it approaches the direction. However, when the impurity concentration distribution of the base layer is set as shown in FIG.
This is not a problem when the n-junction does not terminate on the main surface, but in the planar structure where the pn junction terminates on the main surface, if the impurity concentration on the base surface is low, the base layer surface may be degraded when the main junction is reverse-biased. When the conductivity changes or in an extreme case, a conductivity type inversion phenomenon occurs, and there is a problem that the blocking characteristics of the main junction deteriorate. Therefore, when the main junction is a planar structure, when the main junction is reverse biased,
The conductivity type inversion phenomenon on the surface of the base layer does not occur, and it is necessary to increase the impurity concentration on the surface of the base layer near the surface where the main junction terminates so that the depletion layer does not reach the emitter layer.

To illustrate the features of the present invention, in FIG.
The impurity concentration distribution of is 5th in the area A including the emitter layer 3.
As shown in the figure, the impurity concentration is almost maximum at a position near the depth of the emitter layer, and the impurity concentration decreases as it approaches the main surface, and the B region near the end of the main junction 50 not including the emitter layer 3 is terminated. Then, as shown in FIG. 6, the impurity concentration distribution is such that the impurity concentration near the surface becomes high. This makes it possible to obtain a planar semiconductor device in which both the EB junction 40 and the main junction 50 have good blocking characteristics.

There are several possible methods for forming the base layer 2 having different impurity concentration distributions in the A region and the B region as shown in FIG. Now, as an example of the case where the conductivity type of the base layer 2 is p-type, first, impurities such as gallium and aluminum accompanied by outward diffusion are selectively diffused, and first, as shown in FIG. After forming the base layer 2 having the maximum value, for example, boron is selectively diffused in the portion corresponding to the B region in FIG. 4 to increase the surface impurity concentration of the p base layer 2 in the B region, as shown in FIG. Such an impurity concentration distribution can be obtained. Further, as described in the following embodiments, the method of utilizing the ion implantation-drive-in diffusion of gallium or aluminum is extremely effective in manufacturing the planar type semiconductor device of the present invention.

Example of Invention

An embodiment of the present invention will be described below by taking GTO as an example.

FIG. 7 shows the GTO manufacturing process. The semiconductor substrate 1 used is a FZ, n-type silicon wafer having a resistivity of about 20 Ωcm. This wafer is placed in a mixed atmosphere of water vapor and oxygen for 8
After heat treatment at 00 ° C. for 1 hour, an oxide film (SiO ₂ ) 100 of about 500 Å is formed on the surface as shown in FIG. Then 75
SiN150 is formed on one surface of the sample by reaction of SiH ₂ Cl ₂ and NH ₃ in an atmosphere of 0 ° C. and 1 Torr. In about 40 minutes
A film of 1000Å can be obtained. Then, the nitride film (SiN) 150 is etched with hot phosphoric acid in order to obtain a desired width of the p base region by normal photoetching, and then HF and NH ₄ F are added.
Etch SiO ₂ 100 with the mixed etchant. As shown in the figure (a), ⁵⁹ Ga ₊ is implanted at 1 × 10 ₁₆ cm ^-2 at an acceleration energy of 70 KeV to form a p ^- type implanted layer 21. Since SiN 150 has a small diffusion coefficient of Al and Ga, the implanted p-layer 21 can be selectively formed as shown in FIG. Subsequently, SiO ₂ 100 and SiN 150 are formed again on the implanted p-layer 21 by the above method,
Drive in a nitrogen atmosphere at 1250 ° C for 9 hours and drive p
If the layers are deeply diffused in the silicon wafer 1, a p-base layer 2 as shown in FIG. In this case Si
Since N can prevent outward diffusion of Ga, it has a maximum impurity concentration on the surface as shown in FIG. 6, and an impurity concentration distribution that monotonically decreases toward the inside can be obtained. Then, SiO ₂ 100 on the surface of the p base layer 2 and SiN are partially photo-etched by the same method as described in FIG. (A), the opening 15 shown in FIG. Drive again at ℃ for 19 hours. Then, due to the outward diffusion of Ga, the impurity concentration distribution of the p base layer 2 below the opening 15 has the maximum impurity concentration at a certain distance from the surface as shown in FIG. 5, and approaches the surface. It becomes the thing which declined according to. Next, the SiN150 used for Ga diffusion shown above
Is removed, SiO ₂ 100 is formed again, and a window narrower than the width of the opening 15 shown in FIG. 3C is opened by photoetching.
Using Cl ₃ as a raw material, the n emitter layer 3 and the channel cut n ⁺ layer 5 as shown in FIG.
It is formed by time diffusion. As shown in FIG. 4, the n emitter layer 3 is formed to have substantially the same depth as the maximum impurity concentration position b of the p base layer 2. Next, after removing the back surface SiO ₂ film 100 formed in the step of FIG. 3D to form the structure of FIG. By driving in an oxygen atmosphere for 5 hours, a p-emitter layer 4 is formed as shown in FIG. Finally, a window is opened by ordinary photoetching so as to expose a desired position of the p base layer 2, the n emitter layer 3, and the p emitter layer 4 in contact with the electrodes, and a metal such as aluminum is vapor-deposited. As shown, a gate electrode 200, a cathode electrode 300, and an anode electrode 400 are formed. The part where impurities are not diffused is shown as the n-base layer 1a of GTO.

As a result of being manufactured by the method described in this embodiment, the breakdown voltage of the EB junction between the n emitter layer 3 and the p base layer 2 is about 20.
The breakdown voltage of the main junction between the V, p base layer 2 and the n base layer 1a was about 400 V, and a gate turn-off thyristor with excellent turn-off performance could be obtained.

The method of obtaining the impurity concentration distribution of the present invention is not limited to the manufacturing process shown in FIG.

〔The invention's effect〕

As described above, according to the present invention, the reverse breakdown voltage is high in the pn junction of the planar structure formed by the n emitter layer and the p base layer, the surface is stabilized, and the sheet of the p base layer in the junction formation is formed. By significantly improving the control of resistance, it is possible to obtain a semiconductor device with excellent turn-off performance such as an increase in the maximum controllable current, a reduction in turn-off time, and a reduction in turn-off charge when applied to gate turn-off thyristors and transistors. It is possible.

[Brief description of drawings]

FIG. 1 is a schematic sectional view of a main junction portion of a conventional planar type thyristor or transistor, and FIG. 2 is a- in FIG.
FIG. 3 is a diagram showing an impurity concentration distribution on the line bc, FIG. 3 is a diagram showing one conventionally known impurity concentration distribution, and FIG. 4 is an outline of a main junction portion of a planar semiconductor device manufactured by the manufacturing method of the present invention. FIGS. 5 and 6 are sectional views, FIG. 7 and FIG. 7 showing the p-type impurity concentration distributions on the lines abc and a'-b'-c 'in FIG. 1 ... Semiconductor substrate, 1a ... Collector layer (n base layer), 2
... p base layer, 3 ... n emitter layer, 40 ... EB junction, 5
0 ... Main junction.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Hideo Honma 3-1-1 Sachimachi, Hitachi City, Ibaraki Prefecture Hitachi Research Laboratory, Hitachi Ltd. (56) References JP-A-50-38475 (JP, A) JP-A-51-149779 (JP, A)

Claims (1)

[Claims] 1. A layer having a first opening on one main surface of a semiconductor substrate of the first conductivity type, through which impurities of the second conductivity type can easily pass, and a layer on which a second electrically conductive type impurity hardly penetrates. A step of forming a first insulating film made of, and guiding a second conductive type impurity into the semiconductor substrate through the first opening of the first insulating film to form a second conductive type first semiconductor region. Steps, and a layer through which impurities easily pass through the first opening of the first insulating film and a layer through which impurities of the second conductivity type do not easily pass through are formed to cover the entire main surface of the semiconductor substrate. A step of covering the semiconductor substrate again with a second insulating film composed of a layer through which impurities of the second conductivity type easily pass and a layer overlying the layer through which impurities of the second conductivity type hardly pass, and the semiconductor substrate in the first semiconductor region Heating at a temperature sufficient to diffuse impurities of the second conductivity type; Forming a second opening in the insulating film to expose a part of the first semiconductor region, and heating the semiconductor substrate again at a temperature sufficient to diffuse impurities of the second conductivity type in the first semiconductor region, Thereby, a step of outwardly diffusing the second conductivity type impurity from the second opening to recede the maximum impurity concentration position of the portion exposed in the second opening of the first semiconductor region from one main surface of the semiconductor substrate to the inside. After removing the second insulating film, a step of forming a third insulating film on the entire main surface of the semiconductor substrate through which impurities of the first conductivity type are less likely to pass, and a second opening of the third insulating film. Forming a third opening smaller than the second opening at substantially the same position, and guiding impurities of the first conductivity type into the first semiconductor region of the semiconductor substrate through the third opening of the third insulating film. , The first conductivity type of the same depth as the maximum impurity concentration position of the first semiconductor region And a step of forming a second semiconductor region, the method of manufacturing a planar semiconductor device.