JPH065684A - Ic wafer, test device therefor, and test element group - Google Patents

Abstract

PURPOSE:To enable addresses to be automatically and accurately set up to effective chips without changing them in number per wafer. CONSTITUTION:Chips C1 to C6 provided with one or more specific pads whose positions are the same with effective chips are provided outside an effective chip region in a wafer 100, and the chips C1 to C6 are so constituted as to enable their specific pad groups to indicate prescribed data which represent the positions of effective chips.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an IC wafer provided with a chip constructed so that when a chip address is required for testing an IC wafer, the origin of the address can be determined in the wafer.

Further, the present invention is a test element group (TEG; TEST ELEMENT GROUP, for extracting a parameter of a device used for circuit simulation).
Hereinafter referred to as TEG).

[0003]

2. Description of the Related Art The first prior art of the present invention will be described below.

Since an IC has many input / output terminals, it is necessary to measure many items in order to inspect its electrical characteristics, and various measurements and inspections are performed in the IC manufacturing process. Particularly in the measurement in the wafer state, the probe of the probe card is automatically brought into contact with the pad of each chip by the prober, and the electrical test of each chip is performed by the tester connected to the probe.

Here, when setting a chip address within a wafer, a prober and a tester with an X and Y coordinator are used, and the stage of the prober is first adjusted to a certain set address, and an absolute value from that is set. The address was output from the address or the relative address. Or, it was manually adjusted to the specified address chip.

The second prior art of the present invention will be described below.

The TEG is manufactured in all steps or partial steps of the IC manufacturing process, and its purpose is to perform various electrical measurements to monitor actual device characteristics or circuit characteristics.

Conventional TEG for device parameter extraction
Consisted of active devices such as transistors, passive devices such as resistors and capacitors, and parasitic devices such as wiring capacitors and wiring resistors. In addition to these device parameter extracting TEGs, there is a circuit for verifying the extracted parameters such as a ring oscillator.

[0009]

However, in the first prior art of the present invention, the alignment of the initial stage has large variations due to visual observation, and the position with respect to the reference probe card and the pattern of the wafer itself. Since the reference address is shifted due to the shift (overall), it may not match the reference chip (= reference address) when it is taken as a chip, and erroneous data may be taken. In addition, when the origin is manually adjusted to the reference chip, it is possible with a small amount to some extent, but when the number increases, the load will increase unless automatic measurement is performed, and it will not be possible.

In the second prior art of the present invention,
If there is the above TEG, the device parameters can be extracted and verified for the time being, but since the active device and the passive device originally have parasitic devices,
The method of determining the parameters of active devices, passive devices and parasitic devices is not unique.

The test elements incorporated in the TEG for device parameter extraction are not assumed for all circuit simulations of a circuit including the device. Therefore, in the circuit simulation in the case where it is not included in the TEG, there is a problem that the accuracy and precision of the circuit simulation are deteriorated by using the accuracy and precision parameters extracted from the device parameter extraction TEG. .

The problem of deterioration of accuracy and precision of the circuit simulation is naturally reflected in the design of the IC, which leads to deterioration of the performance and reliability of the IC and increase of cost.

[0013]

The problems of the first prior art described above are solved by the following IC wafer and inspection device.

In the first IC wafer of the present invention, a plurality of chips having one or more specific pad positions which are the same as the positions of the effective chips are provided outside the effective chip region in the wafer, and the plurality of chips are specified. Each pad is configured so that the pad group of (4) indicates predetermined information indicating the position of the effective chip.

The first inspection device of the present invention is the first inspection device of the present invention.
The effective chip address is set based on the predetermined information read by the plurality of chips of the IC wafer.

In the second IC wafer of the present invention, two or more specific pad positions are the same as the effective chip positions outside the effective chip area in the wafer, and the two or more specific pads are effective chips. The chip is provided so as to show predetermined information indicating a position.

The second inspection device of the present invention is the second inspection device of the present invention.
The effective chip address is set based on the predetermined information read by the chip of the IC wafer.

Here, the effective chip area means a wafer area on which product chips can be formed.

The problems of the second prior art are as follows.
Will be solved by.

The first TEG of the present invention is characterized in that, in a test element including an active device and a parasitic device, a plurality of test elements having different ratios of the two devices are provided.

A second TEG of the present invention is a test element including a passive device and a parasitic device, and has a plurality of test elements in which the ratio of the two devices is changed.

A third TEG of the present invention is a test element including an active device, a passive device and a parasitic device, wherein a plurality of test elements having different ratios of at least one of the active device and the passive device to the parasitic device. It is characterized by having.

A fourth TEG of the present invention is the test element according to any one of the first to third TEGs described above, an active device in which a parasitic device portion is suppressed, a passive device in which a parasitic device portion is suppressed, and a parasitic device. And at least one device of the above.

A fifth TEG of the present invention includes a test element for extracting device parameters of a single device, and
The present invention is characterized in that it includes a plurality of test elements for evaluating a parasitic effect with different magnitudes of the parasitic effect.

[0025]

[Operation] The IC wafer of the present invention is provided with a chip serving as a reference for alignment in the wafer in order to ensure the alignment accuracy of the prober and the probe card.

The first IC wafer and the first inspection apparatus using the same according to the present invention have one or two or more specific pads having a predetermined characteristic (for example, a short state or an open state) outside the effective chip area. A plurality of chips configured with simple characteristics such that the specific pad group of the plurality of chips indicates predetermined information indicating the position of the effective chip, and the predetermined information is read to read the wafer. The origin address in is determined. In such a configuration,
Since the chip is provided outside the effective chip area, the origin address in the wafer can be accurately and automatically determined by changing the characteristic of the specific pad to a simple characteristic without changing the number of chips to be obtained. Moreover, since the predetermined information is read from the plurality of chips, the predetermined information can be read more accurately.

The second IC wafer of the present invention and the second inspection apparatus using the same show the predetermined information indicating the position of the effective chip by two or more specific pads outside the effective chip area (for example, , A short state, an open state, and other simple characteristics are combined to form predetermined information indicating the position of an effective chip), a chip is provided, and the information of this chip is read to determine the origin address in the wafer. With such a configuration, the origin address in the wafer can be accurately and automatically determined without changing the number of chips taken.

In the TEG of the present invention, not only the active device and the parasitic device, the passive device and the parasitic device, or the active device and the passive device and the parasitic device are separately put into the TEG, but also the ratio of each device is continuously changed. By preparing a plurality of test elements, active device parameters and / or passive device parameters extracted from the active device, the passive device, or the active device and the passive device, and extracted from the parasitic device. By matching with parasitic device parameters, it is possible to realize circuit simulation with higher accuracy and precision.

[0029]

EXAMPLES Examples of the present invention will be described in detail below.

First, the IC wafer and the inspection apparatus of the present invention will be described.

FIG. 1 is a schematic plan view showing a chip structure of an embodiment of an IC wafer according to the present invention. Figure 2 (a)
[Fig. 2] is a partially enlarged view of a portion A in Fig. 1.

As shown in FIGS. 1 and 2A, outside the effective chip area S where the product chips (effective chips) of the IC wafer 100 are arranged, in accordance with the movement of the prober for inspecting the wafer (X is a prober). The probing direction of _{No. 2} ) is shown), and chips C _{1 to} C ₆ for valid chip origin confirmation whose characteristics are changed from those of the valid chips are arranged. In FIG. 1, a chip area Sout indicates an area in which chips for valid chip origin confirmation are arranged. Since the effective chip origin confirmation chip measures the characteristics by the same probe card as the effective chip, at least the positions of the specific pads P _{1 to} P ₃ are made the same, but the chips do not necessarily have the same size.

Here, an example of the internal structure of the pad of the effective chip and its characteristics are shown in FIG. 3A, and an example of the internal structure of the specific pad of the chip for origin confirmation and its characteristics are shown in FIG. 3B.
It shows in (c). 3B shows a case where the specific pad is short-circuited, and FIG. 3C shows a case where the specific pad is open.

In the above-mentioned origin confirmation chip, the characteristics of the _second pad P ₂ are checked at the beginning of the inspection, and data other than short circuit is set to "O". Short (Figure 3
In the case of (b)), another pad P ₁ , which has the characteristics of the short circuit of FIG. 4A or the open circuit of FIG.
Measured between P ₃ a (1-3), if this part is also short "S", leaving the data as if open "O". In this way, the plurality of pads are recognized in order to prevent erroneous recognition. Chips C _{1 to} C ₆ are respectively “O”,
The pads P ₂ , P ₁ and P ₃ are set so that the data of “O”, “S”, “O”, “O” and “S” can be obtained, and the data obtained by one chip is 2C, the _third chip C ₃ in FIG. 2A has “O-O-O-S”, and the fourth chip C ₄ has “O-O-S”.
-S-O "and the sixth chip C _6" S-O-
OS ”. In this embodiment, this "S-O-O-
The area where the data of "S" is obtained is arranged only in this area, and the next chip having the data of "S-O-O-S" is regarded as an effective chip and is designated for each wafer as the address origin.

The number of chips, the pads used for judgment, the characteristics thereof, the position of incorporation in the wafer, etc. can be arbitrarily changed.

In the IC wafer described above, the characteristics of the second pad of each chip are checked, and the first pad and the third pad are checked to prevent erroneous recognition. When the synthesized data of the characteristic pad becomes specific data, the next chip is regarded as an effective chip. However, as shown in FIG. 2B, four predetermined pads P in one chip C ₆ ′ are used. The characteristics of _{1 to} P ₄ are “S-O-O”
It is also possible to regard the next chip C ₇ ′ as an effective chip when it becomes “−S”. In this case, in order to prevent erroneous recognition, it is of course possible to regard the next chip as an effective chip when the chips having the pad characteristics of "S-O-O-S" are continuously measured.

Next, the inspection device used for the IC wafer will be described. Here, the case of the chip arrangement of FIG. 2A will be described as an example, but the same applies to the case of the chip arrangement of FIG. 2B.

As described above, in the measurement by the inspection device in the wafer state, the probe of the probe card is automatically brought into contact with the pad of each chip by the prober, and the tester connected to the probe is used to measure each chip. Conduct electrical test.

FIG. 5 is a flow chart showing the address judgment operation by the inspection device of the present invention.

First, measurement for address judgment is included in the program of the inspection device, and the test is carried out. That is, as shown in FIGS. 1 and 2, the probe provided on the outside of the effective chip area is brought into contact with the stylus of the probe card to measure the characteristic of the specific pad of the chip (F ₁ ).

Next, the measurement result is converted into a variable used for judgment (F ₂ ). For example, if the specific pad is short-circuited, the data is "S", and if it is open, the data is "O".

Next, it is combined with the data for the previous three chips (F
₃ ) Confirm whether or not it is an address judgment variable (F ₄ ).
Here, when the address determination variable is "S-O-O-S", if the previous combined data is "O-O-S-O" and the measured value this time is "O", the combined data " OS-O-
Since it is "O" and does not match the address determination variable, the same measurement is performed in the next chip. The next data is "S"
Then, the combined data becomes "S-O-O-S", which matches the address determination variable.

If the synthesized data coincides with the address judgment variable, the address judgment measurement is stopped, the address is started from this portion, the relative address or the absolute address is designated (F ₅ ), and the prober is moved. And perform a normal test (F ₆ ). The operation of moving the prober and performing a normal test is repeated in the wafer, and when one wafer is completed (F ₇ ), the next wafer is inspected by the same operation.

Next, the TEG of the present invention will be described.

FIG. 6 is a sectional view showing the structure of the first embodiment of the TEG of the present invention.

In this embodiment, the length of the wiring portion forming the parasitic device (parasitic capacitance) is changed to change the composition ratio of the active device and the parasitic device.

As shown in FIG. 6, a P-type silicon substrate 12
An N ⁺ buried layer 13 is provided on the N ⁻ region 14 (which constitutes a part of the collector) separated by an isolation 15 and an emitter 19, a base 18 and a collector 16 are provided, and an NPN bipolar transistor ( B
JT) 11.

Each wiring 21 of the emitter region 19, the base region 18, and the collector region 16 is led out to each pad 22 (only the pad of the emitter region 19 is not shown). The wiring 21 in the isolation region 31 is mainly formed between the isolation region 15 and the oxide film 17, 2.
It has a parasitic capacitance of zero.

In this embodiment, the lengths L _E , L _B , and L _C (L _E , L _B , and L _C ) of the wiring 21 on the isolation 15 connecting between the NPNBJT 11 and the pad 22 are the emitter region 19 and the base, respectively. The lengths of the wirings 21 connected to the region 18 and the collector region 16 are shown. Only L _E is not shown in FIG. 6), each of which is shaken at intervals of 100 μm from 0 μm to 400 μm. 3 = 15
The standard is prepared.

It is desirable that the boundary line 32 between the NPNBJT 11 and the isolation region 31 is set to half the minimum width of the isolation 15 used in the integrated circuit. Thus, the active device NPNBJT1
By separating 1 and the isolation region 31 which is a parasitic device, the device parameters extracted by using the TEG of this embodiment exert their effectiveness for a wider range of integrated circuits. That is, NPNBJT
Even if 11s are arranged closely or roughly, it becomes very easy to estimate the influence of these parasitic devices.

Even if the length L _E of the wiring 21 of the emitter 19 is changed, since the emitter potential is close to the potential of the isolation 15, a parasitic effect does not occur so much. Therefore, as compared with the other two elements L _B and L _C , the priority (importance) can be lowered.

A method of optimizing each device parameter using the TEG of this embodiment will be described below. First, L _E , L
The DC characteristics of the active device NPNBJT11 are measured using a device with _B and L _C = 0 μm. Measurement is D
Since it is C, the capacitance of the wiring 21 and the capacitance of the pad 22 do not cause a parasitic effect.

Next, the capacitance of the pad 22, which is the parasitic device, and the capacitance of the wiring 21 are measured from another TEG. This is a known technique, each ~ 500 fF, ~
A value of 0.1 fF is obtained.

[0054] Then _{(L E, L B, L} C) in each combination of measures the AC characteristics of the active device + parasitic devices. The characteristics of L _E , L _B , and L _C = 0 μm indicate the characteristics of the active device + pad described above. Other this as reference _{(L E, L B, L} C) for measuring the characteristics of the.

A circuit simulation is performed by using the active device parameters and the parasitic device parameters described above, assuming an appropriate equivalent circuit. This is also a known method.
This circuit simulation result is compared with the previous measurement result.

If the two results are close, there is no problem.
If the two values are significantly different, it is necessary to consider other factors that were overlooked. At that time, since five lengths L _E , L _B , and L _C of the wiring that represent the parasitic effect are continuously selected, it is easily determined whether or not the result of the mismatch is caused by these.

[0057] Similarly, _{L → 0μm (L = L E} , L B, L
_If the measured values extrapolated in _C ) are significantly different from the simulation results using the NPNBJT parameters, it is necessary to review the parameters.

In the integrated circuit, not only the case of using L = 0 μm, but also the case of using various L occurs. Therefore, as the parameter of the NPNBJT 11, it is necessary to select an extrapolated value of L → 0 μm or a parameter such that the result of the circuit simulation and the actually measured value are the best for the most frequently used L.

If the capacitance of the pad 22 is too heavy and the influence of the wiring capacitance or the like cannot be observed with sufficient accuracy, a probe means such as an EB (ELECTRON BEAM) probe, which can ignore the probe capacitance, is used. The size of the pad may be reduced, or the pad may be removed to perform the measurement.

As a second embodiment of the present invention, each wiring 2 is used instead of the wiring routed to the region on the isolation.
It is conceivable that one has a coupling capacitance. For example, by configuring a parasitic device (parasitic capacitance) by running parallel in close proximity to each other between wirings, and changing the length of the wiring section to run in parallel,
The composition ratio of the active device and the parasitic device can be changed.

As shown in FIG. 7, the TEG of this embodiment is N
In each wiring 46 drawn out from the emitter 45, the base 44, and the collector 43 of the PNBJT 41, the base wiring and the collector wiring have a pattern in which some of them run in parallel. In the TEG of this embodiment, the parallel running distance L _BC (shown in FIG. 7) is 1 between 0 μm and 400 μm.
A total of 5 levels are provided at intervals of 00 μm. A parasitic capacitance is generated between the parallel wirings.

Since the parallel running section is on the isolation 42, it naturally has the parasitic capacitance as described above.

The method of extracting and verifying each device parameter is the same as that described above.

The parasitic capacitance thus intentionally provided is the base-collector capacitance C _BC of the NPNBJT41 alone _.
It is also useful when estimating. That is, tentatively, NPNBJT41
Even when C _BC of C _BC is unknown, information about C _BC can be obtained by extrapolating the L _BC dependent characteristic.

Other parasitic capacitances, interlayer capacitances, and line capacitances can be obtained by the same method. At the same time, the parameters of the active device and the equivalent circuit suitable for circuit simulation can be obtained.

As a third embodiment of the present invention, a TEG for estimating the parasitic resistance instead of the parasitic capacitance can be considered. For example,
It is possible to change the composition ratio of the active device and the parasitic device by changing the number of contact structures forming the parasitic device (parasitic resistance).

As shown in FIG. 8, a wiring 56 is drawn from the emitter 55 of the NPNBJT 51, and N _B contact structures 58 with the wiring 57 are provided. N _B is from 0 to 100
In total, 5 levels are provided at intervals of 25 pieces. As a result, a parasitic resistance is added to the emitter 55. This emitter resistance seriously affects each characteristic. Therefore, it is very important to estimate the parasitic resistance as well as the resistance of the active device.

Unlike the capacitance case, DC measurements alone are sufficient to evaluate each device parameter. However, contact resistance may rarely show current density dependence, so care must be taken when using it at large currents.

As a fourth embodiment of the present invention, a case where an inductance is formed together with an active device can be considered.

Usually, there are few cases where an inductance is intentionally formed in an integrated circuit. However, various sensors,
Such a case can also be envisioned for micromachining and the like. In this case as well, take a plurality of examples of inductance values in the same manner, and compare the value obtained from the TEG consisting only of other independent parasitic devices with the value obtained from the TEG of the active / passive device + parasitic device. Thus, each device parameter suitable for circuit simulation and an equivalent circuit can be obtained.

As a fifth embodiment of the present invention, not only an active device but also an active device + passive device to which a parasitic element is added can be considered. For example, by changing the size of the parasitic device (diode), the composition ratio of the active / passive device and the parasitic device can be changed. Such an example is shown in FIG.

The example shown in FIG. 9 is a grounded-emitter circuit often used in bipolar transistor circuits.

The NPNBJT 61 has a P-type silicon substrate 63 together with a collector resistance (R _C ) 62 as a passive device.
Exists on. An equivalent circuit diagram is as shown in FIG. 9B, but a parasitic circuit shown by a dotted line is generated in the collector resistor 62. That is, the base diffusion layer 65 that forms the resistor
And N ^- P-N junction diode 69 between the type epitaxial layer 64, N ^- -type epitaxial layer 64 and the N-P junction diode 70 between the P-type silicon substrate 63 is formed.

Therefore, the equivalent circuit for performing the circuit simulation is the circuit shown in FIG. 9B.

The value R _C of the collector resistor 62 is substantially the same unless the number of sheets (L / W ratio) of the base diffusion layer 65 is changed. Therefore, it is possible to configure circuits that exhibit the same main characteristics and different parasitic effects.
In this embodiment, as a combination of sizes of the collector resistor 62, (L / W) = (10 μm / 2 μm), (20 μm
/ 4 μm), (30 μm / 6 μm), (40 μm / 8 μ
m), (50 μm / 10 μm), a total of 5 levels are provided. Since the sheet resistance of the base diffusion layer 65 is ˜1 kΩ / □, the value of R _C is approximately ˜5 kΩ.

In this embodiment, the area of the base diffusion layer 65 varies from 20 μm ² to 500 μm ² , and the depletion layer capacitance and the leakage current associated with the diode 69 are about 25 times larger. Change. In this embodiment, the diode 69 and the diode 70 have a parasitic effect. The method of extracting and verifying the parameters of each device is the same as in the above-described embodiment. First, device parameters are extracted for each of the NPNBJT 61, the P-N junction diode 69, and the N-P junction diode 70, which are single devices, and the measurement result of the above-described embodiment and the circuit simulation result using the parameter are compared. By doing so, the validity of the parameters and the equivalent circuit can be examined.

As a sixth embodiment of the present invention, it is possible to consider an example in which a plurality of sizes of the contact 71 with respect to the base diffusion layer 65 shown in FIG. .

In the present invention, the active device is not limited to the BJT, but the embodiment can be constructed in the same manner as long as it is a transistor such as JFET, MOSFET or the like which exhibits a widening action. The device may be other than the silicon device.

The parasitic device may have electrical characteristics other than R, C and L. For example, a capacitor structure, a wiring structure, or the like that traps and accumulates carrier charges and also has hysteresis can be considered. The parasitic device of the present invention means a device other than those intentionally designed, or a device which is not preferable, which is a problem when the active device is integrated in an integrated circuit, for example.

[0080]

As described in detail above, I of the present invention
According to the C-wafer, a chip for address setting having a simple characteristic (for example, open or short) is formed outside the wafer effective chip area, so that the number of chips can be accurately and accurately changed. The address of the effective chip can be set automatically. In this case, since the chip is manufactured in the same process as the effective chip, there is almost no increase in cost.

Further, according to the inspection apparatus of the present invention, the test program for judging the configuration of the IC wafer can be set easily and automatically and the in-wafer address can be set accurately.

According to the TEG of the present invention, not only the active device, the passive device and the parasitic device, but also the active device and the parasitic device, the passive device and the parasitic device or the active device, and the passive device and the parasitic device are combined. It is possible to evaluate the validity of the device parameters and the equivalent circuit used for circuit simulation by preparing multiple examples of circuits with different composition ratios of each device. Performance, high reliability, low cost I
C can be provided.

[Brief description of drawings]

FIG. 1 is a schematic plan view showing a chip structure of an example of an IC wafer according to the present invention.

FIG. 2 is a partially enlarged view of part A of FIG.

FIG. 3 is a structure and characteristic diagram of a measurement pad portion of each chip used in this embodiment.

FIG. 4 is a structural diagram of another measurement pad portion of each chip used in this embodiment.

FIG. 5 is a flowchart showing an address determination operation by the inspection device of the present invention.

FIG. 6 is a sectional view showing a configuration of a first embodiment of a test element group of the present invention.

FIG. 7 is a plan view showing the configuration of a second embodiment of the test element group of the present invention.

FIG. 8 is a sectional view showing the configuration of a third embodiment of the test element group of the present invention.

FIG. 9 is a sectional view and a circuit diagram showing the configuration of a fifth embodiment of the test element group of the present invention.

[Explanation of symbols]

100 IC wafer C ₁ -C ₆ origin confirmation chip C ₃ '~C _6' origin confirmation chip P ₁ to P ₄ specific pads 11,41,61 NPNBJT 12,52,63 P-type substrate 13 N ⁺ buried Embedded layer 14, 53, 64 N ^- Epitaxial layer 15, 42, 54 Isolation 16, 43 Collector 17 Oxide film 18, 44, 65 Base 19, 45, 55, 66 Emitter 20 Oxide film 21, 46, 56, 57, 67 wiring 22,68 pad 31 isolation region 32 boundary line 58 contact structure 62 collector resistance 69 PN junction diode 70 NP junction diode 71 contact

Claims (11)

[Claims] 1. A plurality of chips having one or more specific pad positions which are the same as the positions of the effective chips are provided outside the effective chip region in the wafer, and the specific pad groups of these plural chips are the effective chips. An IC wafer in which each chip is configured to show predetermined information indicating a position. 2. An inspection apparatus for setting an address of an effective chip based on predetermined information read by the plurality of chips of the IC wafer according to claim 1. 3. Outside the effective chip area in the wafer, two or more specific pad positions are the same as the effective chip position, and the two or more specific pads have predetermined information indicating the effective chip position. An IC wafer with chips built in as shown. 4. An inspection apparatus for setting an address of an effective chip based on predetermined information read by the chip of the IC wafer according to claim 3. 5. A test element group including a plurality of test elements having an active device and a parasitic device and having different ratios of the two devices. 6. A test element group including a passive device and a parasitic device, comprising a plurality of test elements having different ratios of the two devices. 7. A test element including an active device, a passive device and a parasitic device, wherein the test element has a plurality of test elements in which a ratio of at least one of the active device and the passive device to the parasitic device is changed. A group of test elements to be used. 8. The test element according to claim 5, at least one device selected from the group consisting of an active device having a suppressed parasitic device portion, a passive device having a suppressed parasitic device portion, and a parasitic device. And a test element group comprising: 9. A test element group, wherein the active device according to claim 5, claim 7, or claim 8 is a bipolar transistor. 10. The test device group according to claim 5, wherein the active device is an insulated gate field effect transistor. 11. A test element group including a test element for extracting a device parameter of a device, and a plurality of parasitic effect evaluation test elements having different magnitudes of parasitic effects.