CN117517781A - Wafer large-resistance test structure, test method and test system - Google Patents
Wafer large-resistance test structure, test method and test system Download PDFInfo
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Abstract
The application provides a wafer large-resistance test structure, a test method and a test system, which are applied to the technical field of wafer test, wherein a parallel capacitive branch is introduced into a large-resistance structure to be tested on a wafer to form a parallel test branch, and then the parallel test branch is used for measuring corresponding resistance values under alternating current signals with different frequencies by a measuring machine, so that the resistance values of the large-resistance structure to be tested are calculated according to measurement results, the large-resistance structure on the wafer can be tested, the test precision is high, the test process is simple, the test cost is low, the test cost is reduced, and the production efficiency and the production quality are improved.
Description
Technical Field
The application relates to the technical field of wafer testing, in particular to a wafer large-resistance testing structure, a testing method and a testing system.
Background
After the wafer is produced, the wafer is placed on a carrying platform, and the probe on the measuring platform is contacted with the wafer to measure the resistance value of each chip resistor on the wafer. However, since the number of chips on the wafer is large, it takes a long time to detect each chip resistance on the wafer, resulting in lower measurement efficiency of the wafer.
At present, in the electrical test and the reliability test of the WAT (Wafer Acceptance Test ), the wafer internal resistance is tested by using the WAT test structure, but due to the limitation of the precision of the measuring machine and the test method, some resistors with large resistance cannot be accurately measured, which seriously affects the production efficiency, quality, cost and the like of the wafer.
Based on this, a new resistance test solution is needed.
Disclosure of Invention
In view of this, the embodiments of the present disclosure provide a wafer large resistance test structure, a test method and a test system, which have a simple test structure, and can test a large resistance on a wafer, and ensure test accuracy and efficiency.
The embodiment of the specification provides the following technical scheme:
the embodiment of the present disclosure provides a wafer large resistance test structure, including: the first test pad, the second test pad and the capacitive branch;
the first test pad is connected to the first end of the large-resistance structure to be tested;
the second test pad is connected to the second end of the large-resistance structure to be tested;
the first end of the capacitive branch is connected with the first test pad, and the second end of the capacitive branch is connected with the second test pad, so that the capacitive branch and the large-resistance structure to be tested form a parallel test branch;
the first test bonding pad and the second test bonding pad are used for measuring the corresponding resistance values of at least two groups of alternating current signals of the parallel test branch circuits by the measuring machine, and the resistance value of the large-resistance structure to be measured is obtained through the following equation set:
wherein R is test The resistance value of the large-resistance structure to be measured; r is R C1 At a frequency f for the capacitive branch 1 Corresponding resistance under the action of a first group of alternating current signals; r is R C2 At a frequency f for the capacitive branch 2 Corresponding resistance under the action of a second group of alternating current signals; r is R 1 To measure the frequency f of the machine 1 The resistance value obtained by measuring the parallel test branch circuit is measured under the first group of alternating current signals; r is R 2 To measure the frequency f of the machine 2 And (3) measuring the obtained resistance value of the parallel test branch circuit under the second group of alternating current signals.
The embodiment of the specification also provides a wafer large resistance test structure, which comprises: the first test pad, the second test pad, the third test pad and the capacitive branch;
the first test pad is connected with the first end of the large-resistance structure to be tested and the first end of the capacitive branch;
the second test pad is connected to the second end of the capacitive branch;
the third test pad is connected to the second end of the large-resistance structure to be tested;
the first test pad and the second test pad are used for measuring capacitance values of the capacitive branch by the measuring machine; after the capacitance value of the capacitive branch is measured, the second test pad is connected with the third test pad so that the capacitive branch and the large-resistance structure to be measured form a parallel test branch, and the first test pad and the second test pad are used for measuring at least one group of alternating current signal corresponding resistance values of the parallel test branch by a measuring machine, wherein the resistance value of the large-resistance structure to be measured is obtained through the following equation:
wherein R is test The resistance value corresponding to the large resistance structure to be measured; r is R C1 At a frequency f for the capacitive branch 1 Corresponding resistance under the action of a group of alternating current signals,c is the capacitance value of the capacitive branch; r is the frequency f of the measuring machine 1 The resistance value measured for the parallel test branch is measured under a set of alternating current signals.
Preferably, in any one of the examples, the capacitive branches comprise capacitive branches disposed on a wafer.
Preferably, in any of the examples, the capacitive branch disposed on the wafer includes a capacitor disposed on the wafer.
Preferably, in any one of the examples, the first test pad and the second test pad are test pads in the WAT test project.
Preferably, in any one of the examples, when at least two sets of ac signal measurements are made, the frequencies of the sets of ac signals are in a multiple relationship.
The embodiment of the specification also provides a wafer large resistance test system, which is characterized by comprising a measuring machine, a probe card and the wafer large resistance test structure according to any one of the specifications;
when the wafer large-resistance test structure comprises a first test pad and a second test pad and the capacitive branch and the large-resistance structure to be tested form a parallel test branch, the measuring machine measures at least two groups of corresponding resistance values of alternating current signals of the parallel test branch through the probe card;
or when the wafer large-resistance test structure comprises a first test pad, a second test pad and a third test pad, when the second test pad is not connected with the third test pad, the measuring machine firstly measures the capacitance value of the capacitive branch through the probe card, and when the second test pad is connected with the third test pad, and the capacitive branch and the large-resistance structure to be tested form a parallel test branch, the measuring machine also measures the resistance value corresponding to at least one group of alternating current signals of the parallel test branch through the probe card.
Preferably, the metrology tool includes a tool for performing WAT testing.
The embodiment of the specification also provides a wafer large resistance test method, which is applied to the wafer large resistance test system according to any one of the specification, and the wafer large resistance test method comprises the following steps:
measuring at least two groups of alternating current signals or corresponding resistance values under at least one group of alternating current signals by using a measuring machine, wherein the parallel test branch is a parallel branch formed by a capacitive branch in a wafer large-resistance test structure and a large-resistance structure to be measured;
and calculating the resistance of the large-resistance structure to be measured according to the alternating current signal frequency used in measurement and the resistance obtained by measuring the parallel test branch.
Preferably, the measuring the corresponding resistance value of the parallel test branch by using the measuring machine for at least two sets of alternating current signals or at least one set of alternating current signals includes: and carrying out multiple measurements on the parallel test branches under the same group of alternating current signals by using a measuring machine, and determining the corresponding resistance value of the parallel test branches under the same group of alternating current signals according to the multiple measurement results.
Compared with the prior art, the beneficial effects that above-mentioned at least one technical scheme that this description embodiment adopted can reach include at least:
the parallel capacitive branch is introduced to the to-be-tested large-resistance structure on the wafer to form the parallel test branch, and then the parallel test branch is used for measuring corresponding resistance values under alternating current signals with different frequencies, so that the resistance value of the to-be-tested large-resistance structure is calculated according to the measurement result, the large resistance on the wafer can be tested, the test precision is high, the test process is simple, the test cost is low, the test cost is reduced, and the production efficiency and the production quality are improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a wafer large resistance test structure according to the present application;
FIG. 2 is a schematic diagram of another wafer large resistance test structure according to the present application;
FIG. 3 is a schematic diagram of a wafer large resistance test system according to the present application;
FIG. 4 is a flow chart of a wafer large resistance test method in the present application.
Detailed Description
Embodiments of the present application are described in detail below with reference to the accompanying drawings.
Other advantages and effects of the present application will become apparent to those skilled in the art from the present disclosure, when the following description of the embodiments is taken in conjunction with the accompanying drawings. It will be apparent that the described embodiments are only some, but not all, of the embodiments of the present application. The present application may be embodied or carried out in other specific embodiments, and the details of the present application may be modified or changed from various points of view and applications without departing from the spirit of the present application. It should be noted that the following embodiments and features in the embodiments may be combined with each other without conflict. All other embodiments, which can be made by one of ordinary skill in the art based on the embodiments herein without making any inventive effort, are intended to be within the scope of the present application.
It is noted that various aspects of the embodiments are described below within the scope of the following claims. It should be apparent that the aspects described herein may be embodied in a wide variety of forms and that any specific structure and/or function described herein is merely illustrative. Based on the present application, one skilled in the art will appreciate that one aspect described herein may be implemented independently of any other aspect, and that two or more of these aspects may be combined in various ways. For example, apparatus may be implemented and/or methods practiced using any number and aspects set forth herein. In addition, such apparatus may be implemented and/or such methods practiced using other structure and/or functionality in addition to one or more of the aspects set forth herein.
It should also be noted that the illustrations provided in the following embodiments merely illustrate the basic concepts of the application by way of illustration, and only the components related to the application are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of the components in actual implementation may be arbitrarily changed, and the layout of the components may be more complicated.
In addition, in the following description, specific details are provided in order to provide a thorough understanding of the examples. However, it will be understood by those skilled in the art that the present invention may be practiced without these specific details.
The existing scheme can only utilize the measuring machine to directly test the resistance value of the resistor on the wafer, but is limited by the reason of the measuring machine, the measurement of the large resistor on the wafer cannot be directly obtained by using the measuring machine, and the high-precision measurement result of the resistance value of the large resistor cannot be directly obtained by using the measuring machine.
In view of this, by conducting intensive research and improvement exploration on the measuring mechanism of the measuring machine and the resistance measuring circuit of the resistor, it is found that:
on the one hand, although various circuit forms are available in the prior art for accurately measuring the resistance of the resistor, the circuit forms often occupy a large circuit area, and the test circuits cannot be implemented on the wafer, so that the conventional test circuits cannot be basically applied to the resistance measurement of the large resistor on the wafer;
in both aspects, although the measuring machine can directly measure the resistance values of some resistors, the resistance values of the resistors are often moderate, so that the measuring machine is difficult to finish measurement of a large resistance value by firstly measuring the resistance values with the internal mechanism of the measuring machine.
Based on this, the embodiment of the present specification proposes a wafer large resistance test processing scheme: as shown in FIG. 1, although the resistance R of the large-resistance structure to be tested test The device is very large and cannot be obtained by direct measurement by using a measuring machine, but after the large resistor structure to be measured is connected with another auxiliary testing branch (such as the capacitive branch shown in fig. 1) in parallel, the large resistor junction to be measured and the auxiliary testing branch necessarily form a parallel testing branch, namely, the large resistor junction to be measured and the auxiliary testing branch are used as branch circuits in the parallel testing branch, so that according to the principle of parallel circuits, namely, the reciprocal of the corresponding resistance value of the parallel testing branch is necessarily equal to the sum of the reciprocal of the corresponding resistance values of the two branch circuits, at the moment, the reciprocal of the large resistor corresponding to the large resistor structure to be measured is necessarily not a large value, but is converted into a moderate value, and the reciprocal of the large resistor is converted into a moderate valueThe resistance corresponding to the parallel test branch can be ensured not to exceed the direct measurement range of the measuring machine as long as the resistance of the auxiliary test branch is moderately selected, so that the resistance corresponding to the parallel test branch can be directly measured by the measuring machine, and the measured resistance of the parallel test branch can be reversely calculated to obtain the resistance of the large-resistance structure to be measured.
It should be noted that, the resistance value of the auxiliary test branch should be selected appropriately, that is, the resistance value of the auxiliary test branch should not be too small nor too large, because when the resistance value is selected too small, the corresponding reciprocal of the auxiliary test branch in the parallel test branch is necessarily very large, at this time, the measuring machine is limited by itself too much, so that the corresponding resistance value of the parallel test branch cannot be measured, and when the resistance value is selected too large, because the auxiliary test branch is connected in parallel with the large-resistance structure to be measured, the auxiliary test branch easily introduces other effects to the resistance test of the large-resistance structure to be measured, thereby affecting the resistance test precision of the large-resistance structure to be measured.
In addition, the resistance of the parallel test branch formed by the auxiliary test branch and the large-resistance structure to be tested can be directly measured by using a measuring machine, so that the resistance of the large-resistance structure to be tested can be reversely calculated by using the measuring result if the resistance of the auxiliary test branch is known or the resistance of the auxiliary test branch is unknown but can be regularly changed along with the known test condition.
The following describes the technical solutions provided by the embodiments of the present application with reference to the accompanying drawings.
As shown in fig. 1, an embodiment of the present disclosure provides a wafer large resistance test structure, including: a first test PAD1, a second test PAD2, and a capacitive leg, wherein the capacitive leg is labeled Xc; the first test PAD PAD1 is connected to the first end of the large-resistance structure to be tested, and the large-resistance structure to be tested is marked as R test The method comprises the steps of carrying out a first treatment on the surface of the The second test PAD PAD2 is connected to the second end of the large-resistance structure to be tested; and the first end of the capacitive branch is connected with the first test PAD PAD1, the second end of the capacitive branch is connected with the second test PAD PAD2, and the capacitive branch and the large-resistance structure to be tested are formed at the momentAnd forming a parallel test branch.
In the above analysis, when the capacitive branch is used as the auxiliary test branch, since the resistance value of the capacitive device is related to the signal frequency, that is, the reactance value xc=2pi fC, C is the capacitance value, and f is the signal frequency, the resistance value of the large-resistance structure to be tested can be obtained by solving the equation set by using at least two measurement results corresponding to the parallel test branch without knowing the capacitance value of the capacitor.
Specifically, the first test PAD1 and the second test PAD2 are used for measuring resistance values corresponding to at least two groups of alternating current signals of the parallel test branch by a measuring machine (not shown in fig. 1), so that two groups of measured values can be obtained, and resistance values of the large-resistance structure to be measured are obtained through the following equation set:
wherein R is test The resistance value of the large-resistance structure to be measured; r is R C1 At a frequency f for the capacitive branch 1 Corresponding resistance under the action of a first group of alternating current signals; r is R C2 At a frequency f for the capacitive branch 2 Corresponding resistance under the action of a second group of alternating current signals; r is R 1 To measure the frequency f of the machine 1 The resistance value obtained by measuring the parallel test branch circuit is measured under the first group of alternating current signals; r is R 2 To measure the frequency f of the machine 2 And (3) measuring the obtained resistance value of the parallel test branch circuit under the second group of alternating current signals.
It should be noted that in the above test, it is assumed that the capacitance value of the capacitive branch is unknown, and thus even R C1 、R C2 As an unknown, but since the ac signal frequencies f1, f2 are known, R in the test C1 And R is R C2 The relation is necessarily related to the relation between f1 and f2, so that the resistance R corresponding to the large-resistance structure to be measured can be calculated back by utilizing the two groups of resistance measurement results corresponding to the parallel test branches test 。
It should be noted that the measuring machine may be an existing machine for WAT test, or may be another machine capable of measuring resistance, which is not limited herein.
In summary, only the auxiliary test branch (such as the capacitive branch illustrated in fig. 1) with a simple structure is needed to be connected in parallel to the large-resistance structure to be tested in the test, so that the large resistance of the large-resistance structure to be tested is converted into a moderate reciprocal of the numerical value, and the reciprocal belongs to a part of the reciprocal of the resistance in the parallel test branch, so that the large resistance is represented as a parameter which can be calculated after the test on the parallel test branch.
In some examples, the test pads in the various examples in this application may be test pads in the WAT test project, as the wafer needs to be WAT tested, i.e., electrical performance and reliability tests.
It should be noted that, in wafer production, WAT is a common test item for testing a predetermined test structure, and a test structure (testkey) may be often disposed in a scribe line of a wafer, where a test probe is used to prick a test PAD for testing.
Accordingly, the test pads, branches, and the like, which are referred to in the test structure, may be circuit elements, circuit structures, and the like that are provided on the wafer (or in the scribe line of the wafer).
In an example, the capacitive branch used as the auxiliary test branch may be a capacitive branch disposed on the wafer, so that the resistance of the capacitive branch can follow the frequency variation characteristic of the test signal, so that the resistance of the parallel test branch can also vary according to the signal frequency, and the measurement of the resistance of the parallel test branch at different signal frequencies can be completed by using the measurement machine. Even if the resistance value of the capacitive branch is unknown, the large resistance value to be measured can be obtained through back calculation by a plurality of groups of measurement results.
In one example, the capacitive branch includes a capacitor, i.e., the capacitive branch may be a branch formed of a capacitor, further simplifying the circuit structure and circuit form of the auxiliary test branch, reducing the circuit area required for the auxiliary test branch, and making the test structure easier to implement on a wafer (or dicing channel of a wafer).
In one example, the first test pad, the second test pad, etc. in the test structure may be formed from a plurality of test pads within the scribe line of the wafer. In a specific implementation, the PADs of the first test PAD1, the second test PAD2 and the like are test PADs in the WAT test project.
In some embodiments, the capacitive branch is used as the parallel branch of the large-resistance structure to be measured, so that the resistance of the capacitive branch is not required to be known in advance, and only when at least two groups of alternating current signals are measured, the proportional relationship, such as the multiple proportional relationship, between the frequencies of the groups of alternating current signals is maintained, so that the inverse calculation is very conveniently performed.
For example, since the impedance Xc of the capacitive branch has the following relation with the frequency f, the capacitance C: xc=1/(2pi fC), so only 2f needs to be set in measurement 1 ＝f 2 X is then C1 ＝2X C2 In the formula, R is present C1 ＝2R C2 Here, the impedance Xc is marked as a resistance value R C No distinction is made in this application.
Based on the same inventive concept, the embodiment of the present disclosure further provides a wafer large resistance test structure, i.e. the resistance value of the large resistance structure to be tested can be calculated by combining the constant resistance value of the capacitive branch with at least one set of measured resistance values.
As shown in fig. 2, a wafer large resistance test structure includes: a first test PAD1, a second test PAD2, a third test PAD3, and a capacitive leg. The first test PAD PAD1 is connected with the first end of the large-resistance structure to be tested and the first end of the capacitive branch; the second test PAD PAD2 is connected to the second end of the capacitive branch; the third test PAD3 is connected to the second end of the large-resistance structure to be tested.
First, the second test PAD2 and the third test PAD3 are not connected (the broken line shown in fig. 2 is used to represent the unconnected state), and the first test PAD1 and the second test PAD2 are used to measure the capacitance value of the capacitive branch by the measuring machine, where the measuring machine can measure the accurate capacitance value C corresponding to the capacitive branch by using the mechanism of the capacitance value c=q/V.
Then, after the capacitance value of the capacitive branch is measured, the second test PAD2 and the third test PAD3 are connected, that is, the second test PAD2 and the third test PAD3 after connection are equivalent to the second test PAD2 illustrated in fig. 1, that is, the structure of fig. 2 is similar to the structure of fig. 1, the capacitive branch and the large-resistance structure to be tested form a parallel test branch, so that the first test PAD PAD1 and the second test PAD PAD2 (because the second test PAD PAD2 and the third test PAD PAD3 are short-circuited, the third test PAD PAD3 can also be used here) are used for measuring at least one group of alternating signal corresponding resistance values of the parallel test branch by the measuring machine.
Therefore, the resistance value of the large-resistance structure to be measured is obtained by the following equation:
wherein R is test The resistance value corresponding to the large resistance structure to be measured; r is R C1 At a frequency f for the capacitive branch 1 Corresponding resistance under the action of a group of alternating current signals,c is the capacitance of the capacitive branch, which is accurately measured by the measuring machine, so R is as long as the frequency f1 is determined C Can be determined; r is the frequency f of the measuring machine 1 The resistance value measured for the parallel test branch is measured under a set of alternating current signals.
Through adding a test PAD in the test structure, the capacitor C can be measured simultaneously, and the capacitor C can be converted into the test structure illustrated in the foregoing figure 1 after PAD2 and PAD3 are connected in series, so that the area of the test structure can be remarkably saved under the condition of increasing the test function, and the capacitor C can be deployed in the middle of wafer test more easily.
In some embodiments, in any of the foregoing examples, the measurement performed by the measurement machine may be measured multiple times under the same test condition, so that measurement results closer to the actual value are formed by using the multiple measurement data, for example, the measurement results under the same condition are obtained by taking an average value.
In some embodiments, in any of the foregoing examples, the number of measurement signal sets of the ac signal performed by the measuring machine may be more than one, two or more times, so that the R closer to the true value may be obtained by using more times of data test 。
It should be noted that, in the foregoing respective examples corresponding to fig. 1, the embodiments of fig. 2 may also be used, for example, the capacitive branch is disposed on the wafer (or the scribe line of the wafer), and the capacitive branch is preferably formed by a capacitor, which is not listed here.
Based on the same inventive concept, the embodiments of the present disclosure also provide a wafer large resistance test system, so that the result of the wafer large resistance is automatically obtained by using the test system.
As illustrated in fig. 3, a wafer large resistance test system includes a metrology tool 10, a probe card 20, and a wafer large resistance test structure 30 as described in any of the examples herein.
It should be noted that, when the wafer large-resistance test structure 30 includes a first test pad and a second test pad, and the capacitive branch and the large-resistance structure to be tested form a parallel test branch, the measuring machine 10 measures the resistance corresponding to at least two groups of alternating current signals of the parallel test branch through the probe card 20.
Therefore, after at least two sets of measurement results are obtained, a large resistance value can be calculated by the equation set (see the equation set of the foregoing example).
Or, when the wafer large-resistance test structure includes the first test pad, the second test pad and the third test pad, when the second test pad is not connected with the third test pad, the measuring machine 10 measures the capacitance value of the capacitive branch through the probe card 20, and when the second test pad is connected with the third test pad and the capacitive branch and the large-resistance structure to be tested form the parallel test branch, the measuring machine 10 also measures the resistance value corresponding to at least one group of alternating current signals of the parallel test branch through the probe card 20.
Thus, since the capacitance value C involved in the test can be measured, a large resistance value can be calculated by an equation (see the equation of the foregoing example) using at least one set of measurement results.
In the above examples, the specific structure of the wafer large resistance test structure 30 may be referred to in the above respective corresponding implementation examples, and the probe card 20 may be a probe of the measuring machine 10 for wafer testing, which are not described herein.
Furthermore, the measuring machine comprises a machine for performing WAT test, i.e. the WAT test can be directly used for testing without equipment cost, and the WAT measuring equipment is used for ensuring the precision.
Based on the same inventive concept, the embodiment of the present disclosure further provides a method for testing a large resistance of a wafer, which is applied to the system for testing a large resistance of a wafer described in any one of the foregoing examples, so that different ac signals are applied to a test structure by a measurement machine to measure a resistance.
As illustrated in fig. 4, the wafer large resistance testing method includes:
step S202, measuring at least two groups of alternating current signals or corresponding resistance values under at least one group of alternating current signals by using a measuring machine, wherein the parallel test branch is a parallel branch formed by a capacitive branch in a wafer large-resistance test structure and a large-resistance structure to be measured.
For example, an ac signal with a frequency f1 is first used to measure, and the resistance value of the parallel test branch is measured to be R1;
then, continuously using an alternating current signal with the frequency f2, and measuring the resistance value of the parallel test branch circuit as R2;
assuming f1=2f2, since the capacitance resistance rc=1/(2pi fC), R is present C1 ＝2R C2 The large resistance R can be back calculated by taking the formula set of the previous example test 。
And S204, calculating to obtain the resistance of the large-resistance structure to be measured according to the alternating current signal frequency used in measurement and the resistance obtained by measuring the parallel test branch.
It should be noted that, the test structure, the calculation process, and the like may refer to the foregoing respective corresponding implementation examples, and are not further expanded herein.
In some embodiments, more sets of metrology data may be used to obtain a larger resistance value that is closer to the true value. Specifically, the measuring machine measures at least two groups of alternating current signals or corresponding resistance values under at least one group of alternating current signals of the parallel test branch circuit includes: and carrying out multiple measurements on the parallel test branches under the same group of alternating current signals by using a measuring machine, and determining the corresponding resistance value of the parallel test branches under the same group of alternating current signals according to the multiple measurement results.
The processing of the plurality of sets of data may be an average value, a smoothing filter, or the like, which is not particularly limited herein.
In this specification, identical and similar parts of the embodiments are referred to each other, and each embodiment focuses on the differences from the other embodiments. In particular, the description is relatively simple for the embodiments described later, and reference is made to the description of the foregoing embodiments for relevant points.
The foregoing is merely specific embodiments of the present application, but the scope of the present application is not limited thereto, and any changes or substitutions easily conceivable by those skilled in the art within the technical scope of the present application should be covered in the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.
Claims (10)
1. A wafer large resistance test structure, comprising: the first test pad, the second test pad and the capacitive branch;
the first test pad is connected to the first end of the large-resistance structure to be tested;
the second test pad is connected to the second end of the large-resistance structure to be tested;
the first end of the capacitive branch is connected with the first test pad, and the second end of the capacitive branch is connected with the second test pad, so that the capacitive branch and the large-resistance structure to be tested form a parallel test branch;
the first test bonding pad and the second test bonding pad are used for measuring the corresponding resistance values of at least two groups of alternating current signals of the parallel test branch circuits by the measuring machine, and the resistance value of the large-resistance structure to be measured is obtained through the following equation set:
wherein R is test The resistance value of the large-resistance structure to be measured; r is R C1 At a frequency f for the capacitive branch 1 Corresponding resistance under the action of a first group of alternating current signals; r is R C2 At a frequency f for the capacitive branch 2 Corresponding resistance under the action of a second group of alternating current signals; r is R 1 To measure the frequency f of the machine 1 The resistance value obtained by measuring the parallel test branch circuit is measured under the first group of alternating current signals; r is R 2 To measure the frequency f of the machine 2 And (3) measuring the obtained resistance value of the parallel test branch circuit under the second group of alternating current signals.
2. A wafer large resistance test structure, comprising: the first test pad, the second test pad, the third test pad and the capacitive branch;
the first test pad is connected with the first end of the large-resistance structure to be tested and the first end of the capacitive branch;
the second test pad is connected to the second end of the capacitive branch;
the third test pad is connected to the second end of the large-resistance structure to be tested;
the first test pad and the second test pad are used for measuring capacitance values of the capacitive branch by the measuring machine; after the capacitance value of the capacitive branch is measured, the second test pad is connected with the third test pad so that the capacitive branch and the large-resistance structure to be measured form a parallel test branch, and the first test pad and the second test pad are used for measuring at least one group of alternating current signal corresponding resistance values of the parallel test branch by a measuring machine, wherein the resistance value of the large-resistance structure to be measured is obtained through the following equation:
wherein R is test The resistance value corresponding to the large resistance structure to be measured; r is R C1 At a frequency f for the capacitive branch 1 Corresponding resistance under the action of a group of alternating current signals,c is the capacitance value of the capacitive branch; r is the frequency f of the measuring machine 1 The resistance value measured for the parallel test branch is measured under a set of alternating current signals.
3. The wafer large resistance test structure according to claim 1 or 2, wherein the capacitive branch comprises a capacitive branch disposed on the wafer.
4. The wafer large resistance test structure of claim 3, wherein the capacitive branch disposed on the wafer comprises a capacitor disposed on the wafer.
5. The wafer large resistance test structure according to claim 1 or 2, wherein the first test pad and the second test pad are test pads in WAT test program.
6. The wafer large resistance test structure according to claim 1 or 2, wherein frequencies of the plurality of sets of alternating current signals are in a multiple relationship when at least two sets of alternating current signal measurements are performed.
7. A wafer large resistance test system, comprising a measurement machine, a probe card, and a wafer large resistance test structure according to any one of claims 1-6;
when the wafer large-resistance test structure comprises a first test pad and a second test pad and the capacitive branch and the large-resistance structure to be tested form a parallel test branch, the measuring machine measures at least two groups of corresponding resistance values of alternating current signals of the parallel test branch through the probe card;
or when the wafer large-resistance test structure comprises a first test pad, a second test pad and a third test pad, when the second test pad is not connected with the third test pad, the measuring machine firstly measures the capacitance value of the capacitive branch through the probe card, and when the second test pad is connected with the third test pad, and the capacitive branch and the large-resistance structure to be tested form a parallel test branch, the measuring machine also measures the resistance value corresponding to at least one group of alternating current signals of the parallel test branch through the probe card.
8. The wafer large resistance test system of claim 7, wherein the metrology tool comprises a tool for performing WAT testing.
9. A wafer large resistance testing method, characterized in that it is applied to the wafer large resistance testing system according to any one of claims 7 to 8, and comprises:
measuring at least two groups of alternating current signals or corresponding resistance values under at least one group of alternating current signals by using a measuring machine, wherein the parallel test branch is a parallel branch formed by a capacitive branch in a wafer large-resistance test structure and a large-resistance structure to be measured;
and calculating the resistance of the large-resistance structure to be measured according to the alternating current signal frequency used in measurement and the resistance obtained by measuring the parallel test branch.
10. The method of claim 9, wherein measuring the corresponding resistance of the parallel test branch by using the measuring machine for at least two ac signals or at least one ac signal comprises: and carrying out multiple measurements on the parallel test branches under the same group of alternating current signals by using a measuring machine, and determining the corresponding resistance value of the parallel test branches under the same group of alternating current signals according to the multiple measurement results.
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