JPH0656392B2 - A / D converter - Google Patents

Description

The present invention relates to an A / D conversion device used in a digital storage oscilloscope or the like.

(Prior Art and Problems) For example, in a digital storage oscilloscope, an A / D converter for A / D converting an input signal needs to have a high conversion speed as the frequency of the input signal increases. To do.

However, there is a problem that it is difficult to realize a high-speed sample hold circuit.

It is an object of the present invention to solve the above problems and provide an A / D converter that can handle both high speed conversion and low speed conversion.

(Means for Solving the Problems) A sample hold circuit, a D / A converter, a comparator which receives the converted analog signal by the D / A converter as one input, and an input signal to the sample hold circuit. Signal switching means for selecting either a first position where the output of the sample and hold circuit is the other input of the comparator or a second position where the input signal is the other input of the comparator directly;
A conversion timing designating means for outputting a conversion timing designating signal for each cycle of the input signal, a holding means for capturing and holding the output of the comparator using the conversion timing designating signal from the conversion timing designating means as a strobe signal, and a D / A conversion. The digital data is given to the comparator according to the successive approximation method, and when the low speed conversion is instructed, the signal switching means is caused to select the first position and the digital conversion is performed according to the output of the comparator.
When the high speed conversion is instructed, the signal switching means is caused to select the second position, and the digital data of one bit is converted for each conversion timing designating signal according to the output held by the holding means, and all bits are converted. After the completion, a conversion control means for changing the generation time of the conversion timing designating signal from the conversion timing designating means is provided so that the holding method at the low speed variation time and the high speed conversion time can be made different.

(Operation) Therefore, when the low speed conversion is instructed, the signal switching means selects the first position, the input signal is guided to the sample hold circuit, and the output of the sample hold circuit is supplied as one input of the comparator. .

On the other hand, digital data is given as an input of the D / A converter in accordance with the successive approximation method, and the converted analog signal level obtained by converting the digital data into an analog signal and the output signal level from the sample hold circuit are compared. In accordance with the comparison output from the comparator, the input signal is converted into digital data by the conversion control means.

On the other hand, when the high speed conversion is instructed, the signal switching means selects the second position and the input signal is directly supplied as one input of the comparator. On the other hand, digital data is given as an input to the D / A converter in accordance with the successive approximation method, and the converted analog signal level obtained by converting the digital data into an analog signal is compared with the input signal level by the comparator. On the other hand, the comparison output of the comparator is taken in by the holding means using the conversion timing designating signal output from the conversion timing designating means for each cycle of the input signal as a strobe signal,
Retained. With the holding output from the holding means, each conversion time designation signal is converted into 1-bit digital data by the conversion control means, and after the conversion of all bits is completed, the conversion time designation signal from the conversion time designation means is converted. It is changed by the control means.

Therefore, when high speed conversion is instructed, the input signal is converted into digital data one bit at a time for each cycle. For example, in the case of conversion to 8-bit digital data, the predetermined level of the input signal becomes digital data in eight cycle periods. Since it is converted, high-speed conversion is not required, and high-speed conversion and low-speed conversion can be supported.

Further, when high-speed conversion is instructed, the digital data given to the D / A converter is sequentially changed, and when the output of the holding circuit is inverted, the digital data given to the D / A converter is converted digital data. You may make it output from a conversion control means. In this case, the input signal level is compared with the analog level converted by the D / A converter every cycle of the input signal, and after the output of the holding circuit is inverted, the next conversion time is instructed. It will be.

(Examples of the Invention) Hereinafter, the present invention will be described with reference to Examples.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, which is an example of the case applied to an oscilloscope.

The input signal is supplied to the signal switching switch 1, and by switching with the signal switching switch 3 which operates in conjunction with the signal switching switch 1, it is selected whether the input signal is supplied to the sample hold circuit 2 or bypassed. Signal switching switch 3
The input signal level output via the or the output signal level from the sample hold circuit 2 is supplied to the comparator 4,
The output analog signal level from the D / A converter 5 is compared. The comparison output of the comparator 4 is supplied to the D flip-flop 6 as data, and the inversion of the output of the comparator 4 is detected.

The input signal is supplied to the trigger circuit 7, the set level of the trigger level setter 7A is compared with the input signal level, and a trigger signal for instructing the start of sweeping and the start of A / D conversion in this embodiment is output. The sweep start trigger signal output from the trigger circuit 7 is supplied to the sweep circuit 8 to generate a sawtooth wave serving as a reference when performing equivalent sampling during high-speed conversion in the sweep circuit 8. The sawtooth wave output from the sweep circuit 8 is supplied to the comparator 10, and the comparator 10 compares the sawtooth wave level with the analog signal level output from the D / A converter 9. The comparison output of the comparator 10 is supplied as the clock signal of the D flip-flop 6.
Here, the D / A converter 9 is supplied with digital data that sequentially increases over the measurement range from a control circuit 11 described later at a predetermined time interval from the trigger position, and a constant interval from the trigger position for performing equivalent sampling. The strobe signal of is output from the D / A converter 9.

A conversion control circuit (hereinafter, referred to as a control circuit) 11 is a control circuit having a successive approximation register, and is activated by an output of a switch 12 from the outside as shown by a broken line, or activated by a trigger signal, and the conversion speed by the switch 12 is increased. When the instruction is the low speed conversion instruction, the signal switching switches 1 and 3 are set to the first position.
Switching to the contact position shown in the figure, the input signal is guided to the sample hold circuit 2, sampling is supplied to the sample hold circuit 2, the output of the comparator 4 is received, and the D / A converter 5 is operated according to the successive approximation algorithm. Output digital data to. When the conversion instruction from the switch 12 is a high-speed conversion instruction, the control circuit 11 switches the signal switching switches 1 and 3 from the state shown in FIG. 1 to disconnect the sample hold circuit 2 and strobe the output of the comparator 10. The output of the comparator 4 is sent as a signal to the D flip-flop 6
The conversion is performed according to a successive approximation algorithm that changes the data when the output of the comparator 4 that has been taken in is inverted. A sweep gate signal is supplied from the sweep circuit 8 to the control circuit 11 in order to notify the timing for sampling once for each sweep of the sweep circuit 8.

2 and 3 in this embodiment configured as described above.
The operation will be described with reference to the flow chart shown in the figure.

First, when a low speed conversion is instructed, it operates like a flow chart shown in FIG.

When the conversion instruction is given by the external switch 12 and the conversion instruction is the low speed instruction, the signal switching switches 1 and 3 are switched to the state shown in FIG. 1, and the sampling pulse of the designated cycle is output from the control circuit 11. Then, the sample hold circuit 2 is selected and operates (step a). The input signal sampled and held in the sample hold circuit 2 is supplied to the comparator 4.
On the other hand, digital data is supplied from the control circuit 11 to the D / A converter 5, and the analog signal level converted by the D / A converter 5 and the sample hold output level output via the signal switching switch 3 Are compared by the comparator 4, the output of the comparator 4 is fetched by the control circuit 11, and different digital data is given to the D / A converter 5 next according to the state of the output of the comparator 4 According to the algorithm, the input signal is converted into digital data (step b), and the converted digital data is output from the control circuit 11 (step c). The above operation is repeated until all the data are completed (step d).

Next, when high-speed conversion is designated, when the trigger level is set, the control circuit 11 operates, the signal switching switches 1 and 3 are switched from the state shown in FIG. 1, and the sample hold circuit 2 is disconnected. It will be in the state where it was opened (step e). Next, digital data is supplied from the control circuit 11 to the D / A converter 9 (step f). On the other hand, the trigger signal from the trigger circuit 7 causes the sweep circuit 8 to output a sawtooth wave as shown in FIG. The comparator 10 compares the level of the sawtooth wave output with the output from the D / A converter 9. Therefore, as shown in Fig. 4, D
The analog signal output from the A / A converter 9 corresponds to the vertical axis thereof, and the digital data y given to the D / A converter 9 is given.
_i (i = 1, ..., N) is set to y _{i + 1} −y _i = Δy,
They are evenly spaced. Here, the sawtooth wave has good linearity. Therefore, the output of the comparator 10 becomes a pulse from the trigger point [0] to the position x _i on the time axis with respect to y _i .

Following this state of step f, the control circuit 11 executes the successive approximation algorithm to convert the digital data to D / A.
It is supplied to the converter 5 (step g).

Then, the control circuit 11 determines that one sweep is completed by the sweep gate signal, and when it is determined that one sweep is completed (step h), the digital data supplied to the D / A converter 5 is D. Is converted into an analog signal by the / A converter 5, and its level is compared with the input signal level,
The comparison output is read by the D flip-flop 6 at the trailing edge of the output of the comparator 10, and the read output, that is, the Q output of the D flip-flop 6 is read by the control circuit 11 (step i), and then the D / A converter. 5 is supplied with the following digital data. For example, when converting into 8-bit digital data, it is executed every time the input signal is triggered eight times, and converted into 8-bit digital data (step j.k). This state is as shown in FIG. In FIG. 5, t ₁ ... T
₉ ... Is the trigger point, and when the value p _i is converted to 8-bit data at t ₁ ... t _{8, the time} from the control circuit 11 to the new trigger point [0] to y _{i + 1 is} next. It becomes a pulse up to the position x _{i + 1} on the axis, and the next value p _{i + 1} is similarly converted into 8-bit digital data, which is executed until the conversion of all data is completed (step l).

In the above-described embodiment of the present invention, the control circuit 11 is provided with the successive approximation register to perform the conversion in accordance with the successive approximation algorithm. However, when the high speed conversion instruction is given, , D by the control circuit 11
The digital data that is sequentially increased is given to the A / A converter 5,
Even if the digital data supplied to the D / A converter 5 when the Q output of the D flip-flop 6 is inverted is output as digital data and then the digital data supplied to the D / A converter 9 is increased. Good.

(Effects of the Invention) As described above, according to the present invention, in A / D conversion, during low-speed conversion, an input signal is sampled and held by a sample and hold circuit, and its output is A / D converted. By doing so, digital data is obtained, and at the time of high-speed conversion, the input signal is compared with the digital data output from the control circuit without passing through the sample hold circuit,
Since the comparison output is digitally sampled and held, signals in a wide range of frequencies can be A / D-converted, and a component that needs to operate at a particularly high speed is not required.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. FIG. 2 is a flow chart for explaining the operation at low speed conversion in one embodiment of the present invention. FIG. 3 is a flow chart for explaining the operation at the time of high speed conversion in one embodiment of the present invention. FIG. 4 and FIG. 5 are diagrams for explaining the operation at the time of high speed conversion in one embodiment of the present invention. 1 and 3 ... Signal switching switch, 2 ... Sample and hold circuit, 4 and 10 ... Comparator, 5 and 9 ... D
/ A converter, 6 ... D flip-flop, 7 ... trigger circuit, 8 ... sweep circuit, 11 ... control circuit.

Claims (2)

[Claims] 1. A sample-hold circuit, a D / A converter, a comparator which receives the analog signal converted by the D / A converter as one input, an input signal to the sample-hold circuit, and an output of the sample-hold circuit. And a signal switching means for selecting either a first position where the input signal is the other input of the comparator or a second position where the input signal is the other input of the comparator directly, and conversion for each cycle of the input signal The conversion timing designating means for outputting the timing designating signal, the holding means for capturing and holding the output of the comparator by using the conversion timing designating signal from the conversion timing designating means as the strobe signal, and the successive approximation method for the D / A converter. When the digital data is given, and the low speed conversion is instructed, the signal switching means is caused to select the first position, and the digital conversion is performed in accordance with the output of the comparator, and the high conversion is performed. When the conversion is instructed, the signal switching means is caused to select the second position, and the conversion data is converted into one bit digital data for each conversion timing designating signal according to the holding output of the holding means, and after the conversion of all bits is completed. An A / D conversion device comprising: a conversion control means for changing the generation time of a conversion timing designating signal from the conversion timing designating means. 2. A sample / hold circuit, a D / A converter, a comparator having one input of a converted analog signal by the D / A converter, an input signal to the sample / hold circuit, and an output of the sample / hold circuit. And a signal switching means for selecting one of a first position where the input signal is the other input of the comparator or a second position where the input signal is the other input of the comparator directly, and a conversion timing for each cycle of the input signal. The conversion timing designating means for outputting the designation signal, the holding means for fetching and holding the output of the comparator by using the conversion timing designating signal from the conversion timing designating means as the strobe signal, and the signal switching means when the low speed conversion is designated. Whether the first position is selected, digital data is given to the D / A converter in accordance with the successive approximation method, and digital data is converted in accordance with the output of the comparator. When the high speed conversion is instructed, the signal switching means is caused to select the second position and the D / A converter is given sequentially changing digital data, and when the holding output of the holding means is inverted, the D / A converter is given. An A / D conversion device comprising: conversion control means for converting the given digital data to a conversion data output and then changing a generation time of a conversion timing designating signal from the conversion timing designating means.