JPH0655520B2 - Driving method for thermal recording head - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for driving a thermal recording head, and in particular, in a thermal recording head that collectively records at non-constant time intervals and at high speed, printing energy can be controlled for each recording element. The present invention relates to a method of driving the thermal recording head.

2. Description of the Related Art The recording density in thermal recording fluctuates based on various factors. Among these factors, particularly in high-speed recording, the influence of the recording interval time has a large effect. When the element is driven, it returns to the base temperature level after a predetermined time when it is driven, but it is in a heat storage state until then, and when it is driven in a high heat storage state, it becomes a dark record. Therefore, we have been trying to wait until the heat generating element has dropped to the base temperature level for the next recording, or have been devised to drop it rapidly to the base temperature level.However, when high-speed recording is required, it can be dealt with. It was running out and I had no choice but to make the next record in the heat storage state. Therefore, conventionally, a method has been proposed in which the recording interval time is measured for each heating element of the recording head, and each heating element is thermally driven by a recording power pulse having a pulse width selected according to the recording interval time.

Conventionally, as a method of controlling the printing energy for each recording element, there is a method described in JP-A-57-117978, for example. This determines the drive pulse width applied to the heating resistor according to the detection result of the heat generation state, and after writing this in the output buffer for each bit,
The print is sent to an IOP (input / output control device). However, in such a method, it is necessary to separately provide a buffer for writing the pulse width. Further, since the printing energy is controlled by the pulse width, for example, an independent signal line (φ ₁ ... φ ₂₀₄₈ ) is required for each recording element as shown in FIG. _1, and the harness from the thermal head unit is required. There is a problem in that the number of circuits increases and circuits and devices become complicated.

FIG. 1 is a diagram showing a conventional recording head driving method. Data ₁ , ₂ , ₃ ... With pulse widths φ ₁ , φ ₂ , φ ₃ ... Selected according to the measured recording interval time for each bit. Is driven to drive the heat generating elements H ₁ , H ₂ , H ₃ ..., For example, if the bit number of one line (the number of heat generating elements) is 2048, the applied energy is controlled for each heat generating element. Then, the number of lead wires (φ ₁ , φ ₂ ... φ ₂₀₄₈ ) for each of the heating elements H ₁ , H ₂ ... H ₂₀₄₈ becomes 2048, the circuit and device become large-scale, and the pulse width defining signal has a plurality of bits ( If a plurality of heat generating elements are used in common, the number of lead wires can be reduced, but on the other hand, there is a drawback that drive control cannot be performed for each bit (for each heat generating element).

In addition, a shift register, a decoder, and a latch circuit that can control the pulse width for each bit (each heating element) are provided in the recording head, and the transfer transfers a code that defines the pulse width in parallel with the image information. It has been proposed to perform shift, decoding, and latching similarly to image information and use the bit length as a driving pulse width, but it is necessary to have a shift register or the like for pulse width information inside the recording head, This function is wasteful for low speeds where it is not necessary to control each bit pulse width, and there is a problem in cost sharing. Therefore, it is not possible for the device to provide a shift register for pulse width information outside the head. There are drawbacks such as a large scale, and when only the decoder is provided outside, the number of rows of shift registers increases, and it is not possible to expect much reduction of circuits inside the head.

SUMMARY OF THE INVENTION The present invention has been made in view of such circumstances, and uses a thermal recording head that collectively drives recording elements (heating elements) for one line, and is capable of storing thousands of bits without increasing buffers or harness wires. The purpose of this is to make it possible to control the energy of each heating element independently.

Configuration The configuration of the present invention will be described below based on Examples.

FIG. 2 is a circuit configuration diagram showing an embodiment of a thermal recording apparatus to which the present invention is applied, and FIGS. 3 and 4 are time charts for explaining the operation thereof. Line data is set to 2K bits (2048 bits), one line is transferred eight times, and the drive pulse width of each heat generating element is the drive history (3 bits) of each bit up to the time equivalent to 8 lines The following is an example of a case in which the information is calculated from 8 bits of the left and right information (2 bits) and the heat storage state of the thermal head (3 bits), and the present invention calculates the three information, Or, it is not characterized by an arithmetic circuit, but is characterized by a driving method of a head, in particular, a driving method of independently driving each bit (each heating element) of the head. Easy to understand from U

In FIG. 2, the input data IDATA is toggle-input to the RAM 1 or RAM 2, and this control is performed by the toggle buffer control 3. And
As shown in FIG. 3, when one of the RAMs becomes “Full”, the data is output at a speed 8 times faster than one line and input to the shift register 4.

The output to the register 4 is performed eight times during the recording time of one line. In the case of the present embodiment, since each dot is recorded by applying a pulse up to 8 times, it is transferred 8 times at a speed of 8 times. , The recording speed, etc., and is arbitrary. IADD is an address at the time of input, and OADD is an address at the time of output. And DI
Output Q delayed by 3 bits from shift register 4 with respect to N
_C (In FIG. 4, Q _A is 1 bit behind DIN, Q _B is 2 bits behind, and Q _C is 3 bits behind)
Is input to one of the gates 5 as the data to be drawn. The other input of the gate 5 is data that determines printing or non-printing for each bit.
In the case of "ue", the transfer data to the thermal head is valid (printing), and in the case of "False" it is invalid (non-printing). Note that WENA (write enable) is only the first transfer of eight transfers. It is valid and reset with black. After that, the count value of the counter 7 becomes the code of the previous history data, which is stored in the RAM 6 for each 2048 bits.

Next, the data processing for determining the drive pulse will be described. The RAM 6 has a capacity of 2K × 4 bits and is addressed in synchronization with the output speed from the toggle buffer. Input to the RAM 6 is performed at the first time of eight data transfers, as shown in FIG. And
The 4th bit (4pin) of the input of this RAM 6
As shown in the figure, the data of Q _A of the shift register 4 (data of 2 bits before the data Q _C to be drawn now) is input. The data 2 bits before this (Q
_A ) is input to the RAM 6 because the data to the thermal head is 3 bits behind the data to DIN, as described above.
Since a bit delay occurs (the output of the multiplexer 9 is delayed by 1 bit in the multiplexer 9), D
This is because there is a delay of 3 bits with respect to IN), and this is for synchronization.

Now, the input data Q _A to the RAM 6 (4 pin) is “T
When the data of one line before is “true”, the counter 7 is reset by the output of the gate 11. When the data is “False”, the counter 7 is incremented.
The values of Q _A , Q _B , and Q _C are all "True", and the output of the gate 10 stops the operation of the counter 7. Further, the output of the counter 7 is input to the RAM 6 and becomes the data of the driving history of each bit (here, the history data is the driving history data up to 8 lines before in each bit), that is, When the data "True" occurs in the rear latch output of RAM6 (see the rear latch output of RAM6 in FIG. 4 (input of counter 7)), the bit is driven at any position up to eight lines before that. Taka is stored, and this is input to inputs 0, 1 and 2 of the RAM 8 (see the input of the ROM 8 in FIG. 4). Note that the illustrated embodiment describes the case of continuous recording, but if there is an intermittent operation in a facsimile, the counter 7
By performing the increment operation of (1) in a unit time instead of in a line unit, the driving history can be stored in time.

The pins 3 and 4 of the ROM 8 have Q _{A of the} shift register 4,
The output of the Q _C is input. This is the information of the right and left of each bit, because in practice, the left and right Q _B of image data Q _C that is about Egako now, the data of the Q _D, delayed 1 bit latch operation of the multiplexer 9, Q _A is input to the ROM 8 as left data and Q _C is input to the ROM 8 as right data.

Head substrate temperature information THERM is input to pins 5, 6 and 7 of the ROM 8.

As described above, printing or non-printing for each bit is determined by the table of the ROM 8 by the eight inputs to the ROM 8. This operation is performed in the first transfer of eight times (while WENA is "True"). Therefore, all data is set to True during the first transfer (ROM8
Output QO is always "True"). The output of the multiplexer 9 (see the output of the multiplexer 9 in FIG. 4) is MPX.
ROM depending on the number of transfers (the number of times) by CLK
One of 8 bits of the output of 8 (refer to the output of ROM 8 in FIG. 4) is selected, input to the gate 5, and the output is input to the shift register 12 (2048 bits). The n-th transfer data is latched in the head by the LOAD (latch) signal after the transfer is completed, and is transferred to the next LOAD.
Record the signal until it is input. When the 8th latch is completed, RE is returned when the time for one transfer elapses.
Latch data is reset by the SET signal, and recording of one line is completed.

If the data transfer rate does not follow due to the limitation of the element or the like, it is possible to follow the rate by inputting data in parallel and performing the same control in each data line.

Effect As described above, according to the present invention, in driving a thermal recording head that collectively drives recording elements for one line,
The in-line image information is transferred n times (8 times in the illustrated embodiment), the transfer period is τ, and data “T” is set for each bit.
When the number of “rue” is m, the driving energy is m × τ. Therefore, there is no means for controlling the applied energy in each bit unit inside the thermal head. It is possible to perform energy control on a bit-by-bit basis (for each heat generating element) for a heat generating element of several thousand bits without increasing the number of bits.
It is also possible to control the printing energy for each recording element by applying it to a general low-speed recording head that does not have a special signal line for controlling the pulse width.

[Brief description of drawings]

FIG. 1 is a diagram showing a conventional recording head driving method, FIG. 2 is a circuit configuration diagram showing an embodiment of a thermal recording apparatus to which the present invention is applied, and FIGS. 3 and 4 show the present invention. 3 is a time chart for explaining the operation of FIG. 1, 2 ... RAM, 3 ... toggle buffer control, 4 ... shift register, 5 ... gate, 6 ... RA
M, 7 ... Counter, 8 ... RAM, 9 ... Multiplexer, 10, 11 ... Gate, 12 ... Shift register, 13 ... Latch circuit.

Claims (1)

[Claims] 1. A thermosensitive device comprising a plurality of recording elements, wherein image information for one line is repeatedly transmitted a plurality of times to a shift register for latching, and the image information latched in the shift register is collectively recorded for each transfer. In the method of driving the recording head,
When transferring image information to the shift register,
Printing or non-printing is determined for each recording element for each transfer, and when it is determined that printing is to be performed, the image information to be transferred is transferred to the shift register as it is.
A method for driving a thermal recording head, characterized in that, when non-printing is determined, image information to be transferred is invalidated and transferred to the shift register, and printing energy is controlled for each recording element.