JPH0654424B2 - Display controller - Google Patents

Description

The present invention relates to a display control device suitable for use in display control in, for example, a captain system.

“Prior Art” In recent years, a display device having a plurality of display surfaces (described later) is used as a terminal related to a new media such as a captain. FIG. 4 is a block diagram showing the overall configuration of this type of display device. In this figure, 1 is a CPU, 2 is a memory including a ROM storing a program used in the CPU 1 and a RAM for storing data, 3 is a display controller, and 4, 5 and 6 are V respectively.
RAM (video RAM), 7 is a CRT display device. In this case, the VRAMs 4 to 6 each store a color code corresponding to each display dot of the CRT display device 7, and these color codes are read in parallel based on the address data ADS output from the display control device 3. It is output and supplied to the display control device 3. The display control device 3 has a CPU 1
Write the color code supplied from VRAM4 to VRAM6. When the display command is output from the CPU 1,
The address data ADS is output to VRAM4 to VR and VR is output.
The color codes in AM4 to AM6 are sequentially read in parallel.
Now, assuming that the predetermined priority order of the VRAMs 4 to 6 is 4, 5, and 6, the display control device 3 normally sets the color codes read from the VRAM 4 to R (red), G ( Green), B (green) color signal
Converted to (analog signal) and CR with sync signal SYNC
Output to the T display device 7. As a result, color dot display based on the color code in the VRAM 4 is performed.
If the color code read from the VRAM 4 is a transparent color code, the color code read from the VRAM 5 is converted into R, G, B color signals and output to the CRT display device 7, and the VRAM 4 If both color codes of 5 are transparent color codes, VRA
If the color code of M6 is converted to R, G, B color signals and output to the CRT display device 7, and if all the color codes of VRAM 4 to 6 are transparent color codes, the signal YS is displayed on the CRT. Output to the YS terminal of the device 7. When this signal YS is output to the YS terminal of the CRT display device 7, an image by a video signal (for example, an image by a video tape) is displayed on the display screen of the CRT display device 7.

As described above, the display device shown in FIG.
It has display surfaces based on the RAMs 4 to 6, and one of these display surfaces is selected and displayed according to the priority order.

By the way, in the captain system, each VRAM
In some cases, the display surface according to (3) is used as a PHOTO surface, a CHARA surface, and a GEO surface. here,
The PHOTO surface is a surface on which picture data for display is stored, C
The HARA surface is a surface where display character data is stored, and the GEO surface is a surface where display picture data is stored as a dot map. In this case, PHOTO side and CHARA
Data is stored on the surface by the memory map shown in FIG. 5A, and data is stored on the GEO surface by the memory map shown in FIG. 6A.

As shown in Fig. 5 (a), PHOTO surface and CHA
The RA surface has a structure in which 2 bytes form one set, and each set corresponds to 13568 display sections as shown in FIG. In each set, the upper 4 bits of the first byte are the pattern storage unit PAT, the lower 4 bits are the attribute storage unit ATR, the upper 4 bits of the next byte are the foreground color storage unit FGC, and the lower 4 bits are the back bit. It is a ground color storage unit BGC. The background color memory BGC stores the background color (background color) code of each display section, and the foreground color storage unit FGC stores the foreground color (foreground color) code of each display section. The pattern storage unit PAT stores 4-bit pattern data corresponding to the four dots in each display section. When the pattern data is "1", dots are formed by the color code in the foreground color storage unit FGC. When the pattern data is displayed "0", dots are displayed by the color code in the background color storage unit BGC.

When the 0th bit of the attribute storage unit ATR becomes "1", the display in which the luminance of the corresponding display section becomes 1/2 is performed, and when the 1st bit becomes "1", the foreground color becomes the background color. The pattern is displayed by matching and hiding the pattern. In addition, the third and second bits are (0,0)
In the case of, normal static pattern display is performed, and in the cases of (0, 1) and (1, 0), flushing display (flushing mode is different) is performed respectively.

Next, the memory map of the GEO plane is shown in FIG.
As shown in (b), one dot is displayed by 4 bits, and 54272 dots are displayed as a whole. Therefore, 16 colors can be simultaneously displayed on one screen.

[Problems to be Solved by the Invention] By the way, when writing and rewriting the PHOTO surface and the CHARA surface, the pattern storage unit PAT, the attribute storage unit ATR, and the foreground are stored for each 2-byte area corresponding to each display section. It is necessary to individually perform write control on the ground color storage unit FGC and the background color storage unit BGC. Conventionally, this write control is
The CPU performs the calculation of the write address, the transfer of the data to be written, and the like for each storage unit.
Therefore, there is a drawback that a heavy load is imposed on the CPU, the operation program becomes complicated, and a long processing time is required.

On the other hand, in one screen, the storage unit other than the pattern storage unit PAT often stores the same data for each display section. Therefore, conventionally, even in the data writing in such a case, the address calculation and the data transmission are controlled for all the storage units one by one, and there is a drawback that the rewriting process becomes extremely inefficient.

The present invention has been made in view of the above-mentioned circumstances.
Even when the memory map as shown in FIG. 9A is set, when writing data to each storage unit, C
It is an object of the present invention to provide a display control device that can reduce the load on the PU extremely and can perform efficient data writing.

[Means for Solving Problems] In order to solve the above problems, the present invention provides a display control device that performs display based on data in an image memory in which data for image display is stored. A plurality of storage means to be stored, a counting means of a predetermined bit for counting a write control signal for controlling writing to the image memory, and one of the storage means is selected based on the count result of the counting means. And selecting means for forming a word with the data in the selected storage means and outputting it to the image memory.

"Operation" The storage means can be divided into one for writing the same data and one for writing the changing data, and the selection means stores the data in the storage means according to the number of times of writing. Since the word is formed by appropriately selecting, even if the memory map has the structure shown in FIG. 5A and the same data other than the pattern data is written. At the time of writing data to the image memory, the address calculation of the CPU becomes extremely simple, and the data transmission of the CPU is required only once every predetermined number of times.

[Examples] Examples of the present invention will be described below with reference to the drawings.

(1) Configuration of Embodiment FIG. 2 is a block diagram showing a schematic configuration of an embodiment of the present invention. In FIG. 15, reference numeral 15 is a display control device for performing various display controls under the control of the CPU 1 (see FIG. 1). ). 1
Reference numerals 0a, 10b, 11a, 11b, 12a and 12b denote VRAMs for inputting / outputting data in units of 4 bits, and the VRAMs 10a and 10b make the CHARA surface a VRA.
M11a, 11b, PHOTO surface, VRAM12a,
12b constitutes the GEO surface. In this case, each VRA
As shown in FIG. 5A, the M10a and M11a have a pattern storage unit PAT and a foreground color storage unit FG.
C and V are alternately set in the order of addresses, and VRAM 10b,
The attribute storage unit ATR and the background color storage unit BGC are alternately set in the address order 11b. In addition, as shown in FIG.
0a, 11a constitute the upper side of the byte on each side,
The VRAMs 10b and 11b form the lower side of the bytes on each surface. As shown in FIG. 6 (a), the VRAMs 12a and 12b are so arranged that the color codes corresponding to the respective display dots DC ₀ , DC ₁ ... Are sequentially and alternately stored, and the VRAM 12a stores each byte. Upper side, VRA
M12b constitutes the lower side of each byte.

Also, as shown in FIG. 2, the VRAMs 10a-12
The address bus b is commonly connected and is appropriately accessed by the display control device 15.
AM 10a, 10b, 11a, 11b, 12a, 12b
Are control signals WC0, WC1, WP0, WP1, W respectively.
When G0 and WG1 are "1", the write enable is enabled.

Next, FIG. 1 is a block diagram showing a detailed configuration of the display control device 15, in which 21 is a controller 20.
It is an internal bus connected to the data bus of the CPU 1 via. Reference numeral 23 is an 8-bit register (for two sections) in which pattern data is stored, 24 is a register in which attribute data is stored, 25 is a foreground color code in the upper 4 bits, and a back in the lower 4 bits. This is a register that stores a grand color code. Two
6,27 each a selector, respectively input I ₀ when the signal supplied to the terminal S is "0", when the "1" selects input terminal I _1. Reference numeral 28 is a 2-bit counter, which counts the write pulse (write control signal) WP supplied from the controller 20 and resets the count value when a "1" signal is supplied to the terminal R. 30, 31
Is a register for storing predetermined 2-bit data on the data bus 21 when the signals RWP1 and ISP rise. The 0th and 1st bit output signals of the register 30 are supplied to the selectors 36 and 38 as select signals, and the 0th and 1st bit output signals of the register 31 are supplied to the counter 28 and the D type flip-flop 32 respectively as reset signals. It In the selectors 36 and 38, the signals supplied to the select terminals (B, A) are "0",
At the time of "1", "2", "3", the input terminals I ₀ , I ₁ ,
Select I ₂ and I ₃ (all 8-bit input terminals). Three
Reference numerals 5 and 37 denote latches, respectively, which take in the data supplied to the input terminal when the signal LP1 becomes a "1" signal.
Latch 35, VRAM10a, the read data from 10b latched in parallel, and supplied to the input terminal I ₁ of the input terminal I ₀ and the selector 38 of the selector 36, the latch 37 VRAM 11a, the read data from 11b in parallel Latch and input terminal I _{1 of} selector 36 and selector 3
8 input terminals I ₀ .

Next, 40 is a register for taking in predetermined 5-bit data on the data bus 21 when the signal RWP5 rises, and 41 to 46 are output signals of the register 40, output signals of the D type flip-flop 32 and write pulses. It is a NAND gate that determines the values of the write enable signals WC0, WC1, WP0, WP1, WG0, WG1 to each VRAM based on WP.

50, R, based on the read data from the VRAM
This is a data conversion unit that creates G, B (red, green, blue) digital signals and performs transparency processing and the like. The R, G, B digital data output by the data conversion unit 50 is converted into an analog signal by the digital / analog converters 51, 52, 53 and supplied to the CRT display device 7 (see FIG. 2).

(2) Operation of Embodiment Next, the operation of this embodiment having the above-described configuration will be described.

(2-1) Expansion buffer write The operation of this expansion buffer write is CHA.
This is an operation for writing data on the RA surface or the PHOTO surface at high speed. In this case, the operation is almost the same when writing to either surface, and therefore, the case of writing to the CHARA surface will be described below as an example.

First, the CPU 1 supplies data for selecting the register 24 to the controller 20, and further supplies attribute data. As a result, the controller 20 raises the signal RWP3 and sends the above attribute data to the data bus 21. As a result, the attribute data is set in the register 24.

Next, the CPU 1 supplies data for selecting the register 25 to the controller 20, and further supplies the foreground color code and the background color code in parallel. As a result, the controller 20 sends the signal RWP
4, the foreground color code and the background color code are sent to the data bus 21, and these color codes are set in the register 25.

Next, the CPU 1 causes the controller 20 to register 23.
Is supplied, and pattern data for 4 × 2 dots corresponding to the 0th and 1st display sections (see FIG. 5B) is supplied. As a result, the controller 20 raises the signal RWP2, sends the pattern data to the data bus 21, and writes the pattern data in the register 23.

Next, the data (1, 0) and (0, 0) are sequentially written into the register 31 by the same process as described above, and the counter 2
8 is reset once, and the D-type flip-flop 32 is always reset. As a result, from the output terminal of the D type flip-flop 32, "1"
The signal continues to be output. Then, for register 40,
Data writing is performed so that the "1" signal is output from the output terminals Q ₀ , Q ₁ , and Q ₃ . As a result, when the write pulse WP is supplied from the CPU 1 through the controller 20, the signal WC which is the output signal of the NAND gates 41 and 42 is output.
0 and WC1 become "0" signals, and VRAMs 10a and 10
b becomes the write enable state. That is, each time the write pulse WP is supplied by the above process, the CHARA
The state in which the surface is write-enabled is set. Also,
Data (1, 0) is written in the register 30 so that the selectors 36, 38 select the input terminal I ₂ .

When the above-mentioned processing is performed, the counter 28 is reset, so that the selectors 26 and 27 both select the input terminal I ₀ . Further, since the selectors 36, 38 select the input terminal I ₂ , the upper 4 bits of the selectors 36, 38 become the pattern data of the 0th display section stored in the upper side of the register 23, and the selectors 36, 38 The lower 4 bits of 38 are attribute data stored in the register 24.

Next, the CPU 1 accesses the head addresses of the VRAMs 10a and 10b and outputs the write pulse WP. As a result, the output signals WC of the NAND gates 41 and 42
0 and WC1 become "0" signals, and the VRAM 10a becomes the 0th signal.
The pattern data of the display section and the attribute data are written in the VRAM 10b.

When the write pulse WP is output, the counter 28
Performs up-counting and sets the count value to "1".
As a result, the selector 27 is supplied with the "1" signal at the terminal S and selects the input terminal I ₁ . When the selector 27 selects the input terminal I ₁ , the output signal of the selector 27 is
The upper side of the stored data is the foreground color code, and the lower side thereof is the background color code. Next, the CPU 1 accesses the (start address + 1) address of the VRAMs 10a and 10b and outputs the write pulse WP. As a result, the signals WC0 and WC1 become "0" signals, and the foreground color code and the background color code are written in the (start address + 1) addresses of the VRAMs 10a and 10b, respectively.
At this time, the counter 28 is incremented and the count value becomes "2".

When the count value of the counter 28 becomes "2", "1" signal from the Q ₁ output, Q ₀ output from the terminal "0" signal is output, the selector 26 selects the input terminal I _1, the selector 27
Selects the input terminal I ₀ again. As a result, the selector 36
Of the output signal of the upper 4 bits of the lower 4 of the register 23
It becomes the pattern data of the first display section stored in the bit, and the lower 4 bits become the attribute data stored in the register 24. When the CPU 1 accesses the (start address + 2) address and outputs the write pulse WP, the pattern data is stored in the above addresses of the VRAMs 10a and 10b, that is, in the second byte (see FIG. 5A) of the CHARA surface. Attribute data is written respectively.

Further, the counter 28 is incremented in the same manner as described above to have a count value of "3", and the output terminals Q ₁ and Q ₀ each output a "1" signal. As a result, the selector 27 selects the input terminal I _1, and the output signal of the selector 36 becomes the contents of the register 25. That is, the upper side is the foreground color code and the lower side is the background color code. Then, when the CPU 1 accesses the (start address + 3) address and outputs the write pulse WP, the foreground is applied to the corresponding address of the VRAMs 10a and 10b, that is, the third byte of the CHARA surface.
And the background color code is written. Further, the counter 28 counts the write pulse WP, so that the count value becomes “0” again.

By the above operation, data writing conforming to the memory map shown in FIG. 5A is performed in the 0th to 3rd bytes of the CHARA surface.

Next, the CPU 1 supplies the controller 20 with the data for selecting the register 23 and the pattern data of the second and third display sections. As a result, the controller 20 raises the signal RWP2, sends the pattern data of the second and third display sections to the data bus 21, and the register 2
The pattern data of the second display section is written in the upper side of 3, and the pattern data of the third display section is written in the lower side. And
When the CPU 1 performs the write operation similar to the above case while incrementing the write address, the CH 1
Data writing according to the memory map is performed in the 4th to 7th bytes of the ARA surface.

Thereafter, as described above, each time 4 bytes of data are written to the CHARA surface, the pattern data in the register 23 is rewritten corresponding to the display section, and CHA
Writing is performed on the entire RA surface. According to the above operation, the CPU 1 can write the attribute data, the foreground color code, and the background color code at the initial setting of the data writing, and then write the pattern data only once every four accesses. . Moreover, the write address may be sequentially incremented by one, and no troublesome address calculation is required. And, except for pattern data, CHAR
In many cases, all of the A-side or PHOTO-side are the same, and therefore, according to the above-described operation, writing on these sides can be executed at high speed and with an extremely light load on the CPU 1. When writing on the PHOTO surface,
From the output terminals Q ₁ , Q ₂ , Q ₃ to the register 40, “1”
Data may be written so that a signal is output.

(2-2) Exchange Change This exchange operation is performed on the PHOTO side and CHARA.
This is an operation of simultaneously exchanging surface data.

First, the CPU 1 writes data (0, 1) in the register 30 via the controller 20 shown in FIG. 1 so that the selectors 36, 38 both select the input terminal I ₁ . Further, the CPU 1 writes data to the register 40 via the controller 20 so that “1” signals are output from the output terminals Q ₀ , Q ₁ , Q ₂ and Q ₃ .
Thereby, the VRAMs 10a, 10b, 11a, 11b
To be accessible together, ie, CHAR
Both the A side and the PHOTO side should be accessible.

Next, the CPU 1 sends the first address data of the area for data exchange to the VRAM 1 via the controller 20.
The data is supplied to 0a, 10b, 11a, and 11b to perform a read operation, and data for setting the signal LP1 to "1" is supplied to the controller 20. As a result, VRAM1
The data read from 0a and 10b are written in the latch 35, and the data read from VRAMs 11a and 11b are written in the latch 37. Then the CPU
1 supplies the write pulse WP through the controller 20 while keeping the access address as it is. As a result,
The signals WC0, WC1, WP0, WP1 become "0" signals, and the data in the latch 35 is VR via the selector 38.
The data written in the AMs 11a and 11b and written in the latch 37 is written in the VRAMs 10a and 10b through the selector 36. That is, by the above operation, data of the same address on the CHARA side and the PHOTO side are simultaneously exchanged.

Then, the CPU 1 accesses the next address in the area where the data should be exchanged, and alternately performs the read operation and the write operation as described above. After that, the above operation is performed for all areas where data is to be exchanged by sequentially switching addresses. As a result, as shown by arrows in FIG.
Data in the same area of the surface and the PHOTO surface are exchanged. Since one display section is composed of 2-byte data, data exchange for one display section is performed by two data exchanges.

Further, the display priority is set for the PHOTO surface and the CHARA surface, so that the data to be displayed on the front surface and the data to be displayed on the rear surface are exchanged by the data exchange.

According to this exchange operation, data is simultaneously read from two surfaces and data is simultaneously written to the two surfaces, so that the CPU can be compared with a normal data replacement process.
Since the number of accesses of 1 is halved, and the data is exchanged without the CPU 1, the data is exchanged at an extremely high speed. Further, the load on the program of the CPU 1 is reduced.

(2-3) Data Move This data move operation is an operation of moving the display position of the image.

The data move operation is almost the same as the above-mentioned exchange operation, but the area for data read differs from the area for data write. That is, the same operation as the above-mentioned exchange is performed until the data to be moved is read and stored in the latches 35 and 37. However, when writing the latched data, the CPU 1 writes the data corresponding to the destination area. Is sent. At this time, if the register 30 is set to output the data (0, 1), as shown by an arrow in FIG.
If the data is moved between the RA surface and the PHOTO surface and the register 30 is set to output the data (0, 0), the data is moved within the same surface as shown by the arrow in FIG. Is done. Further, by changing the data to be written in the register 40, the signal WC
Since it is possible to prevent any one of 0, WC1, WP0, and WP1 from becoming a "0" signal, only the movement of either one of the arrows shown in FIG. 3 or the movement of either one of the arrows is effective. You can also

(2-4) Mask / skip write In this mask / skip write operation, for example, only the pattern storage section PAT shown in FIG. 5A is accessed to rewrite pattern data, or only the attribute storage section ATR is accessed. It is used when rewriting the attribute data. In the data rewriting process, only the attribute data or the pattern data is often rewritten while leaving the foreground color and background color as they are, and in such a case, the mask / skip write operation is effective.

This operation will be described below by taking as an example the case where only the pattern data on the CHARA surface is sequentially rewritten.

First, CPU 1, such that the "1" signal from the output terminal Q _0, Q ₁ of the register 40 is output from the output terminal Q ₀ of the register 31 "1" so that the signal is output, The register 30 Data is written to each of the above registers so that the "1" signals are output from the output terminals Q ₀ and Q _{1 of} .
As a result, only the signal WC0 becomes a "0" signal, and the data sent to the data bus 21 is
It is supplied to the VRAMs 10a and 10b via the selector 36. Furthermore, the D-type flip-flop 32 becomes a state where it is not reset thereafter.

After the above state is set, the CPU 1 sends the start address to the VRAMs 10a, 1 via the controller 20.
0b, the pattern data to be written (4 bits) is supplied to the upper side of the data bus 21, and the write pulse WP is further supplied. At the time when the first write pulse WP is supplied, the D type flip-flop 32 which is reset in the initial state.
Since the "1" signal is output from the output terminal of the NAND gate 41, the "1" signal is supplied to all the input terminals of the NAND gate 41, and the output signal WC0 of the NAND gate 41 becomes the "0" signal. On the other hand, according to the address data from the CPU 1, V
The head addresses of the RAMs 10a and 10b are accessed. As a result, the pattern data supplied to the data bus 21 is written in the head address of the VRAM 10a. That is, desired pattern data is written on the upper side of the 0th byte on the CHARA surface (see FIG. 5A).

Next, the CPU 1 increments the access address by 1, leaves the data to be transmitted as it is, and outputs the write pulse W.
Output P. When the second write pulse WP is supplied, the output signal of the D-type flip-flop 32 becomes the "0" signal, so the output signal W of the NAND gate 41
C0 does not become a "0" signal, and as a result, VRAM 10a
Data is not written to the memory.

Next, the CPU 1 increments the access address by 1, supplies the pattern data to be written in the third byte of the CHARA surface to the upper side of the data bus 21 via the controller 20, and further, the write pulse W
Output P. When the third write pulse WP is output, the output signal of the D-type flip-flop 32 is inverted to the “1” signal, and the output signal WC of the NAND gate 41 is output.
0 becomes a "0" signal. As a result, the VRAM 10a enters the write enable state, and the pattern data sent to the data bus 21 is transmitted via the selector 36 to the VRAM 10a.
Written to a. That is, desired pattern data is written on the upper side of the third byte on the CHARA surface.

After that, the CPU 1 similarly increments the access address by one, outputs the write pulse WP, and updates the pattern data at the time of writing an odd number of times, thereby sequentially rewriting only the pattern storage unit PAT on the CHARA surface. be able to. As described above, according to the operation of the mask Kip write, when accessing a portion that needs to be rewritten, the CPU 1 may sequentially increment the access address by one, and no address calculation or the like is necessary. In addition, the pattern storage unit PAT is
Although it is arranged on the upper side of the odd-numbered bytes on the RA side, the CPU
1 does not need to mask other bits to access this part.

The attribute storage units ATR and P on the CHARA surface
Pattern memory PAT or PHOTO on the HOTO surface
When the surface attribute storage unit ATR is accessed, data may be written in the register 40 so that each of the signals WC1, WP0 or WP1 can be a "0" signal.

Also, when writing with even bytes on each side,
The reset timing of the D-type flip-flop 32 may be changed so that it is reset at the end of the first access.

In this embodiment, as can be seen from the above description, four operations of expansion buffer write, exchange, data move, and mask / quick write can be arbitrarily selected, so that an optimum operation according to various processes is performed. There is an advantage that can be.

[Advantages of the Invention] As described above, according to the present invention, in the display control device that performs display based on the data in the image memory in which the data for image display is stored, a plurality of storages for storing data are stored. Means, a counting means for counting a write control signal for controlling writing to the image memory, and any one of the storage means based on the count result of the counting means, and in the selected storage means Since there is provided a selecting means for forming a word by the data of the above and outputting it to the image memory, it is possible to divide the storing means into one for writing the same data and one for writing the changing data. This is possible because the selecting means appropriately selects the data in the storage means according to the number of times of writing to form a word. Therefore, even when the memory map has a configuration as shown in FIG. 5A and the portion for writing the same data and the portion for writing different data coexist, the address calculation of the CPU becomes extremely simple, and An advantage is obtained in that the CPU can send data once every predetermined number of times. Therefore, writing to the image memory becomes extremely efficient, and there is an advantage that the writing speed can be increased.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention,
FIG. 2 is a block diagram showing a connection relationship between the same embodiment and VRAM, FIG. 3 is a conceptual diagram of a CHARA surface and a PHOTO surface for explaining the operation in the same embodiment, and FIG. 4 is a conventional display control device. FIG. 5 (a) is a memory map of the PHOTO surface and the CHARA surface set in the captain system, and FIG. 5 (B) is the pattern data on the PHOTO surface and the CHARA surface. FIG. 6 (a) showing the relationship between the display area and the display section
Is a memory map of the GEO plane set in the captain system or the like, and FIG. 6B is a diagram showing a relationship between display dots and dot color codes on the GEO plane. 10a, 10b, 11a, 11b ... VRAM (image memory), 23, 24, 25 ... Registers (first, third,
Second storage means), 26, 27 ... Selector (selection means), 28 ... Counter (counting means), WP ...
Write pulse (write control signal).

Claims (3)

[Claims] 1. A display control device for performing display based on data in an image memory in which data for image display is stored, and a plurality of storage means for storing data and controlling writing to the image memory. A predetermined bit counting means for counting the write control signal and one of the storage means is selected based on the count result of the counting means, and a word is constructed by the data in the selected storage means to the image memory. A display control device comprising: a selection unit for outputting. 2. The plurality of storage means include first storage means for storing pattern data, second storage means for storing color data, and third storage means for storing attribute data.
The selecting means appropriately selects the first to third storing means based on the counting result of the counting means, forms a word by the selected data, and outputs the word to the image memory. The display control device according to claim 1, wherein: 3. The selecting means carries out an associating process for selecting the first to third storage means so as to combine the color data or the attribute data corresponding to the pattern data. The display control device according to claim 2.