JPH0654011A - Demodulation circuit for digital modulation wave - Google Patents

Abstract

PURPOSE:To reduce the circuit scale and to attain circuit integration by providing a changeover switch control circuit and plural changeover switches in the demodulation circuit so as to use the circuit configuration for the input of a QPSK modulation signal and that for the input of an MSK signal in common. CONSTITUTION:Upon the receipt of a QPSK (quadrature phase shift keying) demodulation instruction, a changeover switch control circuit 19 allows changeover switch 18 to select an output of a subtractor 12, the output is inputted to a multiplier 8 and the circuit 19 allows a changeover switch 17 to select an output of a multiplier 11 simultaneously and the output is inputted to a clock recovery circuit 20. Upon the receipt of an MSK (minimum phase shift keying) demodulation instruction, the changeover switch 18 selects an output of the clock recovery circuit 20, the output is inputted to the multiplier 8, the changeover switch 17 selects an output of the subtractor 12 and the output is inputted to the clock recovery circuit 20. Thus, the QPSK demodulation circuit portion and the MSK demodulation circuit portion share their function blocks in common and the circuit scale for the two kinds of the demodulation circuit is halved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a receiver for receiving a signal from a broadcasting satellite, a communication satellite or the like, and more particularly to a demodulator circuit of the receiver for receiving both a QPSK modulated signal and an MSK modulated signal.

[0002]

2. Description of the Related Art As broadcasting services using geostationary satellites, multi-channel pulse code modulation (PCM) broadcasting and multi-channel digital television broadcasting are planned in addition to conventional analog television broadcasting. In these broadcasts, quadrature phase shift keying (QPSK) and minimum
A direct modulation method, such as shift keying (MSK), which directly modulates a carrier with a multi-channel signal is used.

As a demodulation of such a QPSK modulated signal or an MSK modulated signal, there is, for example, a QPSK demodulation circuit disclosed in Japanese Patent Laid-Open No. 62-136152.

This proposed example will be described with reference to FIG. FIG. 3 is a block diagram showing an example of a conventional QPSK demodulator.

In FIG. 3, 1 is a first multiplier, 2 is a second multiplier, 3 is a first filter, 4 is a second filter, 5 is a 90-degree phase shifter, and 6 is a first filter. Voltage controlled oscillator, 7
Is a third filter, 20 is a clock recovery circuit, 31 is a first waveform shaper, 32 is a second waveform shaper, and 33 is a third waveform shaper.
, 34 is a fourth multiplier, 35 is a fifth multiplier,
12 is a subtractor.

In this conventional example, a broadcast wave as an intermediate frequency signal is input to the multipliers 1 and 2 while a carrier frequency signal phase-locked with the carrier of the intermediate frequency signal is obtained from the first voltage controlled oscillator 6. Is supplied to one of the multipliers 2 and is also supplied to the other multiplier 1 via the 90-degree phase shifter 5. Then, the multiplier 1 obtains a binary output I in which the 4-phase PSK signal is detected, while the multiplier 2 obtains a binary output Q in which the 4-phase PSK signal is detected. The I and Q thus obtained are supplied to the waveform shaping circuits 31 and 32, and the waveforms of the rectangular waves ID and QD are shaped and supplied to the third multiplier 33 and the fourth multiplier 34, respectively. Then, the third multiplier 33 and the fourth multiplier 3
The output of 4 is subtracted by the subtraction circuit 12 to obtain the phase error signal. This phase error signal is supplied to the first voltage control oscillation circuit 6 through the third filter 7, and a signal having a frequency corresponding to this phase error signal is output from the first voltage control oscillation circuit 6 and the input intermediate frequency It becomes a reproduction carrier of the signal, and quadrature synchronous detection becomes possible.

Further, as the demodulation of the MSK modulated signal, there is one described in JP-A-58-70664. This already proposed example will be described with reference to FIG. FIG. 4 is a block diagram showing an example of a conventional MSK demodulator. 3 and 4, the same reference numerals are given to the same functional blocks.
Reference numeral 8 is a sixth multiplier, 9 is a third multiplier, 10 is a fourth multiplier, and 11 is a fifth multiplier.

First, in the first multiplier 1 and the second multiplier 2, the modulated signal converted into the intermediate frequency is generated by the first voltage-controlled oscillator 6 and the 90-degree phase shifter 5, and the in-phase carrier and Synchronous detection is performed by multiplying each with an orthogonal carrier. Next, the in-phase component output and the quadrature component output are multiplied by the third multiplier 9, and the multiplied output is further multiplied by the clock signal reproduced by the clock reproduction circuit 20 in the sixth multiplier 8 to obtain the intermediate value. A carrier phase error between the modulated signal having the frequency and the output of the first voltage controlled oscillator 6 is detected,
Output as carrier phase error information. Then, the first voltage controlled oscillator 6 is controlled by the carrier phase error information to make the phase difference between the modulated signal having the third intermediate frequency and the output signal of the first voltage controlled oscillator 6 a certain constant value. It constitutes a feedback loop and enables quadrature synchronous detection.

[0009]

In order to receive two kinds of signals, that is, a QPSK-modulated modulated signal and an MSK-modulated modulated signal, a demodulator like the conventional example of FIG. 3 described above, and FIG. In addition to the need for demodulators as in the conventional example, similar peripheral circuits are also required in addition to the respective demodulators, and there is a problem in making the demodulator circuit a one-chip IC.

An object of the present invention is to provide a demodulation circuit which is capable of stably demodulating two kinds of signals of a QPSK modulation signal and an MSK modulation signal from a satellite or the like and suitable for IC integration.

[0011]

In order to achieve the above object, in QPSK demodulation and MSK demodulation in which the data transmission rates are substantially equal, for example, the configuration of a QPSK demodulator is shown in FIG. 5 and is disclosed in Japanese Patent Laid-Open No. 63-164655. In the present invention, it is noted that the circuit can be shared between the QPSK demodulator and the MSK demodulator in the case of the configuration disclosed in
The same circuit configuration is used for the demodulation of the QPSK modulated signal and the MSK modulated signal, and the output of the subtractor that takes the difference between the signal obtained by squaring the demodulated output I signal and the signal obtained by squaring the demodulated output Q signal is used as carrier recovery. Forming a circuit loop of QPSK demodulation used for the above and a circuit loop of MSK demodulation using the output of the subtractor for clock recovery, and selecting either one of the loops depending on the signal received from QPSK and MSK to operate. A selection means is provided.

[0012]

The subtracter is configured to select the QPS by the selecting means.
When K demodulation is selected, it operates as a carrier recovery circuit, and when MSK demodulation is selected, it operates as a clock recovery circuit.

According to the present invention, by using the structure disclosed in Japanese Patent Laid-Open No. 63-164655 in the structure of the QPSK demodulation circuit, the functional block can be shared with the MSK demodulation circuit, and two kinds of demodulation circuits can be used. The circuit scale of can be halved,
Further, it is possible to share the IF amplifier and the AGC control circuit etc. in the input part, and the circuit can be downsized and the power consumption can be reduced.

[0014]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a demodulation circuit as an embodiment of the present invention.

In FIG. 1, the same functional blocks as those in FIGS. 3 and 4 are designated by the same symbols. Other, 17
Is a second changeover switch, 18 is a first changeover switch, and 19 is a changeover switch control circuit.

In FIG. 1, a modulation signal having the second intermediate frequency is input from the input terminal 101. Further, the changeover switch control circuit 19 inputs a changeover signal in accordance with the type of the inputted modulation signal, that is, the QPSK modulation signal or the MSK modulation signal. When a QPSK demodulation command is input from the changeover switch control circuit 19, the first changeover switch 18 selects the output of the subtractor 12 and inputs this output to the sixth multiplier, and at the same time the second changeover switch. 17 selects the output of the fifth multiplier 11 and inputs it to the clock recovery circuit 20. MSK
When the demodulation command is input, the first changeover switch 18 selects the output of the clock recovery circuit 20 and inputs this output to the sixth multiplier. The second changeover switch 17 selects the output of the subtractor 12, and the clock recovery circuit 2
Enter 0.

Therefore, a command for QPSK demodulation is input from the changeover switch control circuit 19, the first changeover switch 18 selects the output of the subtractor 12, and the second changeover switch 17 of the fifth multiplier 11 is selected. If the output is selected, a QPSK demodulation circuit is formed.

Further, an MSK demodulation command is input from the changeover switch control circuit 19, the first changeover switch 18 selects the output of the clock recovery circuit 20, and the second changeover switch 17 outputs the output of the subtractor 12. If selected, an MSK demodulation circuit is formed.

Next, FIG. 2 shows another embodiment to which the present invention is applied. An MSK demodulation circuit having a reference oscillator as a reproduction carrier signal source as shown in FIG. 2 is disclosed in Japanese Patent Laid-Open No. 63-3.
It is disclosed in Japanese Patent Publication No. 0049.

In the figure, those having the same numbers as those in FIG. 1 indicate the same functional blocks.

In the present embodiment, 100 is an input terminal, 2
2 is a first mixer, 23 is a first local oscillator, 24 is a second mixer, and 25 is a second voltage controlled oscillator which is also a second
Local oscillator, 26 is a bandpass filter (BPF),
28 is a first decision circuit, 29 is a second decision circuit, 27 is an inverting circuit, 21 is a reference oscillator, 30 is a digital signal processing circuit, and 31 is a QPSK / MSK common demodulator.

In this embodiment, an outdoor unit (not shown)
The first frequency conversion circuit including the first mixer 22 and the first local oscillator 23 and the second mixer 24 for the modulation signal having the first intermediate frequency input from the input terminal 100 from the The second frequency conversion circuit composed of the second local oscillator 25 and the second local oscillator 25 reduces the carrier frequency by a double heterodyne method having two frequencies (second and third intermediate frequencies) as intermediate frequencies, and then QPSK. , MSK common demodulator 31 to demodulate a QPSK or MSK modulated signal.

First, in the first multiplier 1 and the second multiplier 2, the in-phase carrier generated by the reference oscillator 21 and the 90-degree phase shifter 5 are applied to the modulated signal converted into the third intermediate frequency. Then, synchronous detection is performed by multiplying the output of the reference oscillator 21 by the quadrature carrier obtained by shifting the phase of the reference oscillator 21 by 90 degrees. When performing QPSK demodulation, a signal for performing QPSK demodulation is input from the changeover switch control circuit 19 to the first changeover switch 18 and the second changeover switch 17, and the first changeover switch 18 is changed over to the changeover switch control circuit 19. From the selector switch 12, the output of the subtractor 12 is selected, and the output of the subtractor 12 is input to the sixth multiplier 8. At the same time, the second changeover switch 17 receives the signal from the changeover switch control circuit 19. In response, the output of the fifth multiplier 11 is selected and input to the clock recovery circuit 20. When the MSK demodulation command is input, the first changeover switch 18 selects the output of the clock recovery circuit 20 and inputs it to the sixth multiplier. The second changeover switch 17 selects the output of the subtractor 12, and the clock recovery circuit 2
Enter 0.

Therefore, a command for QPSK demodulation is input from the changeover switch control circuit 19, the first changeover switch 18 selects the output of the subtractor 12, and the second changeover switch 17 selects the output of the fifth multiplier 11. If the output is selected, a QPSK demodulation circuit is formed.

An MSK demodulation command is input from the changeover switch control circuit 19, the first changeover switch 18 selects the output of the clock recovery circuit 20, and the second changeover switch 17 changes the output of the subtractor 12. If selected, an MSK demodulation circuit is formed. The second local oscillator 25 is controlled by the carrier phase error signal of QPSK or MSK selected in this way, and the phase difference between the modulation signal having the third intermediate frequency and the output of the reference oscillator 21 is set to a certain constant value. Configure a feedback loop. Conventionally, input terminal 1
The second frequency conversion circuit including the second local oscillator 25 and the second mixer 24 is necessary for the demodulation circuits of QPSK and MSK, respectively, for the modulation signal having the intermediate frequency input via 00. However, in this embodiment, sharing can be achieved,
This shows that the partial circuit can be reduced.

FIG. 6 is a block diagram of a clock recovery circuit applied to the present invention. 13 is a phase comparator, 14 is a loop filter, 15 is a voltage controlled oscillator, 1
Reference numeral 6 is a frequency divider, and 20 is a clock recovery circuit shown in FIGS. The QPSK demodulation of the clock recovery circuit is described in detail in JP-A-3-23021.
Regarding the MSK demodulation circuit, the above-mentioned Japanese Patent Laid-Open No. 58-
No. 70664, QPSK demodulation,
It is well known that it can be commonly used for both MSK demodulation.

[0028]

As described above, according to the present invention,
By providing the changeover switch control circuit, the first changeover switch, and the second changeover switch at the time of inputting the QPSK modulation signal and the time of inputting the MSK modulation signal,
Circuit configuration can be the same, QPSK and MSK
In a circuit that demodulates a modulated signal, the circuit can be significantly downsized and power consumption can be reduced, a demodulation circuit can be realized as a one-chip IC, and further, I of two types of demodulation circuits can be realized.
The F amplifier and the like can be shared, and the peripheral circuits such as the AGC control circuit and the AFC control circuit can be shared, and the satellite broadcast receiver itself can be downsized.

[Brief description of drawings]

FIG. 1 is a block diagram showing a demodulation circuit as one embodiment of the present invention.

FIG. 2 is a block diagram showing a demodulation circuit as another embodiment of the present invention.

FIG. 3 is a block diagram showing a conventional QPSK demodulation circuit.

FIG. 4 is a block diagram showing a conventional MSK demodulation circuit.

FIG. 5 is a block diagram showing another conventional QPSK demodulation circuit.

FIG. 6 is a block diagram showing a configuration of a clock recovery circuit.

[Explanation of symbols]

 1 ... 1st multiplier, 2 ... 2nd multiplier, 3 ... 1st LPF, 4 ... 2nd LPF, 5 ... 90 degree phase shifter, 6 ... Voltage controlled oscillator, 7 ... 3rd LPF , 8 ... sixth multiplier, 9 ... third multiplier, 10 ... fourth multiplier, 11 ... fifth multiplier, 12 ... subtractor, 17 ... second changeover switch, 18 ... first Change switch, 19 ... Changeover switch control circuit, 20 ... Clock recovery circuit, 21 ... Reference oscillator, 24 ... Second mixer, 25 ... Second local oscillator, 26 ... Bandpass filter.

Claims (2)

[Claims] 1. A demodulator circuit of a receiver for receiving a QPSK modulated signal and an MSK modulated signal, wherein a first voltage controlled oscillator having a carrier frequency as a center frequency and a phase of an output signal of the first voltage controlled oscillator are 90
Phase-shifted first 90-degree phase shifter, the input modulation signal and the output signal of the first voltage-controlled oscillator 90-degree phase-shifted by the 90-degree phase shifter are multiplied, and synchronous detection is performed. And a second multiplier for performing synchronous detection by multiplying the input modulation signal by the output signal of the first voltage controlled oscillator, and a filter for the output signal of the first multiplier. A first filter that performs processing, a second filter that performs filtering on the output signal of the second multiplier, an output of the first filter and an output of the second filter, and the result is output. A third multiplier, a fourth multiplier that squares the output of the second filter, a fifth multiplier that squares the output of the first filter, and a fifth multiplier of the fifth multiplier. A subtractor for subtracting the output of the fourth multiplier from the output,
A clock regenerating circuit for regenerating a clock of a carrier wave, a multiplication of an output of the third multiplier and an output of the subtractor, and a multiplication of an output of the third multiplier and an output of the clock regenerating circuit. And a QPSK
When the modulated signal is received, the output of the subtractor is input to the sixth multiplier, and when the MSK modulated signal is received, the output of the clock recovery circuit is input to the sixth multiplier. The first changeover switch for performing the changeover control to the above and the fifth changeover switch when receiving the QPSK modulated signal.
Input the output of the multiplier of
When receiving a K-modulated signal, a second changeover switch that performs changeover control so that the output of the subtractor is input to the clock regeneration circuit, and a changeover operation of the first changeover switch and the second changeover switch are performed. When the QPSK modulated signal is received, the output of the subtractor is input to the sixth multiplier, and the output of the subtractor is a carrier wave. When used for reproduction, when receiving the MSK modulated signal, the output of the clock reproduction circuit is input to the sixth multiplier by the first changeover switch, and the output of the subtractor is output by the second changeover switch. Is input to the clock regeneration circuit and the output of the subtractor is used for clock regeneration,
A demodulation circuit for a digital modulated wave, wherein demodulated signals can be obtained for both QPSK modulated signals and MSK modulated signals by sharing the same functional block. 2. A demodulation circuit of a receiver for receiving a QPSK modulated signal and an MSK modulated signal, a frequency conversion circuit including a local oscillator which is a voltage controlled oscillator and a mixer for the modulated signal having an intermediate frequency, and the mixer. A band-pass filter (BPF) for filtering and outputting the output of the reference oscillator is disposed in the input unit, and a reference oscillator for outputting a constant oscillation signal, and a 90-degree phase shifter for shifting the phase of the reference oscillator by 90 degrees A first multiplier for performing synchronous detection by multiplying the input modulation signal by the output signal of the reference oscillator that has been phase-shifted by 90 degrees by the 90-degree phase shifter, the input modulation signal, and the reference A second multiplier that multiplies the output signal of the oscillator and performs synchronous detection;
First filter for filtering the output signal of the multiplier, the second filter for filtering the output signal of the second multiplier, the output of the first filter and the second filter A third multiplier for multiplying and outputting the output of the second filter, a fourth multiplier for squaring the output of the second filter, and a fifth multiplier for squaring the output of the first filter. , A subtractor for subtracting the output of the fourth multiplier from the output of the fifth multiplier, a clock recovery circuit for recovering a clock of a carrier wave, an output of the third multiplier and an output of the subtractor And a sixth multiplier for multiplying the output of the third multiplier and the output of the clock recovery circuit, and when receiving a QPSK modulated signal, the output of the subtractor is Input to sixth multiplier to receive MSK modulated signal In the case of receiving a QPSK modulated signal, the output of the clock recovery circuit is input to the sixth multiplier, and when the QPSK modulated signal is received, the output of the fifth multiplier is changed. A second changeover switch for performing a changeover control so as to input the output of the subtractor to the clock reproduction circuit when inputting to the clock reproduction circuit and receiving the MSK modulated signal;
A changeover switch control circuit for controlling the changeover operations of the changeover switch and the second changeover switch, and when the QPSK modulated signal is received, the output of the subtracter is changed by the first changeover switch. Input to a multiplier, the output of the subtractor is used for carrier recovery, and when the MSK modulated signal is received, the output of the clock recovery circuit is input to the sixth multiplier by the first changeover switch, By the selection operation of inputting the output of the subtractor to the clock recovery circuit and using the output of the subtractor for clock recovery by the second changeover switch, the same functional block is shared and Q
A demodulation circuit for a digitally modulated wave, characterized in that a demodulation signal can be obtained for both the PSK-modulated signal and the MSK-modulated signal.