JPH0653323A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH0653323A
JPH0653323A JP22518692A JP22518692A JPH0653323A JP H0653323 A JPH0653323 A JP H0653323A JP 22518692 A JP22518692 A JP 22518692A JP 22518692 A JP22518692 A JP 22518692A JP H0653323 A JPH0653323 A JP H0653323A
Authority
JP
Japan
Prior art keywords
fuse
layer
wiring
wiring layer
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP22518692A
Other languages
Japanese (ja)
Other versions
JP2817531B2 (en
Inventor
Masaharu Kikuchi
正治 菊地
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP22518692A priority Critical patent/JP2817531B2/en
Publication of JPH0653323A publication Critical patent/JPH0653323A/en
Application granted granted Critical
Publication of JP2817531B2 publication Critical patent/JP2817531B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

PURPOSE:To obtain a semiconductor device of multilayer interconnection structure having a fuse wherein the fuse is readily fused and no damage is caused to wiring layers. CONSTITUTION:A polycrystalline silicon fuse 13 is formed, by a low temperature CVD method, in an upper layer of a multilayer interconnection structure, composed of a first wiring layer 4 through a fourth wiring layer. This reduces the number of films through which laser beam passes in fusing of the fuse 13, and facilitates the fusing. In addition no damage due to heat is caused to lower wiring layers during the formation of the fuse 13.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は半導体装置に関し、特に
メモリ回路におけるヒューズの構造に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to the structure of a fuse in a memory circuit.

【0002】[0002]

【従来の技術】従来、半導体装置には冗長回路としての
ヒューズが設けられる。このヒューズは、例えばメモリ
回路において1つの半導体装置内にある幾つかのメモリ
セルのうち、一部が不良となった場合、その部分を使用
しないようにするときに、外部よりレーザ光でヒューズ
を溶断し、接続を切り換えるために使用している。図3
にその一例の断面図を示すように、基板1上にCVD法
により多結晶シリコンを全面に成長させ、フォトリソグ
ラフィによりヒューズ部のみを残しウェットエッチング
してヒューズ2を形成する。その後、窒化膜等の第1層
間絶縁膜3を形成し、ヒューズの両端に当たる部分にス
ルーホールを開け、更にその上に形成した第1配線層4
と接続する。その上に無機系又は有機系の絶縁膜である
第2層間膜5,第3層間膜7を積層し、第3層間膜7に
ヒューズ用の窓を開けている。ヒューズ2の溶断に際し
ては、第3層間膜7の窓を通してレーザ光を照射し、ヒ
ューズ2を加熱溶断させる。
2. Description of the Related Art Conventionally, a semiconductor device is provided with a fuse as a redundant circuit. For example, when a part of some memory cells in one semiconductor device in a memory circuit becomes defective, this fuse is used by a laser beam from the outside when the part is not used. Used to blow out and switch connections. Figure 3
As shown in a cross-sectional view of an example thereof, polycrystalline silicon is grown on the entire surface of the substrate 1 by the CVD method, and the fuse 2 is formed by photolithography by wet etching leaving only the fuse portion. After that, a first interlayer insulating film 3 such as a nitride film is formed, through holes are formed in the portions corresponding to both ends of the fuse, and the first wiring layer 4 formed further thereon.
Connect with. A second interlayer film 5 and a third interlayer film 7, which are inorganic or organic insulating films, are laminated on top of this, and a fuse window is opened in the third interlayer film 7. When the fuse 2 is blown, a laser beam is irradiated through the window of the third interlayer film 7 to heat and fuse the fuse 2.

【0003】[0003]

【発明が解決しようとする課題】この従来のヒューズで
は、使用する多結晶シリコンは素子の引出し電極として
も用いるため、配線層より下の層に形成する必要があ
る。このような構造の場合、配線層が1,2層ならばヒ
ューズを溶断するためのレーザ光は充分ヒューズ迄で到
達されるため、溶断を容易に行うことができる。また、
配線層が3層程度でも、上層の層間膜に窓を開けること
によりヒューズの溶断は可能である。
In this conventional fuse, since the polycrystalline silicon used is also used as the extraction electrode of the element, it must be formed in a layer below the wiring layer. In the case of such a structure, if the wiring layers are one or two layers, the laser light for blowing the fuse can reach the fuse sufficiently, so that the blowing can be easily performed. Also,
Even if there are about three wiring layers, the fuse can be blown by opening a window in the upper interlayer film.

【0004】しかし、近年配線の多層化が進んでおり、
5〜7層となった場合、層間膜が非常に厚くなるためレ
ーザ光がヒューズに達するまでに減衰してしまい、ヒュ
ーズの溶断ができなくなるおそれがある。また、ヒュー
ズ上部の多数の層間膜に窓を開けようとしても、5〜7
層では層間膜の厚さが数μmになってしまい、窓を開け
ることが困難になる。更に、ヒューズを配線層の上層に
作成しようとしても、通常の減圧CVD法では多結晶シ
リコンの成長温度が 650℃と高いため、下層に形成した
配線層にダメージを与えるため、ヒューズを作成するこ
とが困難になる。本発明の目的は、多層配線に適したヒ
ューズ構造を有する半導体装置を提供することにある。
However, in recent years, the number of wiring layers has increased,
In the case of 5 to 7 layers, the interlayer film becomes very thick, so that the laser beam is attenuated by the time it reaches the fuse, and there is a possibility that the fuse cannot be blown. Moreover, even if an attempt is made to open windows in many interlayer films on the fuse,
In the layer, the thickness of the interlayer film becomes several μm, which makes it difficult to open a window. Furthermore, even if a fuse is to be formed on the upper layer of the wiring layer, since the growth temperature of polycrystalline silicon is as high as 650 ° C. in the normal low pressure CVD method, the wiring layer formed on the lower layer is damaged, so the fuse should be formed. Becomes difficult. An object of the present invention is to provide a semiconductor device having a fuse structure suitable for multilayer wiring.

【0005】[0005]

【課題を解決するための手段】本発明は、多層配線構造
に設けられる多結晶シリコンのヒューズを、低温CVD
法により形成し、かつ多層配線構造の上層部に形成す
る。
According to the present invention, a polycrystalline silicon fuse provided in a multi-layer wiring structure is formed by low temperature CVD.
Formed by the method and formed in the upper layer portion of the multilayer wiring structure.

【0006】[0006]

【実施例】次に、本発明について図面を参照して説明す
る。図1は本発明の一実施例の断面図である。基板1上
に窒化膜等の下地絶縁膜3を形成し、素子と接続するた
めのコンタクトを開けたのち、アルミニウム又は金の第
1配線層4を形成する。その上に、有機又は無機の絶縁
膜である第1層間膜5を形成する。このような層構造を
4層繰り返し、第2配線層6,第2層間膜7,第3配線
層8,第3層間膜9,第4配線層10,第4層間膜1
1,第5配線層12からなる多層配線を形成する。
DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1 is a sectional view of an embodiment of the present invention. After forming a base insulating film 3 such as a nitride film on the substrate 1 and opening a contact for connecting to an element, a first wiring layer 4 of aluminum or gold is formed. A first interlayer film 5 which is an organic or inorganic insulating film is formed thereon. Such a layered structure is repeated four layers, and the second wiring layer 6, the second interlayer film 7, the third wiring layer 8, the third interlayer film 9, the fourth wiring layer 10, and the fourth interlayer film 1 are repeated.
A multi-layer wiring including the first and fifth wiring layers 12 is formed.

【0007】次に、アルミニウム又は金からなる第5配
線層12をヒューズ部分のみ配線が切断されるような形
でパターニングする。このようにした後、FIB(フォ
ーカス・イオン・ビーム)を用いた低温CVD法によ
り、第5配線層12のヒューズに当たる部分にタングス
テン膜を2000Åの厚さで選択的に成長させヒューズ13
を形成する。また、このヒューズ13はレーザ光を光源
とした光CVD法を用いてSiH4 ,N2 ,AsH3
原料ガスとした多結晶シリコンを選択的に成長すること
も可能である。その上で、全面にカバー絶縁膜14を形
成し、第5配線層12とヒューズ13を被覆する。
Next, the fifth wiring layer 12 made of aluminum or gold is patterned so that the wiring is cut only in the fuse portion. After this, a tungsten film is selectively grown to a thickness of 2000 Å on the portion of the fifth wiring layer 12 corresponding to the fuse by the low temperature CVD method using FIB (Focus Ion Beam).
To form. Further, this fuse 13 can also selectively grow polycrystalline silicon using SiH 4 , N 2 , and AsH 3 as source gases by using a photo-CVD method using a laser beam as a light source. Then, a cover insulating film 14 is formed on the entire surface to cover the fifth wiring layer 12 and the fuse 13.

【0008】この構成によれば、ヒューズ13は5層に
形成した配線構造の最上層に形成され、その上にはカバ
ー絶縁膜14が存在しているのみであるため、ヒューズ
13を溶断するためにレーザ光を照射したときには、レ
ーザ光はカバー絶縁膜14を透過するだけでヒューズ1
3に到達されることができ、溶断を容易に行うことがで
きる。一方、第5層までの配線層を形成した後にヒュー
ズ13を形成しているが、このヒューズ13はFIB,
光CVD法等の低温プロセスで形成できるため、他の配
線層にダメージを与えることはない。
According to this structure, the fuse 13 is formed in the uppermost layer of the wiring structure formed of five layers, and only the cover insulating film 14 is present thereon, so that the fuse 13 is blown. When the laser light is applied to the fuse 1, the laser light only passes through the cover insulating film 14.
3 can be reached and the fusing can be done easily. On the other hand, the fuse 13 is formed after the wiring layers up to the fifth layer are formed.
Since it can be formed by a low temperature process such as a photo CVD method, it does not damage other wiring layers.

【0009】図2は本発明の第2実施例の断面図であ
る。第1実施例と同様に第4層間膜11まで形成する。
その上で、水銀ランプを光源とした光CVD法により、
前記したのと同じ原料ガスにて全面に多結晶シリコンを
成長させ、フォトリソグラフィによりパターニングして
ヒューズ13を形成する。その上に第5層間膜15をを
形成し、ヒューズ13の両端に当たる部分にスルーホー
ルを開け、第5配線層12を形成し、ヒューズ13と第
5配線層12を接続する。更に、その上にカバー絶縁膜
14を形成する。この構成においても、ヒューズが最上
配線層の直下の層に形成されているため、レーザによる
溶断を容易に行うことができる。また、第1乃至第4配
線層を形成した後に低温プロセスによりヒューズ13を
形成しているので、これらの配線にダメージを与えるこ
とはない。
FIG. 2 is a sectional view of the second embodiment of the present invention. Similar to the first embodiment, the fourth interlayer film 11 is formed.
Then, by the optical CVD method using a mercury lamp as a light source,
Polycrystalline silicon is grown on the entire surface with the same source gas as described above, and patterned by photolithography to form the fuse 13. A fifth interlayer film 15 is formed thereon, through holes are formed in both ends of the fuse 13, a fifth wiring layer 12 is formed, and the fuse 13 and the fifth wiring layer 12 are connected. Further, the cover insulating film 14 is formed thereon. Also in this configuration, since the fuse is formed in the layer immediately below the uppermost wiring layer, the fusing with the laser can be easily performed. Further, since the fuse 13 is formed by the low temperature process after forming the first to fourth wiring layers, these wirings are not damaged.

【0010】[0010]

【発明の効果】以上説明したように本発明は、低温プロ
セスで成膜できるFIB法,光CVD法を用いて配線層
の上層部へヒューズを形成しているので、5〜7層とい
う今まで以上に厚い多層配線においても、ヒューズを溶
断するためのレーザ光を充分ヒューズにまで到達させる
ことができ、ヒューズの溶断を容易に行うことができる
と共に、ヒューズの形成に際して下層の配線層にダメー
ジを与えることはない。
As described above, according to the present invention, since the fuse is formed in the upper layer portion of the wiring layer by using the FIB method and the photo-CVD method which can be formed in the low temperature process, the number of layers is 5 to 7 layers. Even in the case of thick multilayer wiring, the laser light for blowing the fuse can reach the fuse sufficiently, the fuse can be easily blown, and the lower wiring layer is damaged when the fuse is formed. Never give.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の第1実施例の断面図である。FIG. 1 is a sectional view of a first embodiment of the present invention.

【図2】本発明の第2実施例の断面図である。FIG. 2 is a sectional view of a second embodiment of the present invention.

【図3】従来のヒューズ構造の断面図である。FIG. 3 is a cross-sectional view of a conventional fuse structure.

【符号の説明】[Explanation of symbols]

1 基板 3 下地絶縁膜 4,6,8,10 第1,第2,第3,第4配線層 5,7,9,11 第1,第2,第3,第4層間膜 12 第5配線層 13 ヒューズ 14 カバー絶縁膜 15 第5層間膜 1 Substrate 3 Base Insulating Film 4, 6, 8, 10 First, Second, Third, Fourth Wiring Layer 5, 7, 9, 11 First, Second, Third, Fourth Interlayer Film 12 Fifth Wiring Layer 13 Fuse 14 Cover insulating film 15 Fifth interlayer film

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 配線層と層間膜とで多層配線構造を有
し、かつその配線層の一部に多結晶シリコンで形成した
ヒューズを有する半導体装置において、前記ヒューズは
低温CVD法により形成され、かつ多層配線構造の上層
部に形成されたことを特徴とする半導体装置。
1. A semiconductor device having a multi-layer wiring structure including a wiring layer and an interlayer film, and having a fuse formed of polycrystalline silicon in a part of the wiring layer, wherein the fuse is formed by a low temperature CVD method, A semiconductor device formed on the upper layer of a multi-layer wiring structure.
JP22518692A 1992-07-31 1992-07-31 Semiconductor device Expired - Lifetime JP2817531B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP22518692A JP2817531B2 (en) 1992-07-31 1992-07-31 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP22518692A JP2817531B2 (en) 1992-07-31 1992-07-31 Semiconductor device

Publications (2)

Publication Number Publication Date
JPH0653323A true JPH0653323A (en) 1994-02-25
JP2817531B2 JP2817531B2 (en) 1998-10-30

Family

ID=16825315

Family Applications (1)

Application Number Title Priority Date Filing Date
JP22518692A Expired - Lifetime JP2817531B2 (en) 1992-07-31 1992-07-31 Semiconductor device

Country Status (1)

Country Link
JP (1) JP2817531B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5741731A (en) * 1994-12-19 1998-04-21 Yamaha Corporation Semiconductor device wired with fuse
US6218721B1 (en) 1997-01-14 2001-04-17 Nec Corporation Semiconductor device and method of manufacturing the same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5741731A (en) * 1994-12-19 1998-04-21 Yamaha Corporation Semiconductor device wired with fuse
US6218721B1 (en) 1997-01-14 2001-04-17 Nec Corporation Semiconductor device and method of manufacturing the same

Also Published As

Publication number Publication date
JP2817531B2 (en) 1998-10-30

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