JPH0652894B2 - Bit error rate measurement method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Outline] A bit error rate measuring method for measuring a bit error rate using an error rate converting memory, and counting error bits for the purpose of effectively utilizing an area of the error rate converting memory. A counter for performing an address operation based on the count value of the counter, and an error rate conversion memory for accessing a bit error rate by an address from the address circuit to read out a bit error rate. , A first offset value indicating the start address of the error rate conversion memory is added to the beginning, and a second offset value indicating the most significant digit position of the effective upper n digits of the count value of the counter is set to the first offset value. Next to the offset value, it is shifted to the right by one digit and added, and next to the second offset value, the most significant digit of the valid upper n digits of the count value of the counter is divided. The address with the added n-1 digits is formed, and the error rate conversion memory is accessed by the address to read the bit error rate.

[Industrial application field]

The present invention relates to a bit error rate measuring method for measuring a bit error rate using an error rate conversion memory.

There is known a bit error rate measuring method for obtaining a bit error rate in a communication system by using an error rate conversion memory composed of a read only memory (ROM), and it has been demanded that the error rate conversion memory can be effectively used. There is.

[Conventional technology]

FIG. 5 is an explanatory diagram of the communication system. On the transmission side, the transmission data is encoded into a convolutional code by the encoder 21, modulated by the transmission unit 22, and sent to the wired or wireless transmission path 23. To do. On the receiving side, the receiving section 24 receives and demodulates, and the decoder 25 performs error correction decoding to obtain received data.

In order to measure the bit error rate in such a communication system, conventionally, for example, the configuration shown in FIG. 6 has been adopted. That is, the received data output from the decoder 25 is encoded by the encoder 26, the received signal is delayed by the processing time of the encoder 26 by the delay circuit 27, and compared by the comparison circuit 28. The received signal is a coded signal containing error bits, and the output signal of the encoder 26 is a coded signal of error-corrected received data, and thus is a coded signal containing no error bits. Therefore, the bit of comparison disagreement in the comparison circuit 28 is an error bit, the error bit is counted by the counter 29, an address is formed by the address circuit 30 based on the count content of a predetermined time, and the error rate is generated by this address. The conversion memory 31 is accessed to read the bit error rate.

The error rate conversion memory 31 is a read only memory (RO
M), for example, as shown in FIG.
In the 16-bit address space, the start address is 2000 ₍₁₆₎ and the upper 20 bits make the address 20
00 to 2900 ₍₁₆₎ is specified, and an area in which addresses 0 to FF ₍₁₆₎ are specified by the lower 8 bits is stored, and a bit error rate that increases corresponding to the count value of the counter 29 is stored. .

FIG. 8 is an explanatory diagram of the address calculation in the address circuit 30, for example, a 16-digit count value b of the counter 29.
_{For 15} (MSB) to b ₀ (LSB) (binary number), find the digit with the leading "1" and use this as the leading valid 8
The digits are the lower 8 bits a _{7 to} a ₀ of the address. At this time, if the leading “1” of b ₆ or less of the count value is b,
The lower 8 bits a _{7 to} a ₀ of the address are assumed to be 8 significant digits _{7 to} b ₀ .

Also the first offset value represents a start address of an error rate conversion memory 31 in 4-bit _{a 15, a 14, a 13} , a 12, which is the upper 4 bits of the address. In addition, the bit position where the head of the count values b _{15 to} b ₀ is “1” is set to 4
The bits are represented by the second offset values a ₁₁ , a ₁₀ , a ₉ , and a ₈ and are added next to the first offset value. That is, when the count value b ₁₅ is “1”, the second offset value is set to “10”.
00 "expressed in, and _{b 8} of the count value is""can be expressed by. The _{b 6} of the count value following the leading" 0001 "When it is" 1 can be expressed by 0000 ". In other words, 4 The start position of the effective upper 8 digits can be represented by a bit.

By adding the first offset value, the second offset value, and the effective 8 digits, the 16-digit address a _{15 to} a ₀ is added.
Is formed, the error rate conversion memory 31 is accessed, and the bit error rate is read.

For example, the count values b _{15 to} b ₀ are “000001001”.
"In the case of _(2), b ₁₀ are '0110110 because it is 1", which b ₁₀ ~b ₃ becomes effective upper eight digits top a. The second offset value indicating the position of b ₁₀ a ₁₁ ~ a ₈ is "00
11 "become _(2). Then, the first offset value a ₁₅ ~a ₁₂ indicates the start address of an error rate conversion memory 31" 00
If 10 ” ₍₂₎ , the addresses a _{15 to} a ₀ are“ 001
0001110010110 " ₍₂₎ .

[Problems to be solved by the invention]

Top in the count value b ₁₅ ~b ₀ of counter 29 is "1"
When the position where is b ₇ or more is the position of b ₇ or more, the most significant digit of the effective upper 8 digits is “1”, and therefore the most significant bit a ₇ of the lower 8 bits of the address is always “1”. Therefore, the 7th
In the area of 2100 ₍₁₆₎ or more addresses in the figure, the hatched area of 80 ₍₁₆₎ or less of the address represented by the lower 8 bits is not used, and a useless area is generated.

An object of the present invention is to effectively use the area of the error rate conversion memory.

[Means for solving problems]

The error rate measuring method of the present invention is such that the area of the error rate conversion memory can be continuously used and will be described with reference to FIG.

A counter 1 for counting error bits, an address circuit 2 for performing an address operation based on the count value of the counter 1, and an error conversion memory 3 for accessing a bit error rate by an address from this address circuit and reading the bit error rate are provided. In the address circuit 2, a first offset value indicating the head address of the error rate conversion memory 3 is added to the head,
The second offset value indicating the most significant digit position in the effective upper n digits of the counter 1 is shifted to the right by one digit and added to the first offset value, and the counter is added next to the second offset value. An address is formed by adding n-1 digits excluding the most significant n significant digits of the count value of 1, and the error rate conversion memory 3 is accessed by this address to read the bit error rate.

[Action]

1st offset value, 2nd offset value, and effective upper n
By adding the digits and forming the address of the error rate conversion memory 3, by shifting the second offset value to the right,
The least significant bit of the second offset value will be added by masking the significant upper n digits and the most significant bit of the count value, and the least significant bit of this second offset value will be "0". Therefore, a continuous area can be accessed from the top address of the error rate conversion memory 3.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 2 is a block diagram of an embodiment of the present invention, in which 11 is a counter, 12 is an address circuit, 13 is an error rate conversion memory, 14 is a selector, 15 is an effective upper digit detector, and 16 is an error rate conversion memory 13. Is a register storing the first offset values a _{15 to} a ₁₂ indicating the start address of the second offset value, 17 is a second offset value forming unit forming the second offset values a _{11 to} a ₈ , and 18 is an adding circuit.

The detected error bit is added to the counter 11 and counted for a predetermined time, and the count values b _{15 to} b ₀ are added to the address circuit 12. The count values b _{15 to} b ₀ are added to the selector 14 and the valid upper digit detecting section 15, respectively. In the effective upper digit detecting section 15, the count value b ₁₅
"1" or whether or not the identification from the most significant digit in the order of ~b _0,
When the position of "1" is first found, the digit position information is added to the selector 14 and the second offset value forming unit 17.

The selector 14 counts the count value b ₁₅ to
It has a configuration to select and output the effective upper 8 digits from b ₀ ,
The eight significant significant digits are added to the adder circuit 18. In addition, the second offset value forming unit 17 selects and outputs by the selector 14 8
Second offset value a ₁₁ ~a showing the most significant digit position of the bit
₈ is formed and is shifted to the right by one digit and added to the adder circuit 18. In addition, the first offset values a _{15 to} a ₁₂ from the register 16
Is added to the adder circuit 18.

Therefore, in the adding circuit 18, the most significant eight significant digits selected and output by the selector 14 are set to the second offset value a ₁₁ to.
masked with the least significant bits of a _8, i.e., except for the most significant digit of the effective upper eight digits, which adds a first offset value and the second offset value, to form the address of an error rate conversion memory 13 And the adder circuit 18 has the first and second
This can be realized by an OR circuit configuration in which the digit positions of the offset value and the effective upper digit are selected and added. Alternatively, the counter 11, the address circuit 12, and the adder circuit 13 can be realized by the function of the processor.

FIG. 3 shows a flow chart of the address calculation of the embodiment of the present invention. First, the second offset values a _{11 to} a ₈ are set to the maximum “1000” ₍₂₎ , and the count values b _{15 to} b ₀ are set to b. _{When p} is set, p = 15 is set. And b _p =
It is determined whether it is "1". That is, it searches for the high-order digit of the count value b ₁₅ ~b ₀ "1" at the effective upper digit detector 15.

If b _p = not "1", and p-1, also a second offset value a ₁₁ ~a ₈ with -1 ,, = re _b p "1"
Or not. Repeating this, b _p =
When it becomes "1", the second offset value a ₁₁ ~ at that time
a a ₈ to 1 digit right shift. In the step, when p = 7 or less, the second offset values a _{11 to} a
₈ is not set to be negative, but is set to "0000" ₍₂₎ . Further, when p = 7 or less in the step, it is preferable to control so as to shift to the step without searching for "1" any more. In that case, p≤7.
It is only necessary to provide the judgment step of.

Next, a first offset value a ₁₅ ~a _12, 1 digit and second offset value a ₁₁ ~a ₈ were right shift, the upper seven digits excluding the most significant digit b _p of the effective upper eight digits of the count value b _{p-1 to} b _p-7
And are added by the adder circuit 18. Therefore, the least significant digit of the second offset value a ₁₁ ~a _8, the count value b ₁₅ ~b
_This means that the most significant eight significant digits of ₀ , b _p, are masked and added, and a _{15 to} a ₁₂ , 0, a _{11 to} a ₈ , b _p-1.
A 16-digit address of bp _-7 is formed.

For example, the count values b _{15 to} b _{0 of} the counter 11 that counts error bits are “000011001011011”.
0 "of _(2), b ₁₁ are '' because it is, b ₁₁ ~b ₄ becomes effective upper eight digits at the beginning of this. The" 1 b ₁₁ 1 "is the fourth from _{b 7} From the second offset value a _{11 to} a
₈ "0100" _(2), which the right-shifted one position to "00100" _(2), and also the first offset value a ₁₅ ~a ₁₂ indicates the start address of an error rate conversion memory 13 "00
If 10 ″ ₍₂₎ , the count values b _{15 to} b ₀ are added as shown in the step except for the most significant 8 high-order digits b ₁₁ of the count values b _{15 to} b _0. Therefore, the addresses a _{15 to} a ₀ are “00100”.
01001001011 ".

Figure 4 is a region diagram of an error rate conversion memory embodiment of the present invention, the left side shows the in-use area A~K the conventional example, the effective upper eight digits in the address a ₁₅ ~a ₀ by most significant digit _{a 7} becomes "1", area B~K will be composed of 80~FF address from 2000 to 1900 _{(16) (16).} In contrast, in the present invention, except for the most significant digit a ₇ of the effective upper eight digits, because one using the least significant digit a ₈ of the second offset value a ₁₁ ~a _8,
As shown on the right side, when a ₈ = “0”, the address 200
The area of 0 to 80 ₍₁₆₎ of 0 to 2900 ₍₁₆₎ is A, C,
Use E, G, I, as K, also when _a 8 = "1", to use the region of 80~FF ₍₁₆₎ of the address _{2000~2900 (16) B, D,} F, H, a J be able to.

Since the areas A to K are composed of consecutive addresses,
As the error rate conversion memory, there is no useless area and it can be effectively used.

In the above embodiment, the address of the error rate conversion memory 13 is set to 1
As 6-bit configuration, while indicating if it can instruct the 64K address space, the address configuration are those can be arbitrarily selected, and the count value b ₁₅ ~b ₀
It shows the case of 8 digits as the effective upper n digits of
The value of n is selected according to the range of the storage area of the error rate.

〔The invention's effect〕

As described above, according to the present invention, after the first offset value indicating the leading address of the error rate conversion memory 3, the effective upper n digits of the uppermost digit position of the address value are indicated, and the first digit is shifted right by one digit. 2 offset values are added, and then the most significant n significant digits of the count value are added, and the address of the error rate conversion memory 3 is formed by the address circuit 2. Thereby, the error rate conversion is performed. Since the addresses of the memory 3 can be continuously used, there is an advantage that the error rate conversion memory 3 can be effectively used.

[Brief description of drawings]

FIG. 1 is a diagram for explaining the principle of the present invention, FIG. 2 is a block diagram of an embodiment of the present invention, FIG. 3 is a flow chart of address operation of the embodiment of the present invention, and FIG. 4 is an error of the embodiment of the present invention. FIG. 5 is an explanatory view of the area of the rate conversion memory, FIG. 5 is an explanatory view of the communication system, FIG. 6 is a block diagram of the conventional example, FIG. 7 is an area explanatory view of the error rate conversion memory of the conventional example, and FIG. 8 is a conventional example. 6 is an explanatory diagram of the address calculation of FIG. 1 counter, 2 address circuit, 3 error rate conversion memory, 11 counter, b _{15 to} b ₀ count value, 12 address circuit, 13 error rate conversion memory, 14 selector, 15 effective significant digit detection Section, 16 is a register, 17 is a second offset value forming section, 18 is an adder circuit, and a _{15 to} a ₁₂
Is a first offset value, and a _{11 to} a ₈ are second offset values.

Claims (1)

[Claims] 1. A counter (1) for counting error bits.
And an address circuit (2) for performing an address operation based on the count value of the counter (1), and an error rate conversion memory (3) for accessing by an address from the address circuit (2) and reading a bit error rate. In the address circuit (2), a first offset value indicating the head address of the error rate conversion memory (3) is added to the head, and the effective upper n of the count value of the counter (1) is added. A second offset value indicating the position of the most significant digit in the digit is shifted to the right by one digit next to the first offset value and added, and the second offset value is added next to the counter (1). N− excluding the most significant n significant digits of the count value
A bit error rate measuring method, wherein an address is formed by adding one digit, and the bit rate is read by accessing the error rate conversion memory (3) by the address.