JPH0652122A - Load distribution system for multi-cpu system - Google Patents

Abstract

PURPOSE:To execute system resetting through one reset line by arbitrary CPU units which are distributively loaded on plural sub-tracks and to separate system resetting and individual bus resetting in a multi-CPU system. CONSTITUTION:A direction register controlling the signal transmission direction of the reset line is provided for a common bus buffer unit connecting an external bus with an internal bus in the sub-track. An individual bus reset register which sets whether the CPU unit 2-1 receiving the reset signal from the reset line is to transmit the reset signal received in the individual I/O unit under control, which is connected by an individual bus 10, as it is or not is provided for the CPU unit 2-1.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a load distribution system in a multi CPU system. In a control computer system, a multi-CPU system capable of parallel processing and redundancy by providing a plurality of CPUs is becoming widespread in response to demands for high-speed processing, high-volume processing, and high reliability (non-stop). .

In this case, in order to improve the processing speed of the entire system, it is desirable that the CPUs be made to handle the load evenly.

[0003]

2. Description of the Related Art FIG. 3 is a multi-CPU to which the present invention is applied.
It is a block diagram of a system. In FIG. 3, 1-1 to 1-3 are CPUs, 2-1 to 2-3 are I / O units, 3 is a common memory, 4 is a common bus, and 5 is a bus arbitration circuit. Interrupt notification lines 6-1 to 6-3 are individually provided from each I / O unit to all CPUs to notify the occurrence of processing requested to the CPUs.

Each I / O unit 2-1 to 2-3 is a CP
It is subordinate to U with equal qualification, and under the control of one of the CPUs, it transmits and receives data to and from one CPU via the common bus 5. When each CPU receives a processing request from the I / O unit, it takes in data from the I / O unit, performs predetermined signal processing, and writes it in the data area of the common memory 3.

In the conventional multi-CPU system, the method in which each CPU shares the execution of the processing requested by the I / O unit is as follows. The I / O unit is
When a processing request is generated, the generation of the processing request is notified to all the CPUs by a dedicated interrupt notification line of its own I / O unit. Each CPU judges whether or not to accept the interrupt request according to the priority level, and the CPU that has decided to accept the bus usage request arbitrates the bus usage request to acquire the common bus usage right to access the I / O unit. Notify the circuit 5 and request arbitration. The bus arbitration circuit 5 gives the right to use the bus in advance according to the priority order determined by the CPU ID and the like. The given CPU accesses the processing request I / O unit via the common bus and executes the requested processing.

[0006]

In the conventional method of acquiring processing, when a specific CPU receives a processing request from an I / O unit having a high interrupt priority, it arbitrates even if the other CPU is available. attend to. Then, the bus arbitration circuit gives the bus use right based on the CPU priority that is fixed in advance, and the CPU that has acquired the bus use right interrupts the process being executed at that time and prioritizes the request from the corresponding I / O unit. Then do.

Therefore, there is a problem in that the interrupt processing is concentrated on the CPU having a high priority in the bus arbitration circuit, the load is applied to a specific CPU regardless of the load state of each CPU, and as a result, the overall processing capability is reduced. there were.

The present invention has been made in view of the above problems, and an object of the present invention is to provide a load distribution system that evenly allocates the processing loads of multiple CPUs to the CPUs.

[0009]

FIG. 1 shows a multi-C of the present invention.
It is a block diagram of the load distribution system of a PU system. In order to solve the above problems, a load distribution method of a multi-CPU system according to the present invention, as shown in FIG. 1, includes a plurality of CPU units (1-1 to 1-3) and a plurality of CPU units that require processing. I /
The O units 2-1 to 2-3 and a common memory 3 accessible from all CPUs are connected by a common bus 4, and a bus arbitration circuit 5 that arbitrates for a bus use request from each CPU is provided. I / O in a multi-CPU system
An execution waiting processing queue 31 for registering the contents of processing requests generated by the unit in a FIFO format is provided on the common memory 3,
The CPU that has received the notification of the generation of the processing request by the interrupt from the I / O requests the bus arbitration circuit 5 to perform the arbitration requesting the bus use, and the CPU that wins the arbitration sends the content of the processing request to the execution waiting processing queue. I / O by writing to 31
Accepts processing requests from the unit and sends each CP
U is adapted to take out the contents of the oldest process among the accepted and unexecuted processes from the waiting process queue 31 and execute the process each time the currently executed process ends. This is solved by the load distribution method of the CPU system.

[0010]

[Operation] C for receiving a processing request from the I / O unit
Since only the PU is determined by the bus arbitration, and the CPU that has become available is responsible for executing the processing, the processing is distributed to each CPU and the overall processing capability can be improved.

[0011]

Embodiments of the present invention will be described below with reference to the accompanying drawings. FIG. 1 is a configuration diagram of a load distribution system of a multi-CPU system of the present invention, and FIG. 2 is a flowchart showing the processing procedure. Note that the same reference numeral represents the same object throughout the drawings.

A feature of the present invention is that a waiting queue for processing is provided on a common memory, a CPU that participates in bus arbitration in response to a processing request from an I / O unit, and a CPU that has acquired the bus use right by arbitration is Only the acceptance process for registering the content of the process request is performed, and the execution of the request process becomes available C
Since it is performed by the PU and is otherwise the same as the configuration described above with reference to FIG. 3, the description thereof will be omitted.

In FIG. 1, an execution waiting processing queue 31 is provided on the common memory 3 which is accessed by all the CPUs via the common bus 4. The waiting process queue 31 is a process registration area 31 that stores vector numbers indicating the contents of the process.
a, a start pointer SP indicating the address of the head of the unexecuted process in the process registration area, an end pointer EP indicating the address of the process last received, and the execution waiting process queue being accessed. A control area area 31b having a busy flag F indicating that

When a plurality of CPUs simultaneously request the use of the common bus, the bus arbitration circuit 5 arbitrates in accordance with a predetermined priority order determined by CPUID or the like, and uses the bus for one CPU. Give the right.

Next, the processing procedure in the system having the above configuration will be described with reference to the flowchart of FIG.
At the time of system initialization, the CPU performing initialization initializes the start pointer SP and the end pointer EP of the execution waiting processing queue.
Is initialized by setting to 0 (STEP
1).

After the system is started up, each CPU receives the notification of the processing request from the I / O unit through the interrupt line (STEP 2). When the CPU that has received the interrupt notification has a higher interrupt priority of the processing request from the I / O that is generated this time than the processing being executed at that time, the bus arbitration circuit 5 uses the bus to respond to the request I / O unit. Make a request.
(STEP 3) The bus arbitration circuit 5 receives bus use requests simultaneously from a plurality of CPUs that have determined a response to the current I / O interrupt request.
U is determined and the fact is notified to the corresponding CPU via the system bus (STEP 4).

A CPU that has won arbitration by accepting a processing request
Performs access processing by accessing the I / O unit that issued the processing request via the common bus and writing the processing content in the execution waiting processing queue on the common memory. (ST
EP5).

As described above, only the processing request is accepted by the CPU that has won the arbitration. This acceptance processing is performed by writing the request processing content and the processing request I / O address in the common memory as follows.

First, the CPU that has acquired the bus returns the interrupt acceptance signal IACK to the I / O unit. When the I / O unit that issued the interrupt request receives the interrupt acceptance signal IACK, it sends the interrupt vector to the CPU via the common bus.
Send to. The CPU refers to the in-use flag F of the common memory 4, and when the flag is not set, the other CPU
Recognizes that it is not accessing the area and sets the flag to "1". Then, the interrupt vector indicating the processing content is written to the address designated by the end pointer EP, the end pointer is updated to a value incremented by 1, the busy flag is set to "0", and the bus is released.

According to the above procedure, whenever a processing request is issued to the I / O unit, the CPU that wins the arbitration registers the processing content in the execution waiting processing queue to receive the processing request.

Next, when all the CPUs have finished the job being processed and become free (STEP 6), after confirming that the busy flag F is not set, the values of the end pointer EP and the start pointer are set. Refer to (STEP
7) Check if the two numbers are equal (ST
EP8).

If they are not equal to each other, they are placed in the waiting queue,
Recognize that a process that has been accepted and has not been executed is waiting (STEP 9), and confirms that the busy flag is "0",
The busy flag is set to "1", the interrupt vector number, which is the content of the process, and the address of the I / O requesting the process are read from the execution waiting registration area designated by the start pointer SP, and the process is started. And the start pointer is incremented by 1, and the in-use flag F
Is returned to "0". (STEP 9) By accessing the I / O unit in a predetermined manner, the above STEP 1 is performed.
Execute the specified process started with 0. (STEP 10) As described above, the CPU that wins the bus right arbitration only receives the processing request from the I / O unit, and the received processing requests are sequentially executed by the CPUs that are not processing. Since it is possible to distribute the load in consideration of the operating status, the load is evenly distributed without the processing being concentrated on a specific CPU.

[0023]

As described above, according to the present invention, in the multi-CPU system, the processing loads of all CPUs are equalized, and the processing speed of the entire system is improved.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a load distribution system of a multi-CPU system of the present invention

FIG. 2 is a flowchart of processing acceptance / execution according to an embodiment.

FIG. 3 is a configuration diagram of a multi-CPU system to which the present invention is applied.

[Explanation of symbols]

1-1 to 1-3 CPU, 2-1 to 2-3 I / O unit, 3
... common memory, 31 ... waiting process queue, 31a ... processing registration area, 31b ... control area, 4 ... common bus, 5 ... bus arbitration circuit, 6-1 to 6-3 ... interrupt request line

Claims (1)

[Claims] 1. A plurality of CPU units (1-1 to 1-3),
A plurality of I / O units (2-1 to 2-
3) and a common memory (3) accessible from all CPUs are connected by a common bus (4), and has a bus arbitration circuit (5) that arbitrates for a bus use request from each CPU. In the multi-CPU system, an execution waiting processing queue (31) for registering the contents of processing requests generated by the I / O units (2-1 to 2-3) in the FIFO format is provided on the common memory 3, and the I / O units are The CPU (1-1 to 1-3), which has received the notification that the processing request has been generated by the interrupt from (2-1 to 2-3), issues a bus use request to the bus arbitration circuit 5, requests arbitration, and performs arbitration. The winning CPU accepts the processing request from the I / O unit by writing the content of the processing request in the execution waiting processing queue (31), and each CPU waits for the execution of the processing currently being executed. From the process queue 31, the highest of the accepted and unexecuted processes Is a load distribution method for a multi-CPU system characterized in that the contents of old processing are extracted and executed.