JPH0651956A - Difference absolute value cumulative adder circuit - Google Patents

Abstract

PURPOSE:To provide a difference absolute value cumulative adder circuit in which the whole circuit scale can be decreased when the amount of data and the number of bits of the data in each adder is equal, respectively, and the amount of input data or the number of bits can be increased when the circuit scale is equal by reducing the required number of adders. CONSTITUTION:Difference absolute value arithmetic circuits 101-10N each are comprised of subtractors which find the difference value of two numerals consisting of (i) bits and a bit inversion switching circuit which outputs a subtraction result as it is when no borrow-output is issued from the subtractor and finds the (complement on 1) of a difference absolute value by inverting a bit of subtraction result when the borrow-output is issued. A multi-input adder 112 inputs a borrow to the least significant bit, and also, adds the computed result of each difference absolute value arithmetic circuit, and the adder 113 adds the output value of the multi-input adder 112 cumulatively.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a differential absolute value cumulative addition circuit used for obtaining a correlation between two data.

[0002]

2. Description of the Related Art Conventionally, for example, in the field of image processing technology, 2
When performing pattern matching of two image data,
Correlation between both image data is required. The correlation of the image data is obtained by obtaining the absolute value of the difference between the pixel data of the same coordinates in the two image data for each pixel and cumulatively adding them. For example, in FIG.
When obtaining the correlation between two image data represented by screen A and screen B, (A1-B1), (A2-B2), (A3
-B3), ..., (AK-BK), ... Absolute values are sequentially obtained, and the absolute values of the differences are cumulatively added to obtain a value representing one correlation. A
1 to AK and B1 to BK represent gradation values of pixel data at each coordinate. The subscripts 1 to K may be omitted and designated as A and B, which may be collectively shown as image data. Such arithmetic processing is an essential technique for motion vector detection between frames, which is a moving image coding method.

FIG. 8 shows the configuration of a conventional differential absolute value cumulative addition circuit. In FIG. 8, A1, A2, ..., A
N is N first data each consisting of i bits, which corresponds to N pixel data A1 to AN among the image data of the screen A shown in FIG. 7, for example. Further, in FIG. 8, B1, B2, ..., BN are i
It is N second data consisting of bits, which is shown in FIG.
It corresponds to N pixel data B1 to BN of the image data of the screen B shown in FIG. Here, generally N <K.
Further, in FIG. 8, the absolute difference calculator 11 is A1-B.
1, the absolute value of the difference is calculated by A2-B2.
The absolute value of the difference is calculated, and the difference absolute value calculator 1N calculates the absolute value of AN-BN. The multi-input adder 2 adds all the outputs of the N absolute difference value calculators 11, 12, ..., 1N. The adder 3 temporarily stores the addition result of the multi-input adder 2 in the accumulator 4, and when the addition result of the next multi-input adder 2 is input, the addition result is added to the value of the accumulator 4. In this way, the adder 3 can cumulatively add the calculation results of the multi-input adder 2. Therefore, using the circuit as described above, the screen A and the screen B are
Of the pixel data A1, A2,
, AN and pixel data B1, B2, ..., BN are sequentially input, the adder 3 can obtain the difference absolute value cumulative addition result.

Next, the absolute difference value calculator 1 shown in FIG.
9 and 10 show two different configuration examples of 1, 12, ..., 1N. The i-bit subtractor 5 is a subtractor that performs a subtraction of AB, and the i-bit inverter 6 is an inverter (inverter) that inverts each bit of the i-bit subtraction result output from the i-bit subtractor 5. ). The "2's complement" is obtained by the i-bit inverter 6 and the +1 incrementer 7. When the subtraction result of the subtractor 5 is positive (sign = 0), the selector 8 outputs the subtraction result of the subtractor 5 as it is,
If the subtraction result is negative (sign = 1), the subtraction result “2
Is output. By this, the absolute value of AB is obtained.

In FIG. 10, the subtractor 5 subtracts AB, and the subtractor 9 subtracts BA. Selector 8
When the subtraction result of the subtractor 5 is positive (sign = 0), the subtraction result of the subtractor 5 is output as it is, and when the subtraction result of the subtractor 5 is negative (sign = 1), the subtraction of the subtractor 9 is performed. The subtraction result of the subtractor 9 is output until the result becomes positive. By this, the absolute value of AB is obtained.

FIG. 11 shows an example of the circuit configuration of the subtracter 5 and the subtractor 9 of the difference absolute value calculator shown in FIGS. 9 and 10. The subtractor 5 and the subtractor 9 are composed of i adders (full adders, abbreviated as “FA”) 21 to 2i, and when a carry occurs in each of the adders 21 to 2i, the carry of the adder in which the carry occurs The carry is output from the output terminal C to the carry input terminal C0 of the adder for the upper bits.
Input data a11 to a1i, which are the minuends, are input to the input terminals U of the adders 21 to 2i, and the values of the input data b11 to b1i, which are the subtraction, are inverted to the input terminal V (when it is "1", "0" , And becomes "1" when it is "0".) Is input, 1 is input to the carry input terminal C0 of the least significant bit, and 1 is added to the inverted value of the input data b11 to b1i. . Therefore, the input data a11 to a
1i and the “two's complement” of the input data b11 to b1i are added, that is, the input data a11 to a1i and the input data b11 to b1i are subtracted. As a result of the subtraction, the subtracted values S1 to S from the output terminals S of the adders 21 to 2i and the carry output terminals of the most significant bit adder 2i.
i and carry Ci are output. The carry Ci is 1 when the subtraction result is positive, and the carry Ci is negative when the result is negative.
Becomes 0, the code can be judged by this carry Ci.

FIG. 12 shows an example of the circuit configuration of the +1 incrementer 7 of the difference absolute value calculator shown in FIG. The +1 incrementer 7 includes i adders (full adder, abbreviated as “F”).
A ”) 31 to 3i, and when a carry occurs in each of the adders 31 to 3i, a carry is carried from the carry output terminal C0 of the adder in which the carry is generated to the carry input terminal C of the adder for performing the addition of the upper bit. Is output. Input data a21 to a2i, which are augends, are input to the input terminals U of the adders 31 to 3i, and the adder 3 of the least significant bit is input.
The adder 1 is input to the input terminal V of 1 and the input terminals V of the other high-order bit adders 32 to 3i are fixed to 0 and addition is performed. Bit adder 3 as a result of addition
The addition values S11 to S1i and the carry C1i are output from the output terminals S of 1 to 3i and the carry terminal C of the most significant bit adder 3i. The input data of the carry input terminal C0 of the adder 31 of the least significant bit is fixed at 0.

FIG. 13 shows the configuration of the multi-input adder 2 shown in FIG. In FIG. 13, the first bit adder 41,
The second bit adder 42, ..., The i-th bit adder 4i add | AB | for the first bit, the second bit ,. | AB | i is | AB
Represents the value of the i-th bit of |. Here, each of the i-th bit adder 4i to the first-bit adder 41 is a multi-input adder having an input number N. For example, the i-th bit adder 4i is N
The i-th bit of each operation result output from each of the absolute difference value calculators 11 to 1N is added, and the first bit adder adds the i-th bit of each operation result output from the N difference absolute value calculators 11 to 1N. Add the first bit.

As such a multi-input adder, Wallac
An e Tree adder circuit can be used. Here, FIG. 14 shows a configuration example of a multi-input adder having, for example, 8 inputs. 8
The input adder 50 is an 8-input Wallace Tree adder circuit 51.
And 2-input high-speed adder (Carry Look Ahead adder)
8 input Wallace Tree adder circuit 51
FIG. 15 shows a circuit diagram of the above.

The 8-input Wallace Tree adder circuit 51 is composed of a first bit adder 61 to an eighth bit adder 68, and an nth (n is an integer of 1 to 8) bit adder is an nth bit adder.
Bit input data dn1 to dn8 are input. As shown in FIG. 15, each of the bit adders 61 to 68 is basically composed of a plurality of three-input adders (abbreviated as “FA”), and the adder includes input data and a lower bit adder. The carry inputs are sequentially added, and if a carry occurs, the carry input is output to the upper bit adder. The adders of the bit adders 61 to 68 are arranged in a tree shape as shown in FIG. 15, and the number of inputs is sequentially reduced, and finally, the carry C2 in each of the bit adders 61 to 68.
1-2A and addition value S21-2A are calculated and output. By thus performing addition in each bit adder, the number of adders can be reduced, and addition can be performed efficiently.

For example, in the fourth bit adder 64, the adder 71 adds input data d41 to d43, the adder 72 adds input data d44 to d46, and the adder 73 inputs The data d47 and d48 are added. The adders 71 to 73 input the input data d41 to d.
As a result of adding 48, the added value S is added to the adders 74 and 75.
And carry C to the fifth bit adder 65. The adder 74 adds the carry C input from the third bit adder 63 and the added value S input from the adder 71, and the adder 75 adds the carry C input from the third bit adder 63. C is added to the added value S input from the adders 72 and 73.

As a result of adding the above-mentioned data, the adder 74 outputs the addition value S to the adder 77 and the carry C to the fifth bit adder 65. As a result of adding the above-mentioned data, the adder 75 outputs the addition value S to the adder 76 and the carry C to the fifth bit adder 65. The adder 76 adds the carry C input from the third bit adder 63 and the addition value S input from the adder 75, outputs the addition value S to the adder 77, and the carry C is generated. If it does, it outputs to the 5th bit adder 65. The adder 77 adds the carry C input from the third bit adder 63 and the addition value S input from the adders 74 and 76 to obtain the addition value S24 and the carry C24 at the fourth bit. Output. The circuit configurations of the fourth bit adder to the seventh bit adder are the same.

In this way, although the addition is performed in each bit adder, the carry C generated in the eighth bit adder 68 is sequentially added, and the adders 81 to 83 add the ninth bit. And add
The adder 84 adds the 10th bit. Next, the addition values S21 to S2A obtained by the adders of the first bit adder 61 to the eighth bit adder 68 and the carry C21.
8 to C2A, as shown in FIG. 8, the 2-input high-speed adder 52 sequentially performs cumulative addition, and outputs a final addition value with a maximum of 11 bits.

Also in the multi-input adder circuit 2 shown in FIG. 13, the same addition as in the 8-input adder circuit 50 of FIG. 15 is performed, and each of the first bit adder 41 to the i-th bit adder 4i is added. The added value S and the carry C obtained are cumulatively added by a high-speed adder 30 such as a Carry LookAhead adder as shown in FIG. 6, and the final addition result | AB of the multi-input adder circuit 2 is obtained. Can be output to the adder 3. The CarryLook Ahead adder 40 improves the addition processing speed by performing addition of each bit of the addend and the augend and performing the carry calculation independently.

[0015]

As described above, in the conventional difference absolute value cumulative addition circuit, the difference absolute value calculator 1 is used.
When 1 to 1N are configured as shown in FIG. 9, an adder is required for each bit of the input data. Therefore, as shown in FIG. 11, the number of adders is i for the i-bit subtractor, and FIG. As shown in FIG. 10, +1 incrementer requires i in total of 2i, and in the case of the configuration shown in FIG.
Since one i-bit subtractor is provided with i adders, a total of 2i adders are required. Therefore, FIG.
In the difference absolute value cumulative addition circuit in which the N difference absolute value calculators 11 to 1N shown in (1) are used, 2Ni adders are required even only for the difference absolute value calculation part.

As described above, in the conventional differential absolute value cumulative addition circuit, since a large number of adders are required, the overall circuit scale becomes large, and the data number of input data and the bit number of each data cannot be increased so much. There was a problem.

An object of the present invention is to reduce the required number of adders, to reduce the overall circuit scale when the number of data and the number of bits of each data are the same, and to reduce the total circuit scale. Is to provide a difference absolute value cumulative addition circuit capable of increasing the number of input data or the number of bits.

[0018]

SUMMARY OF THE INVENTION The present invention comprises an i-bit subtractor for determining two difference values each consisting of i-bits,
When there is no borrow output from the i-bit subtractor, the subtraction result of the i-bit subtractor is output as it is, and when there is borrow output from the i-bit subtractor, the subtraction result of the i-bit subtractor is bit-inverted and output. A plurality of differential absolute value arithmetic circuits including a bit inversion switching circuit, and a multi-input adder circuit that inputs the borrow of each differential absolute value arithmetic circuit as the least significant bit and adds the subtraction result of each differential absolute value arithmetic circuit And a cumulative addition circuit that cumulatively adds the outputs of the multi-input addition circuit.

[0019]

According to the present invention, the absolute difference cumulative addition circuit is
It is composed of a plurality of absolute difference value calculation circuits, a multi-input addition circuit, and a cumulative addition circuit. The i-bit subtractor of each difference absolute value calculation circuit obtains two difference values each consisting of i-bits, and the bit inversion switching circuit outputs the subtraction result of the i-bit subtractor when there is no borrow output from the i-bit subtractor. When the borrow output is present, the subtraction result of the i-bit subtractor is bit-inverted and output. Therefore, when there is no borrow output, the difference absolute value of the two numbers is output as it is, and when there is a borrow output, the “1's complement” of the difference value of the two numbers is output. On the other hand, the multi-input adder circuit inputs the borrow of each difference absolute value operation circuit as the least significant bit and adds the operation results of each difference absolute value operation circuit. When a borrow is output from the difference absolute value calculation circuit, the calculation result of the difference absolute value calculation circuit is the “1's complement” of the difference value between two numbers, so a borrow, that is, 1 is set to the least significant bit. Adding is equivalent to taking the “two's complement” of the difference value, and is equivalent to adding two difference absolute values. If there is no borrow output from the difference absolute value calculation circuit, the least significant bit is set to 0.
Is added, the two absolute difference values are correctly added. In this way, the multi-input addition circuit obtains the addition result of the absolute difference values for each of a plurality of pairs of data. And the cumulative addition circuit
The output of the multi-input adder circuit is cumulatively added to obtain the difference absolute value cumulative addition result.

[0020]

FIG. 1 shows the configuration of a differential absolute value cumulative addition circuit according to an embodiment of the present invention. In FIG. 1, X1, X2,
, XN are N first input data each consisting of i bits, and Y1, Y2, ..., YN are N second input data each consisting of i bits. The absolute difference calculators 101, 102, ..., 10N are shown in FIG.
Unlike the absolute difference value calculators 11, 12, ..., 1N shown in FIG. 1, as will be described later, it outputs two differential absolute values or “one's complement” of two differential values together with borrow. The multi-input adder 112 includes the difference absolute value calculators 101, 10
2, ..., 10N, the i-bit subtraction results are input and added, and the difference absolute value calculators 101,
102, ..., borrows b1, b2 output from 10N
, BN are input to the least significant bit adder of the multi-input adder 112 and added.

The adder 113 temporarily stores the addition result of the multi-input adder 112 in the accumulator 114. When the addition result of the next multi-input adder 112 is input, the addition result is compared with the value of the accumulator 114. And add.
Therefore, by using such a circuit, the first input data X1, X2, ..., XN and the second input data Y1, Y2,
, YN are sequentially input to adder 113
Can obtain the difference absolute value cumulative addition result. First input data X1 to XN and second input data Y1 to Y
The suffixes 1 to N of N may be omitted and designated as X and Y, which may be collectively shown as input data.

FIG. 2 is a difference absolute value calculator 1 shown in FIG.
The structure of 01-10N is shown. In FIG. 2, the subtractor 11
Reference numeral 5 denotes a subtracter for performing an X-Y operation, and a bit inverter (inverter) 116 inverts each bit of the i-bit subtraction result output from the subtractor 115. The selector 118 is
When the subtraction result of the subtractor 115 is positive (borrow b = 0), the XY value is output as it is, and when the subtraction result of the subtractor 115 is negative (borrow b = 1), the bit inverter 1
The value bit-inverted by 16, that is, the "1's complement" of XY is output together with borrow. Here, the outputs of the absolute difference value calculators 101 to 10N are collectively represented by | X−Y |.

FIG. 3 shows a circuit configuration example of the subtractor 115 of the difference absolute value calculator shown in FIG. The subtractor 115 uses i
Adders (full adder, abbreviated as “FA”) 121 to 12
i, and when a carry occurs in each of the adders 121 to 12i, the carry output terminal C of the adder in which the carry occurs to the carry input terminal C0 of the adder of the higher bit.
The carry is output. Input data x11 to x1i, which are the minuends, are input to the input terminals U of the adders 121 to 12i, and input data y11, which is the subtraction, are input to the input terminal V.
~ The value of y1i is inverted (when it is "1", it becomes "0",
When it is "0", it becomes "1". ) Is input. 1 is input to the carry input terminal C0 of the least significant bit, and 1 is added to the inverted value of the input data y11 to y1i. Therefore, since the input data x11 to x1i and the “two's complement” of the input data y11 to y1i are added,
That is, the input data x11 to x1i and the input data y11
~ Y1i is subtracted. Result of subtraction, adder 1
Subtracted values S51 to S5i and carry C5i are output from the output terminals S of 21 to 12i and the carry output terminal of the most significant bit adder 12i. The carry C5i becomes 1 when the subtraction result is positive, and the carry C5i when the subtraction result is negative.
Since 5i becomes 0, the code can be determined by this carry C5i.

FIG. 4 shows the multi-input adder 112 shown in FIG.
Shows the configuration of. In FIG. 4, the first bit adder 13
1, 2nd bit adder 132, ..., i-th bit adder 1
3i performs | X−Y | addition for the first bit, the second bit, ..., And the i-th bit, respectively. | X−Y | i is
The value of the i-th bit of | X−Y | is shown. Here, each of the i-th bit adder 13i to the second bit adder 132 is a multi-input adder having the number of inputs N. For example, the i-th bit adder 13i outputs from the N difference absolute value calculators 101 to 10N. The i-th bit of each calculated result is added, and the second bit adder 132 outputs N difference absolute value calculators 101 to 1
The second bit of each operation result output from 0N is added. The first bit adder 131 is a multi-input adder with 2N inputs, and is output from each difference absolute value calculator together with the first bit of each calculation result output from the N difference absolute value calculators. The borrows b1, b2, ..., BN are added.

In this way, in the multi-input adder 112, when the borrow is output from the difference absolute value operation circuits 101 to 10N, the operation result "1's complement" output from the difference absolute value operation circuit and its Since borrow is added, it is equivalent to taking the "2's complement" of the operation result,
The absolute value of the calculation result can be obtained.

As such a multi-input adder, Wallac
An e Tree adder circuit can be used. Here, for example, a configuration example of an 8-input multi-input adder is shown in FIG. However, since the borrow is input to the first bit adder, the number of input data is 16. The 8-input adder 150 has 8
Input Wallace Tree Adder circuit 151 and high-speed adder (Ca
rry Look Ahead adder) 152, 8 input Wa
A circuit diagram of the llace Tree adder circuit 151 is shown in FIG.

The 8-input Wallace Tree adder circuit 151
In the n-th (n is an integer of 2 to 8) bit adder including the first bit adder 161 to the eighth bit adder 168, the n-th bit input data en
1 to en8 are input, and input data e11 to e18 and borrows b1 to b8 are input to the first bit adder. As shown in FIG. 6, each bit adder is basically composed of a three-input adder (full adder, abbreviated as “FA”), and each adder carries input data and a carry input from the lower bit adder. Are sequentially added, and if a carry occurs, it is output to the upper bit adder. The adders of the bit adders 161 to 168 are, as shown in FIG.
The bits are arranged in a tree shape and the number of inputs is sequentially reduced. Finally, in each bit adder 161-168, carry C61-6A and addition value S61-6A are calculated and output. In this way, each bit adder 161-16
In 8, the number of adders can be reduced by performing addition, and the addition can be performed efficiently.

For example, in the fourth bit adder 164, the adder 171 adds the input data e41 to e43, and the adder 172 inputs the input data e44 to e47.
Of the input data e47, e
Add 48. As a result of adding the input data e41 to e48, the adders 171 to 173 output the added value S to the adders 174 and 175 and the carry C to the fifth bit adder 165. The adder 174 adds the carry C input from the third bit adder 163 and the addition value S input from the adder 171, and adds the adder 175.
Is the carry C input from the third bit adder 163.
And the addition value S input from the adders 172 and 173 are added.

As a result of adding the above-mentioned data, the adder 174 outputs the addition value S to the adder 176 and the carry C to the fifth bit adder 165. Adder 175
Outputs the addition value S to the adder 177 as a result of adding the above-mentioned data, and the carry C to the fifth bit adder 16
Output to 5. The adder 176 is the third bit adder 16
Carry C input from 3 and addition value S input from adder 174 are added, and the addition value S is added to adder 1
When the carry C is generated, it is output to the fifth bit adder 165. The adder 177 adds the carry C input from the third bit adder 165 and the adder 175.
And the addition value S input from the adder 176 are added, and the addition value S64 and the carry C6 in the fourth bit are added.
4 is output. The circuit configurations of the fourth bit adder to the seventh bit adder are the same.

In this way, each bit adder 161 ...
Although addition is performed in 168, the carry C generated in the eighth bit adder is sequentially added in the carry C, the ninth bit is added in adders 181 to 183, and the adder 184 adds , The 10th bit is added. Next, the addition values S61 to S6A and the carrys C61 to C6A obtained by the adders of the first bit adder 161 to the eighth bit adder 168 are:
As shown in FIG. 4, the addition is performed by the high-speed adder 152, and the final addition value is output with 11 bits at maximum.

The number of input data of the first bit adder 161 is the same as that of the conventional first bit adder 6 shown in FIG.
Compared to 1, there is an increase of borrow input data b1 to b8, that is, there are eight more inputs. As the borrow input data b1 to b8 increase, the adders 191 to 194 increase in the first bit adder 161, and the carry C is output from the adders 191 to 194 in the second bit adder 162. In order to perform the addition, the number of adders 195 and 196 is increased, and the total of six adders is increased.

Also in the multi-input adder circuit 112, the same addition as in the 8-input adder circuit 150 shown in FIG. 6 is performed,
The addition value S and carry C obtained by the adders of the first bit adder 131 to the i-th bit adder 13i are accumulated by the 2-input high-speed adder 130 such as the Carry LookAhead adder as shown in FIG. The addition is performed, and the final addition result | X−Y | of the multi-input circuit can be output to the adder 113. The Carry Look Ahead adder improves the addition processing speed by performing the carry calculation independently while performing addition for each bit of the addend and the augend.

The i-th bit adder 13i shown in FIG.
..., the second bit adder 132 has W for each input number N
The first bit adder 131 can be configured by an allace Tree adder circuit, and the first bit adder 131 can be configured by a Wallace Tree adder circuit having 2N inputs. Like this, Wallace Tree
Since the adder circuit is a circuit in which adders are connected in a tree shape to increase the number of inputs, the number of adders required for each increase in the number of inputs can be suppressed to one or less.

Compared with the multi-input adder circuit 2 in the conventional differential absolute value cumulative addition circuit shown in FIG. 13, the multi-input adder 112 in the differential absolute value cumulative addition circuit shown in FIG. 1 is different. The input number of the first bit adder 131 is increased from N to 2N because the inputs of the borrows b1 to bn are increased. Further, along with this, as shown in the configuration example of FIG. 6, the number of adders of the first bit adder 131 increases, and the carry C is output from the adder to the second bit adder 132. In the bit multi-input adder 132, the number of adders for adding the carry C increases, and in the same manner, the number of additions in the high-bit multi-input adder increases. The total number of increased adders in each bit adder can be estimated to be about N when the number of inputs in the first bit adder 131 increases by N.

Further, compared with the conventional difference absolute value calculator shown in FIG. 9, the difference between the difference absolute value calculator according to the present invention shown in FIG. 2 is that the +1 incrementer 7 is not provided. Is. Therefore, the +1 incrementer 7 of the conventional difference absolute value calculator is provided with i adders as shown in FIG. 12, and the difference absolute value cumulative addition circuit shown in FIG. 11 has N difference absolute values. Since the arithmetic units 11 to 1N are provided, the conventional differential absolute value arithmetic unit is provided with a larger number of Ni adders as a whole than the differential absolute value arithmetic unit of the present invention. Further, the number of adders of the conventional difference absolute value calculator shown in FIG. 10 is equal to the number of adders of the i-bit subtractor 9, that is, i, from the number of adders of the difference absolute value calculator of the present invention shown in FIG. Many are provided. Therefore, the number of adders of the conventional difference absolute value calculator shown in FIG. 10 is larger than the number of adders of the difference absolute value calculator of the present invention by Ni in the total difference absolute value cumulative addition circuits 101 to 10N. There is.

From the above, the number of adders in the difference absolute value cumulative addition circuit of the present invention is the difference absolute value calculator 101.
-10N, the conventional difference absolute value calculators 11 to 1
Compared to the conventional multi-input adder 2, the number of Ni is smaller than that of the conventional multi-input adder 2 by N, and thus the total number of inputs is larger than that of the conventional differential absolute value cumulative addition circuit.
Ni-N = (i-1) N is less. As a result, the number of adders required for the differential absolute value cumulative addition circuit of the present invention is significantly reduced as compared with the conventional one, and when the number of data N is large, it is reduced to approximately 1/2 as compared with the conventional one. It will be.

[0037]

As described above, according to the present invention, in the difference absolute value arithmetic circuit for obtaining the difference value of two numbers, when there is borrow output, the "1's complement" of the arithmetic result is sent to the multi-input adder. Output. In addition, the borrow is the first of the multi-input adder.
The result is output to the bit adder, and +1 is added to the operation result to make it a "2's complement" collectively in the multi-input first bit adder in the subsequent stage.

Therefore, the number of adders required for the difference absolute value calculation can be greatly reduced, and the overall circuit scale can be greatly reduced. Moreover, if the circuit scale is the same, the number of input data or the number of bits of each data can be increased.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of a differential absolute value cumulative addition circuit that is an embodiment of the present invention.

FIG. 2 is a diagram showing respective difference absolute value calculators 101 to 10 in FIG.
It is a figure which shows the structure of N.

FIG. 3 is a diagram showing a configuration example of an i-bit subtractor 115 in FIG.

FIG. 4 is a diagram showing a configuration of a multi-input adder 112 in FIG.

5 is a diagram showing a configuration example of a multi-input adder 112 in FIG.

FIG. 6 is an 8-input Wallace Tree adder circuit 1 in FIG.
It is a circuit diagram of 51.

FIG. 7 is a diagram showing an example of image data when the correlation between two image data is obtained.

FIG. 8 is a diagram showing a configuration of a conventional differential absolute value cumulative addition circuit.

9 is a diagram showing a configuration example of difference absolute value calculators 11 to 1N in FIG.

10 is a diagram showing another configuration example of the absolute difference value calculators 11 to 1N in FIG.

FIG. 11 is an i-bit subtractor 5 in FIGS. 9 and 10.
3 is a diagram showing a configuration example of an i-bit subtractor 9 and FIG.

12 is a diagram showing a configuration example of an incrementer 7 in FIG.

13 is a diagram showing a configuration of a multi-input adder 2 in FIG.

14 is a diagram showing a configuration example of a multi-input adder 2 in FIG.

15 is a circuit diagram of an 8-input Wallace Tree adder circuit 55 in FIG.

[Explanation of symbols]

 101-10N Difference absolute value calculator 112 Multi-input adder 113 Adder 114 Accumulator 115 i-bit subtractor 116 Inverter 118 Selector 121-12i Full adder 130 High-speed adder 131-13i-bit adder 151 8-input Wallace Tree Adder circuit 152 High-speed Adder 161-168 bit adder

Claims (1)

[Claims] 1. An i-bit subtractor for obtaining a difference value of two numbers each consisting of i-bits, and a subtraction result of the i-bit subtractor is output as it is when there is no borrow output from the i-bit subtractor. When there is a borrow output from the subtractor, a plurality of difference absolute value subtraction circuits including a bit inversion switching circuit that bit-inverts and outputs the subtraction result of the i-bit subtractor; Difference absolute value accumulation, characterized in that it includes a multi-input addition circuit that inputs as a bit and adds the subtraction results of each difference absolute value subtraction circuit, and a cumulative addition circuit that cumulatively adds the outputs of the multi-input addition circuit. Adder circuit.