JPH0650598B2 - RAM / ROM selectable semiconductor memory device - Google Patents

Description

TECHNICAL FIELD The present invention relates to a read / write memory (hereinafter referred to as “ROM”), which is a writable / readable memory (hereinafter referred to as “R”).
AM ”. The present invention relates to a semiconductor memory device having a memory cell that can also be used as a).

(Prior Art) When a variable data part and a fixed data part are required in the same chip, a chip having an independent RAM and ROM wastes a memory area due to the ratio of the variable data part and the fixed data part. Therefore, in order to efficiently use the memory area, in a semiconductor memory device having a memory cell composed of a flip-flop and a MOS transistor serving as a writing / reading gate, the gate of the driving MOS transistor of the flip-flop is used. Depending on whether the contact is provided between the common potential points and is used in the open state or the closed state, the RAM is
Also, a ROM that can be used as a ROM has been proposed (see JP-A-55-160392).

However, in that memory device, even if the memory cell is a RAM or a ROM, it can be used only as a memory cell for one bit, and there is a drawback that the utilization efficiency of the memory cell is low.

(Object) It is an object of the present invention to provide a semiconductor memory device in which the same memory cell can be used as both a RAM and a ROM, and when it is used as a ROM, the capacity can be doubled. It is intended.

(Structure) A semiconductor memory device of the present invention includes a flip-flop, a pair of bit lines, and a MOS transistor connected to each bit line and serving as a gate at the time of writing / reading.
The OS transistor can be connected to either the flip-flop or the constant potential point, and the decoder for selecting a pair of bit lines can be connected.

Examples will be specifically described below.

FIG. 1 shows a memory cell according to an embodiment of the present invention.

Reference numerals 1 and 2 are P-type MOS transistors as load resistance elements, and 3 and 4 are drive N-type MOS transistors.
The sources of the S transistors 3 and 4 are connected to the GND terminal, and the sources of the MOS transistors 1 and 2 are connected to the power supply Vcc terminal. By connecting the drain node N ₁ of the MOS transistors ₁ and 3 to the gates of the MOS transistors 2 and 4, and connecting the drain node N ₂ of the MOS transistors ₂ and 4 to the gates of the MOS transistors 1 and 3. , MOS transistors 1, 2, 3, and 4 form a flip-flop.

13 and 14 are bit lines, and the bit line 13 has an N-type M
The drain of the OS transistor 5 is connected to the bit line 1
The drain of the N-type MOS transistor 6 is connected to 4. The MOS transistors 5 and 6 are MOS transistors that serve as gates when writing / reading. 15 is a word line, and the word line 15 is a MOS transistor 5,
It is connected to the gate of 6.

A contact 7 is provided at the source of the MOS transistor 5, and a contact 11 is provided at the node N _{1 of the} flip-flop.
Is provided. Reference numeral 9 is a contact connected to the GND terminal. The contacts 7 and 9 and the contacts 7 and 11 are arranged so that they can be connected by forming a metal wiring. A contact 8 is provided at the source of the MOS transistor 6, and a contact 12 is provided at the node N _{2 of the} flip-flop. Reference numeral 10 is a contact connected to the GND terminal. These contacts are also arranged so that the contacts 8 and 10 and the contacts 8 and 12 can be connected by forming a metal wiring.

FIG. 2 shows a memory cell and a decoder. Reference numeral 17 is the memory cell shown in FIG. An X decoder 18 is connected to the word line 15. On the other hand, a pair of bit lines 1
MOS transistors 22 and 24 are inserted in 3 and 14, respectively.
The Y decoder 20 is connected to the gate of the No. 4.

The pair of bit lines 13 and 14 are cut at appropriate positions. This cutting position can be set arbitrarily. Contacts 26 and 34 are provided at the cutting position of the bit line 13, and a MOS transistor 23 is arranged near the cutting position, and contacts 28 and 36 are also provided at the source and drain of the MOS transistor 23. ing. These contacts 26, 28, 34, 36 are
Between contacts 26 and 34 or contacts 26 and 28
And the contacts 34 and 36 are arranged so that they can be connected by forming a metal wiring. Contacts 30 and 38 are also provided at the cutting position of the bit line 14, and the MOS transistor 2 is provided near the cutting position.
5 is arranged, and contacts 32 and 40 are also provided to the source / drain of the MOS transistor 25. These contacts 30, 32, 38, 40 are also arranged so that they can be connected by forming metal wiring between the contacts 30 and 38, or between the contacts 30 and 32 and between the contacts 38 and 40.

Reference numeral 44 is a 1-bit equivalent decoder equipped with an inverter 42. The gate of the MOS transistor 23 is connected to the inverted output of the decoder 44, and the MOS transistor 25
Is connected to the input terminal 46 which is the non-inverted output of the decoder 44.

When this memory cell is used as a RAM, contacts 7 and 11, 8 and 12 are connected in FIG. 1, and contacts 26 and 34 and contacts 30 and 28 are connected in FIG. The contact is connected by forming a metal wiring using a mask.
An arbitrary address can be designated by designating a row-direction RAM cell group by the X decoder 18 and a column-direction RAM cell group by the Y decoder 20.

On the other hand, when this memory cell is used as a ROM, it is fixed to "0" or "1" in FIG. 1 depending on whether the contact 7 of the MOS transistor 5 is connected to the contact 9 by a metal wiring. ROM is formed, and the other ROM fixed to "0" or "1" is formed depending on whether the contact 8 of the MOS transistor 6 is connected to the contact 10 by a metal wiring. In this way, two ROMs are formed from one memory cell. Further, in FIG. 2, between the contacts 26 and 28 and between the contacts 34 and 3 on the bit line 13 side.
6 are connected, and between the contacts 30 and 32 and between the contacts 38 and 40 on the bit line 14 side. As a result, the two ROMs in the memory cell are selected by the X decoder 18 and the Y decoder 20, and the decoder 44 is added.
Will select one of them. Decoder 44 increases the Y decoder capability by one bit.

In the embodiment, the memory cell is of CMOS type,
It may be of NMOS type.

Further, in the embodiment, a contact is provided so that the memory cell can be set to the RAM or the ROM by forming the metal wiring.

The memory cell of the present invention can also be applied to a gate array. In that case, after forming a contact hole using a mask at a necessary position among the positions where the contact is provided in the embodiment, a metal wiring is further formed using the mask.

In the gate array, it is easy to change the configuration of the Y decoder. Therefore, it is effective to use the memory device of the present invention in which a bit line changes depending on whether it is a RAM or a ROM in a gate array.

(Effect) As described above, according to the present invention, by setting a slight amount of wiring on the memory cell and on the decoder section, one memory cell can form one bit in the RAM and two bits in the ROM can be doubled. Therefore, the area efficiency is improved as a memory cell for both RAM and ROM.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a memory cell used in an embodiment of the present invention, and FIG. 2 is a circuit diagram showing an embodiment of the present invention together with a decoder. 1 to 6 ... MOS transistor, 7 to 12, 26, 28, 30, 32, 34, 36, 3
8, 40 ... Contact, 13, 14 ... Bit line, 15 ... Word line, 18 ... X decoder, 20 ... Y decoder, 44 ... Decoder.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification number Reference number within the agency FI Technical indication location 7210-4M H01L 27/10 433 (72) Inventor Keiichi Yoshioka 1-3-3 Nakamagome, Ota-ku, Tokyo No. 6 Within Ricoh Co., Ltd. (56) Bibliography SHO 61-93896 (JP, U)

Claims (1)

[Claims] 1. A flip-flop, a pair of bit lines,
M connected to each bit line to serve as a gate for writing and reading
An OS transistor is provided, the MOS transistor can be connected to either the flip-flop or the constant potential point, and a decoder for selecting a pair of bit lines can be connected. A characteristic semiconductor memory device.