JPH0650340U - Terminal structure of electronic parts - Google Patents
Terminal structure of electronic partsInfo
- Publication number
- JPH0650340U JPH0650340U JP088666U JP8866692U JPH0650340U JP H0650340 U JPH0650340 U JP H0650340U JP 088666 U JP088666 U JP 088666U JP 8866692 U JP8866692 U JP 8866692U JP H0650340 U JPH0650340 U JP H0650340U
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- bonding pad
- bonding
- pad
- wire
- main
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-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/494—Connecting portions
- H01L2224/4943—Connecting portions the connecting portions being staggered
- H01L2224/49431—Connecting portions the connecting portions being staggered on the semiconductor or solid-state body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/494—Connecting portions
- H01L2224/4943—Connecting portions the connecting portions being staggered
- H01L2224/49433—Connecting portions the connecting portions being staggered outside the semiconductor or solid-state body
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
(57)【要約】
【目的】 ボンディングワイヤの修理打ちを可能とす
る。
【構成】 配線部４に形成された主ボンディングパッド
５の基部に予備ボンディングパッド６を直列に形成し
た。
【効果】 主ボンディングパッドに剥離が生じても、予
備ボンディングパッドを利用してボンディングワイヤの
修理打ちを行うことができ、製造歩留まりを向上でき
る。
(57) [Summary] [Purpose] Repair bonding of bonding wires is possible. [Structure] A preliminary bonding pad 6 is formed in series on the base of the main bonding pad 5 formed on the wiring portion 4. [Effect] Even if the main bonding pad is peeled off, the bonding wire can be repaired by using the auxiliary bonding pad, and the manufacturing yield can be improved.
Description
【０００１】[0001]
この考案は、ワイヤボンディングによって接続が行われる電子部品におけるボ ンディングパッドの改良に関する。 The present invention relates to improvement of a bonding pad in an electronic component that is connected by wire bonding.
【０００２】[0002]
ＩＣ等の電子部品の電極端子と、基板上にパターン形成されている配線部ある いは他の電子部品の電極端子との間をワイヤボンディングによって電気的に接続 する場合には、配線部に他の部分より幅が広くなったボンディングパッドが形成 される。図３はその一例を示したもので、１１は電子部品、１２はその側縁に沿 って配列されている複数の電極端子、１３は電子部品１１が実装される基板、１ ４は電極端子１２に対応して基板１３上に形成された複数の配線部、１５は各配 線部１４の先端に設けられているボンディングパッドであり、ボンディングワイ ヤ１６をボンディングすることにより対応する電極端子１２とボンディングパッ ド１５との間が接続される。 When electrically connecting the electrode terminals of electronic parts such as ICs and the wiring parts patterned on the substrate or the electrode terminals of other electronic parts by wire bonding, the wiring parts should be different from each other. Bonding pads having a width wider than that of the above are formed. FIG. 3 shows an example thereof, 11 is an electronic component, 12 is a plurality of electrode terminals arranged along the side edge thereof, 13 is a substrate on which the electronic component 11 is mounted, and 14 is an electrode terminal. A plurality of wiring portions formed on the substrate 13 corresponding to 12 and 15 are bonding pads provided at the tip of each wiring portion 14, and the corresponding electrode terminals 12 are formed by bonding the bonding wires 16. And the bonding pad 15 are connected.
【０００３】 例えばＣＯＧ方式の液晶表示素子の場合には、電子部品１１は駆動用のＩＣ、 基板１３はガラス基板の一方であり、表示部用の透明導電膜からなる電極がシー ル部の外まで引き出されて配線部１４として利用される。この場合には、配線部 １４の表面にボンディングワイヤ１６との密着強度の大きなアルミニウムや金等 の材料を積層することが行われるが、透明導電膜とこれらの材料との密着力を高 めるためにクロム等の中間層が一般に設けられる。In the case of a COG type liquid crystal display element, for example, the electronic component 11 is a driving IC and the substrate 13 is one of a glass substrate, and an electrode made of a transparent conductive film for a display portion is provided outside the seal portion. Is used as the wiring portion 14. In this case, a material such as aluminum or gold having a high adhesion strength with the bonding wire 16 is laminated on the surface of the wiring portion 14, but the adhesion between the transparent conductive film and these materials is increased. For this purpose, an intermediate layer such as chromium is generally provided.
【０００４】 しかしながら、液晶表示素子の高精細化が進むにつれて配線部１４のパターン ピッチが小さくなり、必然的に配線部１４の線幅も小さくなって十分な密着強度 を得ることが次第に困難になり、ワイヤボンディングの際にボンディングパッド １５が透明導電膜と中間層との界面から剥離して断線するという現象が生じやす くなる。図４はこの剥離状態を示したものであり、１４ａは透明導電膜、１４ｂ はクロム等の中間層、１４ｃはアルミニウムや金等の表面層である。具体的な数 値例を示すと、図５の(a)のようにボンディングパッド１５の大きさが２００× １６０μｍの場合にはワイヤボンディング時のパッドの剥離不良の発生率は０． １％以下であるのに対して、(b)のように配線ピッチが小さくなって大きさが１ ５０×１２０μｍになると剥離不良発生率が２．６％に増加するという結果とな っている。However, as the definition of the liquid crystal display element becomes higher, the pattern pitch of the wiring portion 14 becomes smaller, and the line width of the wiring portion 14 becomes smaller inevitably, and it becomes gradually difficult to obtain sufficient adhesion strength. During wire bonding, the phenomenon that the bonding pad 15 separates from the interface between the transparent conductive film and the intermediate layer and breaks easily occurs. FIG. 4 shows this peeled state, in which 14a is a transparent conductive film, 14b is an intermediate layer of chromium or the like, and 14c is a surface layer of aluminum or gold. As a concrete numerical example, when the size of the bonding pad 15 is 200 × 160 μm as shown in FIG. While it is 1% or less, as shown in (b), when the wiring pitch becomes small and the size becomes 150 × 120 μm, the peeling failure occurrence rate increases to 2.6%. .
【０００５】 また、ボンディングパッドの縁部は中心部よりも接着力が弱いために、面積が 比較的大きな場合でもワイヤの位置がずれてパッドの縁部にボンディングされる と、パッドは縁部から剥離して結果的に断線してしまうこともある。いずれにし ても、剥離断線してしまうとボンディングワイヤの修理打ちはできず、製造歩留 まりを低下させる一因となっていた。Also, since the edge of the bonding pad has a weaker adhesive force than the central portion, even if the area is relatively large, if the wire is misaligned and bonded to the edge of the pad, the pad is removed from the edge. It may peel off and eventually break. In either case, if peeling and disconnection occur, the bonding wire cannot be repaired and driven, which is one of the causes of lowering the manufacturing yield.
【０００６】[0006]
この考案はこの点に着目し、ボンディングワイヤの修理打ちを可能とすること を課題としてなされたものである。 With this in mind, the present invention has been made with the task of making it possible to repair the bonding wire.
【０００７】[0007]
上述の課題を解決するために、この考案では、配線部に形成された主ボンディ ングパッドの基部に予備ボンディングパッドを直列に形成している。 In order to solve the above-mentioned problems, in this invention, a preliminary bonding pad is formed in series on the base of the main bonding pad formed on the wiring portion.
【０００８】[0008]
ワイヤのボンディングは主ボンディングパッドに対して行われるが、仮にパッ ドが剥離して断線することがあっても、予備ボンディングパッドを利用してボン ディングワイヤの修理打ちを行うことができる。 Although wire bonding is performed with respect to the main bonding pad, even if the pad is peeled off and the wire is broken, the bonding wire can be repaired by using the spare bonding pad.
【０００９】[0009]
次に、ＣＯＧ方式の液晶表示素子における一実施例について説明する。 図１において、１は駆動用ＩＣ、２はその側縁に沿って配列されている複数の 電極端子、３は駆動用ＩＣ１が実装されるガラス基板、４は電極端子２に対応し てガラス基板３上に形成された複数の配線部である。この配線部４は例えば厚さ ２０００Åの透明導電膜、５００Åのクロム層、１００００Åのアルミニウム層 を順に連続スパッタ法により成膜し、その上にポジレジストを塗布して所定パタ ーンのマスクを介して露光し、各々の層をエッチングして形成されている。 Next, an example of a COG type liquid crystal display device will be described. In FIG. 1, 1 is a driving IC, 2 is a plurality of electrode terminals arranged along the side edges, 3 is a glass substrate on which the driving IC 1 is mounted, 4 is a glass substrate corresponding to the electrode terminal 2. 3 is a plurality of wiring portions formed on. The wiring portion 4 is, for example, a transparent conductive film having a thickness of 2000 Å, a chromium layer having a thickness of 500 Å, and an aluminum layer having a thickness of 10000 Å are sequentially formed by a continuous sputtering method. Exposed, and each layer is etched.
【００１０】 ５は主ボンディングパッド、６は予備ボンディングパッドであって、主ボンデ ィングパッド５は各配線部４の先端に設けられ、また予備ボンディングパッド６ は主ボンディングパッド５の基部に直列に形成されており、両ボンディングパッ ド５，６間にはくびれ部７が形成されている。８はボンディングワイヤであり、 通常は互いに対応する電極端子２と主ボンディングパッド５の間がワイヤ８のボ ンディングによって接続される。Reference numeral 5 is a main bonding pad, 6 is a preliminary bonding pad, the main bonding pad 5 is provided at the tip of each wiring portion 4, and the preliminary bonding pad 6 is formed in series at the base of the main bonding pad 5. A constricted portion 7 is formed between the bonding pads 5 and 6. Reference numeral 8 is a bonding wire, and the electrode terminal 2 and the main bonding pad 5 which correspond to each other are normally connected by the bonding of the wire 8.
【００１１】 この実施例は上述のような構成であり、仮に主ボンディングパッド５にワイヤ ８がボンディングされてパッド５がガラス基板３から剥離した場合でも、予備ボ ンディングパッド６との間にくびれ部７があるため剥離が予備ボンディングパッ ド６にまで波及することが少ない。従って、図中にＡで示すように剥離した主ボ ンディングパッド５に続く予備ボンディングパッド６にワイヤ８をボンディング しなおすことにより、該当する電極端子２と配線部４の間を接続することが可能 であり、この部品が不良品として廃棄処分される事態を回避できるのである。This embodiment has the above-described structure, and even if the wire 8 is bonded to the main bonding pad 5 and the pad 5 is peeled off from the glass substrate 3, the constricted portion is formed between the spare bonding pad 6 and the spare bonding pad 6. Since there is 7, peeling rarely spreads to the pre-bonding pad 6. Therefore, by rebonding the wire 8 to the preliminary bonding pad 6 following the peeled main bonding pad 5 as shown by A in the figure, it is possible to connect the corresponding electrode terminal 2 and the wiring portion 4. Therefore, it is possible to avoid the situation where this part is discarded as a defective product.
【００１２】 上記の主ボンディングパッド５と予備ボンディングパッド６は例えば図５の(b )に例示したものと同様な１５０×１２０μｍの大きさであり、その間隔が１０ ０μｍ以下、好ましくは１０〜４０μｍになるようにくびれ部７が形成される。 図２の(a)はこれを図示したものであり、この程度の寸法のくびれ部７があれば 主ボンディングパッド５で生じた剥離が予備ボンディングパッド６に及ぶことは 十分防止できる。ちなみに、上述のように透明導電膜２０００Å、クロム層５０ ０Å、アルミニウム層１００００Åを成膜し、各層をエッチングして配線部４を 形成した後、配向処理、シール材印刷、スペーサ散布、圧着、分断、液晶注入、 ＩＣのダイアタッチと、通常の液晶パネルの製造工程を経て太さ３２μｍの金ワ イヤ８でボンディングし、更に剥離不良の箇所を修理打ちしてボンディングを終 了した。その結果、最終的な剥離不良率は０．０６％となり、この考案の効果を 確認することができた。The main bonding pad 5 and the auxiliary bonding pad 6 have a size of, for example, 150 × 120 μm similar to that illustrated in FIG. 5B, and the distance between them is 100 μm or less, preferably 10-40 μm. The constricted portion 7 is formed so that FIG. 2A shows this, and if there is a constricted portion 7 having such a size, it is possible to sufficiently prevent the peeling generated at the main bonding pad 5 from reaching the preliminary bonding pad 6. By the way, as described above, the transparent conductive film 2000Å, the chromium layer 500Å, and the aluminum layer 10000Å are formed, and after each layer is etched to form the wiring portion 4, the alignment treatment, the sealing material printing, the spacer dispersion, the pressure bonding and the cutting are performed. After the liquid crystal injection, IC die attachment, and the normal liquid crystal panel manufacturing process, the bonding was completed by bonding with the gold wire 8 having a thickness of 32 μm, and repairing the defective peeling portion. As a result, the final peeling failure rate was 0.06%, confirming the effect of this invention.
【００１３】 なお、この考案は図２の(a)のようなパッド配置に限定されるものではなく、 基板３のスペースや配線部４のパターンなどに応じて他の配置を採用することが できる。図２の(b)はその一例であって、パッド５とパッド６の間隔を各パッド の長さ以上に広げ、その間に隣接する配線部４のパッド５あるいはパッド６がは まり込むような配置とした例を示している。The present invention is not limited to the pad arrangement as shown in FIG. 2A, and other arrangements can be adopted depending on the space of the substrate 3 and the pattern of the wiring portion 4. . FIG. 2 (b) is an example of such an arrangement, in which the distance between the pad 5 and the pad 6 is made wider than the length of each pad, and the pad 5 or the pad 6 of the adjacent wiring portion 4 is fitted between them. Is shown as an example.
【００１４】[0014]
上述の実施例から明らかなように、この考案は、ＣＯＧ方式の液晶表示素子や ＥＬパネルのように半導体素子を基板上に搭載したものなど、導電膜からなる配 線部のボンディングパッドとこれに対応する電極端子との間をワイヤボンディン グによって電気的に接続する構造の電子部品において、配線部に形成された主ボ ンディングパッドの基部に予備ボンディングパッドを直列に形成するようにした ものである。 従って、ワイヤがボンディングされて主ボンディングパッドに剥離が生じるこ とがあっても、予備ボンディングパッドを利用してボンディングワイヤの修理打 ちを行うことが可能となって、製造歩留まりを向上し、また信頼性を高めること ができるのであり、特に配線部の線幅が小さく、ボンディングパッドに剥離が起 きやすい高精細化された超小型の電子部品の場合に大きな効果が得られる。 As is apparent from the above-described embodiments, the present invention provides a bonding pad for a wiring part made of a conductive film such as a COG type liquid crystal display device or a semiconductor device mounted on a substrate such as an EL panel. In an electronic component with a structure in which it is electrically connected to the corresponding electrode terminal by wire bonding, a preliminary bonding pad is formed in series at the base of the main bonding pad formed in the wiring part. is there. Therefore, even if the wire is bonded and peels off on the main bonding pad, the bonding wire can be repaired by using the preliminary bonding pad, improving the manufacturing yield and The reliability can be improved, and a great effect can be obtained especially in the case of a high-definition ultra-small electronic component in which the line width of the wiring portion is small and peeling easily occurs on the bonding pad.
【図１】この考案の一実施例の要部の平面図である。FIG. 1 is a plan view of an essential part of an embodiment of the present invention.
【図２】実施例のボンディングパッドの平面図である。FIG. 2 is a plan view of a bonding pad of an example.
【図３】従来例の要部の平面図である。FIG. 3 is a plan view of a main part of a conventional example.
【図４】従来例における剥離部分の側面図である。FIG. 4 is a side view of a peeled portion in a conventional example.
【図５】ボンディングパッドの寸法例を示す平面図であ
る。FIG. 5 is a plan view showing a dimension example of a bonding pad.
１ 駆動用ＩＣ ２ 電極端子 ３ ガラス基板 ４ 配線部 ５ 主ボンディングパッド ６ 予備ボンディングパッド ７ くびれ部 ８ ボンディングワイヤ 1 Driving IC 2 Electrode Terminal 3 Glass Substrate 4 Wiring Section 5 Main Bonding Pad 6 Preliminary Bonding Pad 7 Constriction 8 Bonding Wire
Claims (1)
ディングパッドとこれに対応する電極端子との間をワイ
ヤボンディングによって電気的に接続する構造の電子部
品において、配線部の主ボンディングパッドの基部に予
備ボンディングパッドが直列に形成されていることを特
徴とする電子部品の端子構造。1. A base part of a main bonding pad of a wiring part in an electronic component having a structure in which a bonding pad formed on a wiring part made of a conductive film and an electrode terminal corresponding to the bonding pad are electrically connected by wire bonding. A terminal structure for an electronic component, characterized in that preliminary bonding pads are formed in series on the terminal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP088666U JPH0650340U (en) | 1992-11-30 | 1992-11-30 | Terminal structure of electronic parts |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP088666U JPH0650340U (en) | 1992-11-30 | 1992-11-30 | Terminal structure of electronic parts |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0650340U true JPH0650340U (en) | 1994-07-08 |
Family
ID=13949151
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP088666U Pending JPH0650340U (en) | 1992-11-30 | 1992-11-30 | Terminal structure of electronic parts |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0650340U (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003060122A (en) * | 2001-08-21 | 2003-02-28 | Texas Instr Japan Ltd | Substrate for mounting semiconductor chip and semiconductor device using the same |
| JP2012030342A (en) * | 2010-08-03 | 2012-02-16 | Nippon Telegr & Teleph Corp <Ntt> | Package for mems element |
| JP2012094866A (en) * | 2010-10-22 | 2012-05-17 | Paragon Semiconductor Lighting Technology Co Ltd | Multi-chip package having direct electric connection with alternating current power supply |
-
1992
- 1992-11-30 JP JP088666U patent/JPH0650340U/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003060122A (en) * | 2001-08-21 | 2003-02-28 | Texas Instr Japan Ltd | Substrate for mounting semiconductor chip and semiconductor device using the same |
| JP4586316B2 (en) * | 2001-08-21 | 2010-11-24 | 日本テキサス・インスツルメンツ株式会社 | Semiconductor chip mounting substrate and semiconductor device using the same |
| JP2012030342A (en) * | 2010-08-03 | 2012-02-16 | Nippon Telegr & Teleph Corp <Ntt> | Package for mems element |
| JP2012094866A (en) * | 2010-10-22 | 2012-05-17 | Paragon Semiconductor Lighting Technology Co Ltd | Multi-chip package having direct electric connection with alternating current power supply |
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