JPH06502265A - 信号処理におけるマトリクス演算の計算回路装置 - Google Patents

信号処理におけるマトリクス演算の計算回路装置

Info

Publication number
JPH06502265A
JPH06502265A JP3517639A JP51763991A JPH06502265A JP H06502265 A JPH06502265 A JP H06502265A JP 3517639 A JP3517639 A JP 3517639A JP 51763991 A JP51763991 A JP 51763991A JP H06502265 A JPH06502265 A JP H06502265A
Authority
JP
Japan
Prior art keywords
matrix
multiplier
adder
memory
circuit device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3517639A
Other languages
English (en)
Japanese (ja)
Inventor
バイヒター，　イェルク
ラーマッハー，　ウルリヒ
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
Original Assignee
Siemens AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG filed Critical Siemens AG
Publication of JPH06502265A publication Critical patent/JPH06502265A/ja
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/10—Complex mathematical operations
    • G06F17/16—Matrix or vector computation, e.g. matrix-matrix or matrix-vector multiplication, matrix factorization

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Pure & Applied Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Computational Mathematics (AREA)
  • Data Mining & Analysis (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • Algebra (AREA)
  • Databases & Information Systems (AREA)
  • Software Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Complex Calculations (AREA)
JP3517639A 1990-11-15 1991-11-04 信号処理におけるマトリクス演算の計算回路装置 Pending JPH06502265A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE4036455.0 1990-11-15
DE4036455A DE4036455C1 (enExample) 1990-11-15 1990-11-15
PCT/DE1991/000858 WO1992009040A1 (de) 1990-11-15 1991-11-04 Schaltungsanordnung zur berechnung von matrixoperationen in der signalverarbeitung

Publications (1)

Publication Number Publication Date
JPH06502265A true JPH06502265A (ja) 1994-03-10

Family

ID=6418338

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3517639A Pending JPH06502265A (ja) 1990-11-15 1991-11-04 信号処理におけるマトリクス演算の計算回路装置

Country Status (5)

Country Link
US (1) US5422836A (enExample)
EP (1) EP0557314A1 (enExample)
JP (1) JPH06502265A (enExample)
DE (1) DE4036455C1 (enExample)
WO (1) WO1992009040A1 (enExample)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2021522630A (ja) * 2018-04-21 2021-08-30 マイクロソフト テクノロジー ライセンシング，エルエルシー マルチポート・メモリーを備えたベクトル・レジスター・ファイルを有する行列ベクトル乗算器
JP2024036383A (ja) * 2019-03-15 2024-03-15 インテル コーポレイション 行列アクセラレータアーキテクチャのためのスパース最適化

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5311459A (en) * 1992-09-17 1994-05-10 Eastman Kodak Company Selectively configurable integrated circuit device for performing multiple digital signal processing functions
FR2757973B1 (fr) * 1996-12-27 1999-04-09 Sgs Thomson Microelectronics Processeur de traitement matriciel
KR100451147B1 (ko) * 1997-02-25 2004-11-26 엘지전자 주식회사 고속곱셈기
KR100457040B1 (ko) * 2000-06-21 2004-11-10 패러데이 테크놀로지 코퍼레이션 곱셈 누산 명령을 이용한 데이터 처리 장치 및 방법
US7216140B1 (en) * 2000-09-30 2007-05-08 Intel Corporation Efficient implementation of n-point DCT, n-point IDCT, SA-DCT and SA-IDCT algorithms
JP3940714B2 (ja) * 2003-09-25 2007-07-04 株式会社東芝 演算装置、および、暗号・復号演算装置
NZ532757A (en) * 2004-05-04 2005-07-29 Canterprise Method and apparatus for identifying a maximum subarray
FR2880446A1 (fr) * 2005-01-04 2006-07-07 France Telecom Indexation par transposition de matrice de grande dimension
US10304008B2 (en) * 2015-03-20 2019-05-28 Nec Corporation Fast distributed nonnegative matrix factorization and completion for big data analytics
CN111090467B (zh) * 2016-04-26 2025-05-27 中科寒武纪科技股份有限公司 一种用于执行矩阵乘运算的装置和方法
WO2018113597A1 (zh) 2016-12-20 2018-06-28 上海寒武纪信息科技有限公司 矩阵乘加运算装置、神经网络运算装置和方法
US10982633B2 (en) * 2017-07-03 2021-04-20 Continental Automotive Systems, Inc. Fuel pump solenoid assembly method
CN109992743B (zh) 2017-12-29 2020-06-16 华为技术有限公司 矩阵乘法器

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB226899A (en) * 1923-10-09 1925-01-08 Robert Sohner Improvements in motor ploughs
JPS5932216A (ja) * 1982-08-17 1984-02-21 Sony Corp ディジタル信号処理回路及びディジタルフィルタ
DE3735654C2 (de) * 1986-10-21 1996-05-02 Sharp Kk Elektronischer Rechner
US4815019A (en) * 1987-02-26 1989-03-21 Texas Instruments Incorporated Fast ALU equals zero circuit
US4949292A (en) * 1987-05-14 1990-08-14 Fujitsu Limited Vector processor for processing recurrent equations at a high speed
US4958312A (en) * 1987-11-09 1990-09-18 Lsi Logic Corporation Digital multiplier circuit and a digital multiplier-accumulator circuit which preloads and accumulates subresults
GB2226899A (en) * 1989-01-06 1990-07-11 Philips Electronic Associated An electronic circuit and signal processing arrangements using it
US5179531A (en) * 1990-04-27 1993-01-12 Pioneer Electronic Corporation Accelerated digital signal processor
EP0466997A1 (en) * 1990-07-18 1992-01-22 International Business Machines Corporation Improved digital signal processor architecture

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2021522630A (ja) * 2018-04-21 2021-08-30 マイクロソフト テクノロジー ライセンシング，エルエルシー マルチポート・メモリーを備えたベクトル・レジスター・ファイルを有する行列ベクトル乗算器
JP2024036383A (ja) * 2019-03-15 2024-03-15 インテル コーポレイション 行列アクセラレータアーキテクチャのためのスパース最適化

Also Published As

Publication number Publication date
WO1992009040A1 (de) 1992-05-29
DE4036455C1 (enExample) 1992-04-02
US5422836A (en) 1995-06-06
EP0557314A1 (de) 1993-09-01

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