JPH0649110Y2 - Zero volt signal generation circuit - Google Patents

Zero volt signal generation circuit

Info

Publication number
JPH0649110Y2
JPH0649110Y2 JP1986155030U JP15503086U JPH0649110Y2 JP H0649110 Y2 JPH0649110 Y2 JP H0649110Y2 JP 1986155030 U JP1986155030 U JP 1986155030U JP 15503086 U JP15503086 U JP 15503086U JP H0649110 Y2 JPH0649110 Y2 JP H0649110Y2
Authority
JP
Japan
Prior art keywords
circuit
signal
outputs
output
operational amplifiers
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP1986155030U
Other languages
Japanese (ja)
Other versions
JPS6363090U (en
Inventor
昇三 浅野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Tottori Sanyo Electric Co Ltd
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tottori Sanyo Electric Co Ltd, Sanyo Electric Co Ltd filed Critical Tottori Sanyo Electric Co Ltd
Priority to JP1986155030U priority Critical patent/JPH0649110Y2/en
Publication of JPS6363090U publication Critical patent/JPS6363090U/ja
Application granted granted Critical
Publication of JPH0649110Y2 publication Critical patent/JPH0649110Y2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Description

【考案の詳細な説明】 (イ)産業上の利用分野 本考案はゼロボルト信号発生回路に関する。DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to a zero volt signal generating circuit.

(ロ)従来の技術 従来より交流負荷を制御する方法として、SCR或いはト
ライアック等のスイッチング素子を使用し、位相制御回
路によりON・OFF制御している。この際交流信号の半サ
イクル内でスイッチング制御が行なわれると、スイッチ
ング素子のON・OFF時に高周波ノイズが発生しラジオ等
へノイズ妨害を与える為、一般に交流信号のゼロ点でス
イッチング制御するゼロボルト制御が採用されている
(例えば特開昭52−147756号公報〔58H172〕参照)。
(B) Conventional technology Conventionally, as a method for controlling an AC load, a switching element such as an SCR or a triac is used and ON / OFF control is performed by a phase control circuit. At this time, if switching control is performed within a half cycle of the AC signal, high-frequency noise is generated when the switching element is turned on and off, which causes noise interference to the radio, etc.Therefore, in general, zero volt control for switching control at the zero point of the AC signal is used. It has been adopted (see, for example, JP-A-52-147756 [58H172]).

(ハ)考案が解決しようとする問題点 しかしながら、従来行なわれているゼロボルト信号発生
回路より発生されるゼロボルト信号は、第3図に示すよ
うに交流信号のゼロ点を中心とした所定幅のパルス信号
であり、ゼロ点より少しずれた位置でスイッチング制御
される為、完全にノイズ発生を防止できないという問題
が有った。
(C) Problems to be solved by the invention However, as shown in FIG. 3, the zero volt signal generated by the conventional zero volt signal generating circuit is a pulse having a predetermined width centered on the zero point of the AC signal. Since it is a signal and switching control is performed at a position slightly deviated from the zero point, there is a problem that noise generation cannot be completely prevented.

(ニ)問題点を解決するための手段 本考案は交流信号をクランプして方形波信号を作るクラ
ンプ手段と、クランプされた信号を増幅する増幅器と、
増幅器の出力を微分する微分回路と、微分出力をグラン
ドレベルと比較する比較器と、比較器出力の論理和を取
る論理和回路で構成したものである。
(D) Means for solving the problem The present invention is a clamp means for clamping an alternating current signal to produce a square wave signal, and an amplifier for amplifying the clamped signal,
It is configured by a differentiating circuit that differentiates the output of the amplifier, a comparator that compares the differential output with the ground level, and a logical sum circuit that takes the logical sum of the comparator outputs.

(ホ)作用 本考案は上述の如く構成したことにより、交流信号のゼ
ロ点で立つ上るゼロボルト信号を発生でき、スイッチン
グ素子のスイッチング時点を交流信号のゼロ点に完全に
一致させることができ、ノイズの発生を確実に防止する
ことができる。
(E) Operation The present invention, which is configured as described above, can generate a rising zero volt signal at the zero point of an alternating current signal, can perfectly match the switching time of the switching element with the zero point of the alternating current signal, and It is possible to reliably prevent the occurrence of.

(ヘ)実施例 以下本考案の実施例を図面に基づき説明する。(F) Embodiment An embodiment of the present invention will be described below with reference to the drawings.

(1)は交流電源が接続された電源トランスで二次側よ
り所定電圧の交流信号を出力している。(2)は電源ト
ランス(1)の二次側に接続された抵抗(3)(4)と
ダイオード(5)(6)よりなるクランプ回路で、交流
信号をクランプし方形波信号を出力する。(7)(8)
はそれぞれ正入力端子及び負入力端子に方形波信号が入
力され、他方の負入力端子及び正入力端子が接地され、
増幅器として作用する第1、第2オペアンプで、第2オ
ペアンプ(8)からは第1オペアンプ(7)の出力の反
転した増幅信号が出力される。(9)(10)はオペアン
プ(7)(8)の出力を微分する微分回路で、微分出力
が比較器として作用する第3、第4オペアンプ(11)
(12)に供給されグランドレベルと比較される。(13)
(14)(15)は論理和回路(16)を形成するダイオード
と抵抗である。尚前述の4個のオペアンプ(7)(8)
(11)(12)は、集積化され1つのICで構成され、±5V
の電源で駆動されている。
(1) is a power supply transformer to which an AC power supply is connected, and outputs an AC signal of a predetermined voltage from the secondary side. (2) is a clamp circuit composed of resistors (3) and (4) and diodes (5) and (6) connected to the secondary side of the power transformer (1) and clamps an AC signal to output a square wave signal. (7) (8)
Square wave signal is input to the positive input terminal and the negative input terminal, respectively, and the other negative input terminal and the positive input terminal are grounded,
The first and second operational amplifiers functioning as amplifiers, and the amplified signal obtained by inverting the output of the first operational amplifier (7) is output from the second operational amplifier (8). (9) and (10) are differentiating circuits that differentiate the outputs of the operational amplifiers (7) and (8), and the third and fourth operational amplifiers (11) whose differential outputs act as comparators.
It is supplied to (12) and compared with the ground level. (13)
(14) and (15) are a diode and a resistor that form an OR circuit (16). The above-mentioned four operational amplifiers (7) (8)
(11) and (12) are integrated and composed of one IC, ± 5V
It is powered by.

次に斯る構成よりなる本考案の動作につき第2図の波形
図に基づき説明する。
Next, the operation of the present invention having such a configuration will be described with reference to the waveform chart of FIG.

先ず第2図(a)に示すような交流信号が供給される
と、クランプ回路(2)のダイオード(5)(6)の順
方向電圧に基づき第2図(b)に示すように約0.7Vの電
圧にクランプされ、方形波信号に変換され第1、第2オ
ペアンプ(7)(8)に供給される。そしてオペアンプ
(7)(8)により入力された方形波信号の増幅が行な
われるが、オペアンプ(7)(8)の電源電圧が±5Vで
あり且つ無限増幅器として作用するよう構成されている
為、オペアンプ(7)(8)からは第2図(c)(f)
に示す増幅信号出力が得られる。尚オペアンプ(8)か
らは入力の方形波信号が反転された増幅信号が出力され
ている。続いてオペアンプ(7)(8)の出力信号は、
各々微分回路(9)(10)で微分されるが、微分回路
(9)(10)は−5V電源にプルダウンされている為、−
5Vを中心とした第2図(d)(g)に示すような微分波
形出力が得られる。この微分波形出力は比較器として作
用する第3、第4オペアンプ(11)(12)に供給され、
グランドレベルと比較されることにより、微分波形のグ
ラドレベル以上の部分が出力され、第2図(e)(h)
に示すようなパルス信号としてオペアンプ(11)(12)
より出力される。このオペアンプ(11)(12)の出力は
論理和回路(16)に供給されるが、抵抗(15)によりグ
ランドレベルにプルダウンされている為、第2図(i)
に示すようにダイオード(13)(14)の順方向電圧分低
い出力パルスが発生される。この出力パルスは入力され
た交流信号のゼロ点で立上るゼロボルトパルス信号であ
り、このパルス信号を図示しないスイッチング素子に供
給することにより、交流負荷をゼロ点で確実にON・OFF
制御することが出来る。
First, when an AC signal as shown in FIG. 2 (a) is supplied, about 0.7 as shown in FIG. 2 (b) based on the forward voltage of the diodes (5) and (6) of the clamp circuit (2). It is clamped to the voltage of V, converted into a square wave signal, and supplied to the first and second operational amplifiers (7) and (8). Then, the square wave signal inputted by the operational amplifiers (7) and (8) is amplified. However, since the power supply voltage of the operational amplifiers (7) and (8) is ± 5 V, and the amplifier operates as an infinite amplifier, From the operational amplifiers (7) and (8), see FIG. 2 (c) and (f).
The amplified signal output shown in is obtained. The operational amplifier (8) outputs an amplified signal obtained by inverting the input square wave signal. Then, the output signals of the operational amplifiers (7) and (8) are
Each is differentiated by the differentiating circuit (9) (10), but since the differentiating circuit (9) (10) is pulled down to the -5V power supply,
A differential waveform output as shown in FIGS. 2 (d) and (g) centered on 5 V is obtained. This differential waveform output is supplied to the third and fourth operational amplifiers (11) and (12) which function as comparators,
By comparing with the ground level, the portion of the differential waveform above the grad level is output, and FIG. 2 (e) (h)
Opamp as pulse signal as shown in (11) (12)
Will be output. The outputs of the operational amplifiers (11) and (12) are supplied to the logical sum circuit (16), but are pulled down to the ground level by the resistor (15).
As shown in, an output pulse lower than the forward voltage of the diodes (13) and (14) is generated. This output pulse is a zero volt pulse signal that rises at the zero point of the input AC signal.By supplying this pulse signal to a switching element (not shown), the AC load can be reliably turned on and off at the zero point.
It can be controlled.

(ト)考案の効果 上述の如く本考案のゼロボルト信号発生回路は、クラン
プ回路、オペアンプ、微分回路等の簡単な回路構成によ
り、交流信号のゼロ点で立上るゼロボルト信号を発生す
ることができるものであり、交流負荷のON・OFF制御時
にスイッチング素子に供給される交流信号が完全にゼロ
となった時点でスイッチング制御されるので、スイッチ
ングに伴なうノイズ発生を完全に防止することができ
る。
(G) Effect of the Invention As described above, the zero volt signal generating circuit of the present invention can generate a zero volt signal rising at the zero point of an AC signal by a simple circuit configuration such as a clamp circuit, an operational amplifier and a differentiating circuit. Since the switching control is performed when the AC signal supplied to the switching element becomes completely zero during the ON / OFF control of the AC load, it is possible to completely prevent the generation of noise accompanying the switching.

【図面の簡単な説明】[Brief description of drawings]

第1図は本考案のゼロボルト信号発生回路の構成を示す
回路図、第2図は第1図要部の波形図、第3図は従来の
ゼロボルト信号を示す波形図である。 (2)…クランプ回路、(7)(8)(11)(12)…オ
ペアンプ、(9)(10)…微分回路、(16)…論理和回
路。
FIG. 1 is a circuit diagram showing a configuration of a zero volt signal generating circuit of the present invention, FIG. 2 is a waveform diagram of an essential part of FIG. 1, and FIG. 3 is a waveform diagram showing a conventional zero volt signal. (2) ... Clamp circuit, (7) (8) (11) (12) ... Operational amplifier, (9) (10) ... Differentiation circuit, (16) ... OR circuit.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 【請求項1】交流信号をクランプし方形波を出力するク
ランプ回路と、正入力に前記クランプ回路の出力が供給
され負入力が接地された第1オペアンプと、負入力に前
記クランプ回路の出力が供給され正入力が接地された第
2オペアンプと、前記第1、第2オペアンプの出力をそ
れぞれ微分する微分回路と、微分回路の出力をそれぞれ
グランドレベルと比較する第3、第4オペアンプと、該
第3、第4オペアンプの出力の論理和を出力する論理和
回路で構成したことを特徴とするゼロボルト信号発生回
路。
1. A clamp circuit which clamps an AC signal and outputs a square wave, a first operational amplifier whose positive input is supplied with the output of the clamp circuit and whose negative input is grounded, and a negative input which is connected to the output of the clamp circuit. A second operational amplifier which is supplied and whose positive input is grounded; a differential circuit which differentiates the outputs of the first and second operational amplifiers; and third and fourth operational amplifiers which compare the outputs of the differential circuit with the ground level, respectively. A zero-volt signal generation circuit comprising a logical sum circuit that outputs a logical sum of the outputs of the third and fourth operational amplifiers.
JP1986155030U 1986-10-09 1986-10-09 Zero volt signal generation circuit Expired - Lifetime JPH0649110Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1986155030U JPH0649110Y2 (en) 1986-10-09 1986-10-09 Zero volt signal generation circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1986155030U JPH0649110Y2 (en) 1986-10-09 1986-10-09 Zero volt signal generation circuit

Publications (2)

Publication Number Publication Date
JPS6363090U JPS6363090U (en) 1988-04-26
JPH0649110Y2 true JPH0649110Y2 (en) 1994-12-12

Family

ID=31075362

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1986155030U Expired - Lifetime JPH0649110Y2 (en) 1986-10-09 1986-10-09 Zero volt signal generation circuit

Country Status (1)

Country Link
JP (1) JPH0649110Y2 (en)

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6031186B2 (en) * 1975-07-21 1985-07-20 東芝機械株式会社 Synchronous signal generation circuit in thyristor gate circuit

Also Published As

Publication number Publication date
JPS6363090U (en) 1988-04-26

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