JPH0648754B2 - Wiring board manufacturing method - Google Patents

Description

The present invention relates to a method of manufacturing a wiring board suitable for use in electronic equipment such as a computer and a communication device, and particularly to a high density,
The present invention relates to a method for forming a fine pattern.

[Conventional technology]

Conventionally, there are various methods for forming wiring on this kind of wiring board, but photolithography technology is required to form a high-density and fine pattern. As a typical method for forming the conductor wiring, there is a selective plating method, which is described, for example, in Japanese Patent Publication No. 20-2059. This is an insulating substrate 1 as shown in FIG.
After forming the thin-film metal layer 2 on the surface of the photoresist (Fig. 2 (a)), the photoresist 4 is applied thereon and exposed and developed to remove the photoresist in a desired portion (Fig. 2 (b)). ), And the plating metal 5 is attached to the portion (FIG. 2 (c)). After that, the photoresist film 4 and the thin film metal layer 2 thereunder are removed to obtain a conductor pattern (second).
Figure (d), Figure 2 (e)).

[Problems to be solved by the invention]

However, according to the method described above, when the underlying thin film metal layer 2 is removed with an etching solution, an undercutting phenomenon occurs in which the underlying layer of the plating part is also removed. It was difficult to get the wiring. Also, as this etching liquid,
A strong acid such as hydrofluoric acid is used, but this attacks the glass-ceramic insulating layer and adversely affects the properties as an interlayer insulating layer.

As a method for solving this, as shown in FIG. 3, instead of removing the thin film metal layer 2 with an etching solution, the metal layer 2 is oxidized and sintered by the high temperature heating in an oxygen atmosphere and converted into the insulating layer 6. The method of storing is disclosed in JP-A-56-64.
It is described in Japanese Patent No. 494.

However, even when this method is used, when the heating temperature is insufficient with respect to the film thickness of the thin film metal layer 2, there is a problem that the thin film metal layer 2 is not sufficiently oxidized and insulation failure occurs.

The present invention is made in view of the above points, and an object thereof is to stably oxidize a plating base metal layer by using a method that does not use an etching solution in forming a conductor wiring by a selective plating method. By doing so, it is an object of the present invention to provide a method for removing the above-mentioned defects and forming a fine conductor wiring pattern.

[Means for solving problems]

In order to achieve such an object, the present invention provides a method for forming a plurality of conductor wirings on a heat resistant insulating substrate, in which a thin film metal layer is formed on the surface of the substrate, and the thin film metal layer is formed using a photoresist. After forming an arbitrary conductor pattern by plating on the top and removing the photoresist,
The exposed surface of the thin film metal layer is roughly etched by irradiating the surface of the substrate with an ion beam, and then the thin film metal layer that cannot be completely removed in the etching step is oxidized and sintered by high-temperature heating in an oxygen atmosphere. It is characterized in that the conductor patterns are electrically isolated and insulated from each other to form conductor wiring.

[Action]

In the present invention, the conductor pattern is formed by the selective plating method without using the etching liquid.

〔Example〕

1 (a) to 1 (h) are sectional views of steps showing an embodiment of a method for manufacturing a wiring board according to the present invention. In the figure, first, as shown in FIG. 1 (a), a titanium thin film layer 2 and a palladium thin film layer 3 are sequentially laminated on a heat resistant insulating substrate 1 such as ceramics by a sputtering method or a vacuum evaporation method. At this time, the thickness of the titanium thin film layer 2 is
The thickness of the palladium thin film layer 3 is 500 to 2000 angstroms, and the film thickness of the palladium thin film layer 3 is 3000 to 10,000 angstroms.
A chromium thin film layer may be formed instead of the titanium thin film layer 2. Further, the thicker the thickness of the palladium thin film layer 3 is, the smaller the deviation in the thickness of the conductor pattern in the subsequent plating step is. Therefore, about 10,000 angstroms is preferable. Next, as shown in FIG. 1 (b), a photoresist layer 4 is spin-coated on the whole surface of the palladium thin film layer 3 and prebaked, and the photoresist layer 4 is formed using a glass mask (not shown). Selectively expose.
Then, the patterning by the photoresist layer 4 is completed by developing with a developing solution. As an example of the photoresist layer 4, OFPR series manufactured by Tokyo Ohka is used. The thickness of this photoresist layer 4 is about 6 micrometers. Next, as shown in FIG. 1 (c), a gold plating layer 5 is applied to the opening of the photoresist layer 4. In this case, the palladium thin film layer 3 is used as an electrode layer with electrolytic gold plating. The thickness of this gold plating layer 5 is about 5
It is a micrometer. Next, as shown in FIG. 1 (d), the photoresist layer 4 is peeled off using a peeling solution such as methyl ethyl ketone to expose the palladium thin film layer 3 other than the gold plated portion. Next, as shown in FIG. 1 (e), ion beam etching is performed from the surface of the palladium thin film layer 3 to roughly etch the palladium thin film layer 3. At this time, if the palladium thin film layer 3 and the titanium thin film layer 2 can be completely etched by the ion beam etching, the individual patterns of the gold plating layer 5 are insulated from each other and become independent patterns, but the palladium thin film layer 3 is thick. In this case, or when the surface of the insulating substrate 1 is not sufficiently smooth, the titanium thin film layer 2 and the palladium thin film layer 3 are not completely etched as shown in FIG. With this film, the individual patterns due to the gold plating layer 5 are short of each other. Next, as shown in FIG. 1 (f), when the insulating substrate 1 is heated in an oxygen atmosphere,
The titanium thin film layer 2 and the palladium thin film layer 3 are oxidized and sintered to become the insulating film 6. As a result, the individual conductor patterns 5'formed by the gold plating layer 5 are electrically isolated and insulated from each other. At this time, the conductor pattern 5'of the gold plating layer 5 is alloyed by mutual diffusion with the titanium thin film layer 2 and the palladium thin film layer 3 in the step of high temperature heat treatment, and the gold alloy thin film layer 7 is shown in the figure. It may not be as clear as it was. In addition, the condition of high temperature heating is about 850 ℃
A time of 10 minutes or more at the above temperature is preferable. In this way, the conductor pattern 5'can be formed without using the etching solution while using the selective plating method. Therefore, the pattern width capable of forming the conductor pattern 5'depends on the characteristics of the resist, but in the case of OFPR, the thickness can be about 15 μm when the thickness is about 6 μm. Next, as shown in FIG. 1 (g), an insulating layer 8 and a via hole 9 are further formed on the wiring pattern 5'formed in this way by using a glass-ceramic paste, and then, as shown in FIG. ), A titanium thin film layer 10 and a palladium thin film layer 11 are further formed on the insulating layer 8, and the first thin film layer 11 and the palladium thin film layer 11 are formed from FIG.
The second conductor wiring layer is formed by the gold plating pattern 12 by the same method as that shown in FIG. Thus, by using a material having excellent heat resistance such as glass-ceramic as the interlayer insulating material, it is possible to form a multilayer wiring board having an arbitrary number of layers.

〔The invention's effect〕

As described above, according to the method for manufacturing a wiring board according to the present invention, it is possible to form a high density and fine wiring pattern by forming the conductor pattern by using the selective plating method without using the etching liquid. . Furthermore, since the conductor pattern can be formed without using an etching liquid that corrodes the glass-ceramic, it has an extremely excellent effect that a high-quality conductor pattern without deterioration of characteristics can be obtained.

[Brief description of drawings]

FIG. 1 is a vertical sectional view of a step showing a method for manufacturing a wiring board according to an embodiment of the present invention, and FIGS. 2 (a) to 2 (e) are vertical sectional views showing an example of a conventional technique. FIGS. 3A to 3E are longitudinal sectional views showing an example of another prior art. 1 ... Ceramic substrate, 2, 10 ... Titanium thin film layer,
3, 11 ... Palladium thin film layer, 4 ... Photoresist layer, 5 ... Gold plated layer, 5 '... Conductor pattern, 6 ...
Oxide insulation film, 7 ... Gold alloy thin film layer, 8 ... Interlayer insulation layer,
9 ... Via hole, 12 ... Second wiring layer conductor pattern.

Claims (1)

[Claims] 1. A step of forming at least one thin-film metal layer on the surface of a heat-resistant insulating substrate, and a step of forming an arbitrary conductor pattern on the thin-film metal layer by plating with a photoresist. And a step of removing the photoresist, a step of irradiating the heat-resistant insulating substrate with an ion beam to roughly etch an exposed portion of the thin film metal layer, and an oxidation baking of the thin film metal layer by high temperature heating in an oxygen atmosphere. And a step of electrically separating and insulating between the conductor patterns of the gold plating layer that cannot be completely removed in the etching step.