JPH0648036U - Synchronous clock communication network - Google Patents

Abstract

(57) [Abstract] [Purpose] The present invention enables transmission / reception with two communication lines even if a communication line for transmitting a synchronous clock is included. The purpose is to eliminate the need to attach a start mark and to transfer the same data as the start mark. A synchronous clock communication network according to the present invention includes a CPU 1 for generating a synchronous clock, a CPU 2 for receiving the synchronous clock generated by the CPU 1, a communication line 3 for propagating the synchronous clock, and communication data between the CPU 1 and the CPU 2. It is composed of the propagating communication line 4, and the synchronization clock waveform generated from the CPU1 is fixed to "H" for 3 clocks or more to make it the start mark of the transmission data from the CPU1 to the CPU2, and also to "L" for 3 clocks. From the above fixing I, the transmission data from the CPU 2 to the CPU 1 is used as a start mark, and the transmission and reception between the CPU 1 and the CPU 2 can be performed with only two communication lines.

Description

[Detailed description of the device]

[0001]

[Industrial applications]

 The present invention relates to a synchronous clock communication network using a synchronous clock.

[0002]

[Prior art]

 Conventionally, in this kind of synchronous clock communication, in order to enable transmission and reception between CPUs, a communication line 7 for propagating a synchronous clock, a communication line 8 for transmitting from the CPU 1 to the CPU 2, and a communication line 8 for transmitting from the CPU 2 to the CPU 1 The communication line 9 is composed of a total of three communication lines. When transmitting data from the CPU1 to the CPU2, the CPU1 sends a synchronous clock to the CPU2 to the communication line 7, and outputs the transmitted data to the communication line 9 according to the synchronous clock. Similarly, when transmitting data from the CPU 2 to the CPU 1, a synchronous clock is transmitted from the CPU 2 to the CPU 1 to the communication line 7, and transmission data is transmitted to the communication line 8 in synchronization with the synchronous clock.

At this time, it is determined whether or not the data segmentation from the other party is a start mark each time the transmitted data is received, and if so, it is recognized as the start of the data. .

[0004]

[Issues to be solved by the device]

 However, in such a conventional method, three communication lines are required for transmission / reception between the CPU1 and the CPU2, and a start mark is required at the beginning of the transmission data. Furthermore, the same data as the start mark is confused, so there was a restriction that it could not be sent until then.

The present invention was made to solve the above problems, and even if a communication line for transmitting a synchronous clock is included, it is possible to perform transmission / reception with two communication lines. By incorporating the start mark in the synchronous clock, it is not necessary to attach a start mark to the transfer data, and the purpose is to transfer the same data as the start mark.

[0006]

[Means for Solving the Problems]

 In the synchronous clock communication network according to the present invention, by fixing the synchronous signal waveform generated from the CPU1 to "H" for 3 clocks or more, it is used as the start mark of the transmission data from the CPU1 to the CPU2, and also "L". It is a means for solving the problem by fixing the clock for 3 clocks or more to the start mark of the transmission data from the CPU 2 to the CPU 1.

[0007]

【Example】

 An embodiment of the invention will be described below with reference to the drawings. FIG. 1 is a block diagram of the present invention, in which a synchronous clock is propagated from a CPU 1 to a CPU 2 on a communication line 1. Further, on the communication line 2, communication data is propagated from the CPU 1 to the CPU 2 or vice versa in synchronization with the synchronization clock.

As an example of transmission / reception, FIG. 2 shows a waveform when 12H is transmitted from the CPU 1 to the CPU 2 and 34H is transmitted from the CPU 2 to the CPU 1. In period 3, the clock waveform is the "L" period continuation part, and shows the start mark when transmission from CPU1 to CPU2 is started. In period 4, the clock waveform is the "H" period continuation part. , A start mark at the time of starting transmission from CPU2 to CPU1.

A period 5 is a period in which data is transmitted from the CPU 1 to the CPU 2, and the CPU 1 changes the synchronization clock from “L” to “H” and outputs the data to be transferred each time the data is output onto the communication line 1. It outputs to the communication line 2 from the lower bit one by one. By repeating this 8 times, 8-bit data can be transmitted. On the other hand, the CPU 2 side fetches the data on the communication line 2 as the received data when it detects the falling of the clock. Next, during the period 6, the transmission from the CPU 2 to the CPU 1 is performed, and the CPU 2 outputs the transmission data onto the communication line 2 every time the received clock changes from "H" to "L". The CPU 1 side fetches the data on the communication line 2 as received data every time the synchronous clock is changed from "L" to "H".

[0010]

[Function of the device]

 Since the synchronous clock communication network configured in this way uses the period 3 in FIG. 2 as the start mark of the transmission data from the CPU 1 to the CPU 2, when the CPU 1 attempts to transmit the data, the synchronous clock for only 3 clocks is used. It is only necessary to output "L" to the communication line 1, and thereafter, as shown in period 5, the transfer data is output from the lower bit to the communication line 2 at each rising transition of the synchronous clock on the communication line 1. Since it is sufficient, it is not necessary to put a start mark in the transmission data from the CPU 1 to the CPU 2 in the transfer data.

In the conventional case, the start mark is fixed to 02H in many cases, but if this 02H is output as transmission data on the communication line 2, it will be confused with the start mark. It was necessary to convert the data to another data or to add extra control data and send it, but by detecting the start mark with the synchronous clock in this way, the start mark is detected and the transferred data is analyzed. Since it is not necessary to detect it, the hexadecimal data from 00H to FFH can be transmitted without any restrictions.

Further, fixing the synchronous clock to “L” indicates that the transmission from the CPU1 to the CPU2 is started, and fixing it to “H” declares that the transmission from the CPU2 to the CPU1 is started. Therefore, it is possible to determine whether the current synchronization clock is synchronized with the transmission from the CPU1 to the CPU2 or the transmission from the CPU2 to the CPU1 inside the CPU1 and the CPU2. It is possible to perform the transmission from the CPU1 to the CPU2 and the transmission from the CPU2 to the CPU1 alone.

[0013]

[Effect of device]

 In this way, by fixing the output data of the synchronous clock on the communication line 1 to "H" or "L", the start mark at the start of transmission from the CPU1 to the CPU2 or the start mark at the start of transmission from the CPU2 to the CPU1 By using the start mark of, any hexadecimal data from 00H to FFH can be output on the communication line 2. Furthermore, since the synchronous clock is directional, a total of two communication lines, that is, the communication line 1 for propagating the synchronous clock and the communication line 2 for propagating data can be transmitted and received between the CPU1 and the CPU2. , Its practical effect is truly great.

[Brief description of drawings]

FIG. 1 is a connection diagram of a synchronous clock communication network of the present invention.

FIG. 2 is an example of communication when the configuration shown in FIG. 1 is used.

FIG. 3 is a connection diagram of a conventional synchronous clock communication network.

[Explanation of symbols]

1 Communication line for propagating synchronous clock 2 Communication line for propagating data 3 Synchronous clock waveform for start mark (when transmitting CPU1) 4 Synchronous clock waveform for start mark (when transmitting CPU2) 5 Waveform of transmission / reception period (transmission of CPU1) 6 Transmission / reception rule Waveform between (during CPU2 transmission) 7 Synchronous clock propagation communication line 8 Data propagation communication line 9 Data propagation communication line

Claims (1)

[Scope of utility model registration request] 1. A CPU1 for generating a synchronous clock, a CPU2 for receiving the synchronous clock generated by the CPU1, a communication line 3 for propagating the synchronous clock, and a CPU.
1 and the communication line 4 that propagates communication data between the CPU 2 and the synchronization clock waveform generated from the CPU 1
By fixing it to H "for 3 clocks or more, it is used as the start mark of the transmission data from CPU1 to CPU2, and similarly, fixing it to" L "for 3 clocks or more
A synchronous clock communication network characterized in that it is used as a start mark of data transmitted from the CPU 1 to the CPU 1 and transmission / reception between the CPU 1 and the CPU 2 is possible with only two communication lines.