JPH064661A - Image processor - Google Patents

Abstract

PURPOSE:To process image at a high speed with respect to image data of one line. CONSTITUTION:Plural image sensors 401 read an original while dividing it so as to mak reading areas partially overlap and divides image data of one line into plural blocks. A dividing means 402 using a memory, e.g. furthermore divides the respective blocks into plural blocks so that the respective blocks have image data in the neighborhood of the border of adjacent two blocks overlapping. Then, an image processing means 403 image-processes color ghost correction, the connection correction of a marker, and digital filter processing, etc., independently of and parallelly with the respective blocks.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus for processing image data for one line at high speed.

[0002]

2. Description of the Related Art In an image input / output system such as a digital copying machine or a facsimile machine, as an input means thereof, for example, a surface of an original is optically scanned to be scanned pixel by pixel, sampled and photoelectrically converted line by line to be read. A photoelectric conversion element such as a coupling element (hereinafter referred to as CCD) is used. An image processing apparatus that performs image processing such as correction processing on the image data obtained by this photoelectric conversion element is well known.

In such an image processing apparatus, for example, CC
When a wide original of about A0 size is read with high resolution using D as a line sensor, a long CCD line sensor with high pixel density must be used. However, in practice, it is difficult to manufacture such an element capable of reading one long line of image data due to manufacturing problems in the semiconductor integrated technology.

Therefore, conventionally, for example, JP-A-57-26 has been used.
As shown in Japanese Patent Application Laid-Open No. 963 and Japanese Patent Application Laid-Open No. 58-131860, a plurality of elements are arranged in a line to form one image.
The scanning line area is divided into a plurality of areas and read, and then the divided image data is converted into one line of image data.

[0005]

However, the read data for one line of a document of about A0 size naturally has a large amount of data, and the processing speed in the line unit processing becomes slow and real-time processing is required. There is a problem that image processing may become difficult.

On the other hand, image processing may be performed for each image data of a plurality of elements. In this case, an image such as digital filter processing using image data of peripheral pixels in addition to the image data of the pixel of interest. In the processing, there is a problem that the image processing cannot be performed on the pixels near the boundary of the element.

Therefore, an object of the present invention is to provide an image processing apparatus capable of performing image processing on one line of image data at high speed.

Another object of the present invention is to perform image processing on a target pixel by using image data of a plurality of pixels around the target pixel, when the image data for one line is not processed, An object of the present invention is to provide an image processing device capable of performing image processing at high speed without causing any problems.

[0009]

An image processing apparatus according to a first aspect of the present invention, as shown in the conceptual diagram of FIG. 1, is obtained by reading an original by an image sensor 401, for example.
Dividing means 402 for dividing the image data of lines into a plurality of blocks so that each block has image data near the boundary between two adjacent blocks, and each block divided by the dividing means 402. And an image processing unit 403 that performs image processing independently and in parallel.

In this image processing apparatus, the image data for one line is divided into a plurality of blocks by the dividing means 402. At that time, each block overlaps the image data near the boundary between two adjacent blocks. Divided to have. Then, the image processing means 403 performs image processing on each block independently and in parallel.

According to a second aspect of the present invention, there is provided the image processing apparatus according to the first aspect, wherein the dividing means divides the image information of one line area of the original into predetermined areas and reads them. It includes a plurality of image sensors that read image information in the vicinity of the boundary of (1) and output it as image data for each block.

In this image processing apparatus, the image data for one line is divided into a plurality of blocks by a plurality of image sensors that read image information of a region of one line of the document in a partially overlapping manner.

According to a third aspect of the present invention, in the image processing apparatus according to the first aspect, the dividing means captures image data of a predetermined area of the input image data, and image data near the boundary of each area. Is duplicated, and a plurality of data input / output means for outputting as image data for each block are included.

In this image processing apparatus, the image data for one line is divided into a plurality of blocks by a plurality of data input / output means for capturing a part of the input image data and outputting it.

According to a fourth aspect of the present invention, in the image processing apparatus according to the third aspect, the data input / output means outputs image data of a predetermined area of the input image data and image data near an area boundary. It includes a memory for storing and outputting the stored data.

According to a fifth aspect of the present invention, in the image processing apparatus according to the first, second or third aspect, the image processing means performs image processing using the image data of a plurality of pixels around the target pixel. It is something to do.

According to a sixth aspect of the present invention, in the image processing apparatus according to the fifth aspect, the image processing means corrects the color information of the target pixel on the basis of the image data of a plurality of peripheral pixels. Is included.

An image processing apparatus according to a seventh aspect of the present invention is the image processing apparatus according to the fifth aspect, wherein, when the image processing means identifies a portion where pixels having a specific feature are connected, a plurality of adjacent pixels are arranged. It includes a connection correction means for performing correction for compensating for a portion where the pixel connection is interrupted, based on the image data. A pixel having a specific feature is, for example, a pixel having hue data that matches a marker color designated by the user.

An image processing apparatus according to an eighth aspect of the present invention is the image processing apparatus according to the fifth aspect, wherein the image processing means includes a filter processing means for performing an operation using image data of a plurality of pixels around the target pixel. It is a waste.

[0020]

Embodiments of the present invention will be described below with reference to the drawings. 2 to 41 relate to one embodiment of the present invention, and this embodiment is an example in which the present invention is applied to a digital copying machine.

The digital copying machine according to the present embodiment reads an original with a full-color image sensor, performs various image processing,
The image scanner unit is equipped with a page memory for storing image data that has undergone image editing, and a printing unit for printing the image data stored by the image scanner unit in two colors. The image scanner unit is provided with a control panel for the user to specify the number of copies and various image processing / editing functions, etc. The desired copy can be obtained by this control panel specification. There is.

FIG. 2 is a block diagram showing the structure of the image scanner unit. The image scanner unit 220 is a CCD
Has an image sensor 308 which is mounted on the CCD drive circuit 200. In the subsequent stage of the CCD drive circuit 200,
An analog circuit 201, a video (1) circuit 202, a video (2) circuit 203, a color circuit 204, a digital filter circuit (hereinafter referred to as a DF circuit) 206, and a halftone processing circuit (hereinafter referred to as an HTP circuit) 207. Is provided. Further, an area recognition circuit (hereinafter referred to as an AR circuit) 205 is connected to the color circuit 204, and an HTP is provided.
An edit circuit (hereinafter referred to as an EDIT circuit) 208 is connected to the circuit 207. Also, the video (1) circuit 202 to the HTP circuit 207, the AR circuit 205, and the E circuit
The DIT circuit 208 and a central processing unit (hereinafter referred to as CPU) that controls them (1) circuit 209 are connected to each other by a VME bus 16 which is one of the system bus standards. The circuits 202 to 209 are the image processing unit 214.

A data processing circuit 210 is connected to the latter stage of the HTP circuit 207. This data processing circuit 210
Includes a CPU (2) circuit 211 and a page memory circuit 2
12 are connected. In addition, the CPU (2) circuit 211
A control panel 213 is connected to the. The data processing circuit 210 outputs the image data 215 to the printing section and inputs the control signal 238 from the printing section. In addition, the CPU (2) circuit 211
Is the CPU (1) circuit 209 via the control data line 120.
And the control unit of the printing unit via the control data line 237.

FIG. 3 is a block diagram showing the arrangement of the printing unit. The print unit 221 is the image scanner unit 22.
Data separation unit 23 for inputting image data 215 from 0
1 and the first provided in the latter stage of the data separation unit 231.
The color image data memory 232 and the second color image data memory 234, the first color laser driving section 233 provided in the latter stage of the first color image data memory 232, and the latter stage of the second color image data memory 234 are provided. A second color laser drive unit 235 and a control unit 236 that controls each of the above units are provided. The control unit 236 is connected to the CPU (2) circuit 211 of the image scanner unit 220 via the control data line 237 and sends a control signal 238 to the data processing circuit 210 of the image scanner unit 220. .

FIG. 4 is an explanatory view showing a part of the cross section of the image scanner section. The image scanner unit includes a plurality of document feed rollers 302 provided on the upper side of the document feeding path,
303, and a plurality of rollers 304 and 305 provided below the document feeding path and nipping the document 310 together with the document feed rollers 302 and 303. A platen glass (not shown) is provided on the lower side of the document transport path, and a platen roller 311 is provided on the platen glass. Further, a light source 306 below the platen glass, an image sensor 308 mounted on the CCD drive circuit 200, and a converging rod lens for forming an image of an original 310 illuminated by the light source 306 on the image sensor 308. An array 309 is provided. In addition, a sensor 301 that detects the document 310 is provided in the document insertion portion. In addition, the platen roller 311
Has a plurality of flat surfaces around the platen roller 311
A reference plate 312 is provided which is rotatable around the central axis of. As shown in FIG. 5, the reference plate 312 has a black surface 313 serving as a black level reference and a white surface 314 serving as a white level reference. The black surface 313 and the white surface 314 are connected to the platen glass. And the platen roller 311 can be selectively interposed.

FIG. 6 is a plan view of the image sensor 308. The image sensor 308 used in this embodiment is a full-color contact type sensor, and as shown in FIG. 6, five line type sensor chips (1) to (1) arranged in a zigzag pattern.
(5) 321 to 325 are included. Sensor chips (1), (3), (5) and sensor chips (2), (4)
And are spatially displaced by Δx. Therefore, the image data read by the image sensor 308 is stored in two chip groups (sensor chips (1), (3), (5) and sensor chips (2), (4)) at different portions on the document. The data will be read at the same time. A process of converting this data into data obtained by reading the same line of the original is performed in the video (1) circuit 202 described later.

FIG. 7 is an explanatory diagram showing a pixel array of one chip of the image sensor 308. Image sensor 30
A pixel 8 is formed by arranging pixels of each color of blue (hereinafter referred to as B), green (hereinafter referred to as G), and red (hereinafter referred to as R) in this order.

In the present embodiment, the image sensor 30 for A3 size is used to read a document as wide as A0 size.
The three image sensors 308a, 308b, 308c are arranged in a zigzag pattern, and the three image sensors 308a, 308b, 308c are attached so as to read the same line of the original. 8 is a plan view of the image sensors 308a, 308b, 308c, FIG. 9 is a perspective view thereof, FIG. 10 is a side view seen from the longitudinal direction thereof, and FIG.
FIG. 3 is an explanatory diagram showing a pixel arrangement at end portions of the image sensors 308a and 308b. As shown in these figures, in this embodiment, three image sensors 308a, 308b, and 3 are provided.
Reference numeral 08c indicates that the image information of one line area of the original is read by dividing it into predetermined areas, and the image information near the boundary of each area is read by overlapping by several pixels.
The ends of the two image sensors are arranged so as to overlap by several pixels in the main scanning direction. The number of pixels read in duplicate is
Although it is determined by the later-described processing, that is, ghost cancellation, marker connection correction, and digital filter processing, which will be described later, in the present embodiment, there are 14 pixels as shown in FIG.

FIG. 12 shows three image sensors 308a,
It is explanatory drawing which shows the block divided by 308b and 308c. As shown in FIG. 12A, the original 404
Image information of the three image sensors 308a, 308
b, 308c are divided and read, and the hatched portions in the drawing are read redundantly, and as shown in FIG. 12B, three blocks 405a, 405b, 405 are read.
It is output as image data divided into c. These three blocks have image data in the vicinity of the boundary between adjacent blocks indicated by hatched lines in the figure in an overlapping manner. Then, the output image data of the three image sensors are processed independently and in parallel for each of the three blocks thereafter.

Next, the configuration and operation of each circuit of the image scanner section 220 will be described.

FIG. 13 is a block diagram of the CPU (1) circuit 209. The CPU (1) circuit 209 is the CPU 11
1, timer 112, read only memory (hereinafter R
It is written as OM. ) 113, a random access memory (hereinafter referred to as RAM) 114, a VME bus interface (hereinafter referred to as VME bus I / F) 115, an output control unit 116, an input control unit 117, and a serial communication unit 118. And they are connected to each other by a bus. The VMEbus I / F 115 is connected to the VMEbus 16 and the serial communication unit 118 is connected to the control data line 120. This CPU (1) circuit 209 is
By executing the program stored in the ROM 113 by using M114 as a work area, the image processing unit 2
Control of each circuit in 14 and communication with the CPU (2) circuit 211 are performed.

In FIG. 2, when the user specifies the desired number of copies and various image processing / editing from the control panel 213, the CPU on the CPU (2) circuit 211 passes on the CPU (1) circuit 209 via the control data line 120. The CPU 111 sends various image processing / editing information selected on the control panel 213. Also,
The CPU on the CPU (2) circuit 211 sends information such as the paper size selected by the control panel 213 to the control unit 236 of the printing unit 221 through the control data line 237.

In FIG. 13, various image processing / editing information sent through the control data line 120 is taken into the CPU (1) circuit 209 via the serial communication unit 118 and decoded by the CPU 111. CPU11
Reference numeral 1 denotes various parameters (control data) corresponding to the image processing / editing information through the VME bus I / F 115 and the VME bus 16 and each circuit 202 to 20 in the image processing unit 214.
8 registers and RAM.

Next, in FIG. 4, when the document 310 is inserted into the image scanner section 220, the sensor 301 is turned on, which is detected by the CPU 111 through the input control section 117 of the CPU (1) circuit 209 in FIG. A motor for document feeding is driven, and the document 310 is conveyed by the document feed rollers 302 and 303. When the conveyed document 310 reaches the platen roller 311, the light source 30
The light 307 emitted by the light source 6 and reflected by the original 310 is incident on the image sensor 308, and as shown in FIG.
The original image is read by the image sensor 308 driven by the drive circuit 200, and the CCD video signal 9 is sequentially processed by the analog circuit 201.

FIG. 14 is a block diagram of the analog circuit 201. The analog circuit 201 is the CCD drive circuit 2
A sample and hold unit 1 for extracting an effective image signal from the CCD video signal 9 from 00, and a gain control unit 2 provided in sequence after the sample and hold unit 1.
Dark correction unit 3, offset control unit 4, and analog-digital conversion (hereinafter referred to as A / D conversion).
Digital / analog conversion (hereinafter referred to as D / A conversion) data from the unit 5 and the video (1) circuit 202 is D / A.
It is provided with a D / A conversion unit 6 which performs A conversion and sets the gain control unit 2 and the offset control unit 4.

Prior to reading the original, when the power of the image scanner unit 220 is turned on, the black surface 313 of the reference plate 312 shown in FIG. 5 is exposed on the platen glass and read, and the read value at this time becomes a predetermined value. As described above, the offset value of the offset control unit 4 is set to the CPU 11
1 to the D / A converter 6 is automatically set (hereinafter, this is referred to as automatic offset control: AOC). Next, on the platen glass, the reference plate 3 shown in FIG.
The white surface 314 of 12 is read and read, and the gain value of the gain control unit 2 is changed from the CPU 111 to the D / A conversion unit 6 so that the read value at this time becomes a predetermined value.
Is automatically set (hereinafter, this is referred to as automatic gain control: AGC). Since such adjustment is performed in advance, the actual document reading data becomes video data having a sufficient dynamic range without being saturated, and is digitized by the A / D conversion unit 5 to obtain the image data 8. The video data is sequentially sent to the video (1) circuit 202. The dark correction unit 3 is a unit that removes an output change due to a dark current of the image sensor 308 by using an output signal of a shield bit (light-shielded pixel) of the image sensor 308.

FIG. 15 is a block diagram of the video (1) circuit 202. The video (1) circuit 202 includes a CCD gap correction unit 11 that inputs the image data 8 from the analog circuit 201, an RGB separation unit 12 and a dark shading correction unit 13 that are sequentially provided at the subsequent stage of the CCD gap correction unit 11. A control unit 14 that controls each of the units 11 to 13 and a clock generation unit 15 that supplies a clock to each of the units 11 to 13 are provided. The control unit 14 is connected to the VME bus 16, sends the D / A conversion data 7 to the analog circuit 201 via the VME bus 16, and outputs the control signal 19 to the video (2) circuit 203 in the subsequent stage. It is supposed to do. The clock generator 15 sends a drive clock 20 to the analog circuit 201, and the drive clock 20 is sent to the CCD drive circuit 200 via the analog circuit 201.

As described above, the image sensor 308 used in this embodiment is composed of the five chips 321 to 325 arranged in a staggered pattern as shown in FIG. 6, and the two chip groups are displaced by Δx. Therefore, the CCD gap correction unit 11 performs a process of converting the data read by the two chips into the data read on the same line of the original. In the CCD gap correction unit 11, specifically, the data read by the chips (2) and (4) 322 and 324 is delayed by using a memory and is converted into read data of the same line. The output pixel data string of the CCD gap correction unit 11 is a series of B, G, and R data, as shown in FIG. 16, which is shown in FIG.
As shown in (c) to (c), the RGB separation unit 12 performs the process of converting the pixel data sequence into R, G, and B. The pixel data separated into R, G, and B in this way is sequentially sent to the dark shading correction unit 13, and dark shading correction is performed. The dark shading correction is performed after the AOC and AGC operations are performed when the power of the image scanner unit 220 is turned on before the reading of the original, and then the black surface 313.
Is a process of storing the read image data in the memory for each pixel, and subtracting the black surface read data stored for each pixel from the image data of each pixel when the document is actually read. The image data 18 thus sequentially processed by the video (1) circuit 202 is sent to the video (2) circuit 203.

FIG. 18 is a block diagram of the video (2) circuit 203. The video (2) circuit 203 uses the video (1)
The bright shading correction unit 21 that inputs the image data 18 from the circuit 202, and the bright shading correction unit 21.
RGB misalignment correction unit 22, sensor misalignment correction unit 24, and data block division unit 2 which are sequentially provided in the subsequent stage.
5, a control unit 26 for controlling each of the units 21 to 25, and a clock generation unit 27 for supplying a clock to each of the units 21 to 25. The control unit 26 is connected to the VME bus 16, inputs the control signal 19 from the video (1) circuit 202, and sends the control signal 30 to the color circuit 204. Further, the clock generator 27 sends the control clock 28 to each circuit in the subsequent stage.

The image data 18 sent to the video (2) circuit 203 is first subjected to bright shading correction by the bright shading correction section 21. Similar to the dark shading correction, the bright shading correction stores the image data obtained by reading the white surface 314 in the memory for each pixel after the AOC and AGC operations, and the image data of each pixel when the original is actually read. Is a process for normalizing (dividing) with the white surface read data for each pixel stored.
The image data that has been subjected to the light shading correction and the dark shading correction becomes image data that is not affected by the light amount distribution of the light source 306 or the sensitivity variation of each pixel. Further, the offset value and gain value of AOC and AGC can be set by the CPU 111, and the memories of the light shading correction unit 21 and the dark shading correction unit 13 can be read and written by the CPU 111 via the VME bus 16. , AGC and control of bright and dark shading correction by CPU11
One can do it.

Further, since the image sensor 308 used in this embodiment has B, G, and R pixels arranged side by side as shown in FIG. 7, the actual document reading between B, G, and R is performed. The position is incorrect. This causes an erroneous judgment when the color is judged by the color circuit 204 in the next stage.
It is necessary to perform correction so that the R, G, and B reading positions become the same virtual point. The RGB misregistration correction unit 22 performs this correction. The RGB misregistration correction is based on the G2 position in FIG.
The data and the virtual R data are obtained by calculating image data of B2 and B3 and calculating image data of R1 and R2, respectively.

The explanation of the operation up to this point is made in the image sensor 3.
However, as described above, three image sensors 308 are actually used to read a wide original. These three image sensors 308 are adjusted and attached so that the same line of the original can be read, but in reality, a deviation occurs. The sensor position shift correction unit 24 corrects this shift. The sensor position deviation correction is almost the same as the CCD gap correction, and the image data of each sensor is delayed by an arbitrary time by using a memory, so that the image data of the three sensors is main-scanned on the original at the joint. The images are adjacent to each other in the same direction.

In the case of a high-speed wide-width digital copying machine, it is necessary to process image data at a high speed.
There is a limit to high-speed operation of digital integrated circuits and the like. Therefore, the output image data of the sensor displacement correction unit 24 is
The data block dividing unit 25 divides the block into a plurality of blocks in the main scanning direction. Here, for example, the output image data of one image sensor 308 is divided into two blocks, the read data of the original 310 is divided into a total of six blocks as shown in FIG. Will be processed. The image data 29 thus divided into blocks is sequentially sent to the color circuit 204.

Here, the data block dividing section 25 will be described in detail. FIG. 20 shows the data block division unit 25.
3 is a block diagram showing a configuration example of FIG. The data block division unit 25 includes a memory (1) 251 and a memory (2) 252 which respectively input input image data, and a control circuit 253 which controls writing and reading of the two memories 251 and 252. . It should be noted that the data block dividing unit 25 is configured by the three image sensors 308.
Three are provided corresponding to.

FIG. 21 shows the data block division unit 2 of FIG.
6 is a timing chart showing the operation of FIG. Figure 21
One block of input image data 255 from one image sensor 308 as shown in FIG.
1, 252 are supplied. Here, as shown in FIG. 21B, a write control signal WE1 is applied from the control circuit 253 to the memory (1) 251 so as to write the first half data of one block of input image data. On the other hand, the control circuit 2 controls the memory (2) 252 so as to write the latter half of the input image data of one block.
A write control signal WE2 is given from 53. Figure 21
As shown in (b) and (c), the two write control signals WE1 and WE2 overlap at the boundary between the first half and the second half of the input image data of one block. Therefore, the image data at the boundary between the first half and the second half of the input image data is stored in the memory 25.
That is, the data is written in the first and the second lines 252 in a duplicated manner. In this embodiment, the amount of data written in the memories 251 and 252 in an overlapping manner is 14 pixels. The 14 pixels are the same as the number of pixels that are redundantly output by overlapping the image sensors 308 in the reading unit.

The two memories 251 and 252 receive the read control signal RE from the control circuit 253 shown in FIG.
21. At the same time, the data is read in a cycle slower than the cycle of the input image data, and output data (1) 256 and output data (2) 257 are output as shown in FIGS.
Is divided into two and output.

FIG. 22 is an explanatory diagram showing input image data and output data of the data block dividing section 25. FIG. 22
Assuming that the number of pixels of one block input in time series is 4800 pixels as shown in (a), as shown in FIG.
Data up to the 07th pixel is written in the memory (1) 251 and read as output data (1) 256. On the other hand, as shown in FIG. 22C, data from the 2394th pixel to the 4800th pixel is written in the memory (2) 252 and is read as output data (2) 257.

As described above, in the data block dividing unit 25, each of the three blocks divided by the three image sensors 308 is further divided into two blocks, so that one line of data is divided into six blocks. become. Then, the subsequent processing is performed independently and in parallel for each of the six blocks.

FIG. 23 is a block diagram of the color circuit 204. The color circuit 204 includes a hue determination unit 41 that inputs the image data 29 from the video (2) circuit 203, and a ghost cancellation unit 42, a buffer memory 43, and a color editing unit 44 that are sequentially provided at the subsequent stage of the hue determination unit 41. And a density correction unit 45, and a control unit 46 for controlling the above units 41 to 45. The control unit 46 is connected to the VME bus 16 and inputs the control signal 30 from the video (2) circuit 203 and the control signal 49 from the AR circuit 205 to the DF circuit 206 and the AR circuit 205. Control signals 50 and 51 are sent respectively.

The image data 29 input to the color circuit 204 are R, G, and B color image signals. The hue determining section 41 determines the color of the image on the original and encodes the encoded color code signal and density. Data and are generated. The ghost canceling section 42 in the next stage corrects the color code signal generated by the hue determining section 41. This is because, as a result of the RGB misregistration correction of the video (2) circuit 203, for example, an erroneous hue determination may be made at the edge portion of the black image on the document, and a color code other than the achromatic color may be generated. This is a process for converting a color code into an achromatic color code (hereinafter referred to as color ghost correction). This erroneous color code is called a ghost, and the change pattern of the color code when the ghost occurs is known in advance. Therefore, when the pattern matches, the color code is corrected to an achromatic color.

Here, the ghost canceling section 42 will be described in detail. FIG. 25 shows the ghost cancellation unit 42.
3 is a block diagram showing a configuration example of FIG. The ghost canceling section 42 corrects a ghost in the main scanning direction. The ghost canceling section 42 includes a hue determining section 41.
For example, a shift register 421 for inputting a 4-bit color code 428 from, and outputting after delaying by a predetermined pixel, and 8-bit density data from the hue determining unit 41 are input to indicate whether or not the pixel of interest is background density. A background detection unit 422 that outputs a 1-bit background flag, and a color code 428.
OR gate 423 that takes the logical sum of the 4 bits of the OR gate 423, a shift register 424 that holds the outputs of the OR circuit 423 and the background detection unit 422 for 5 pixels, and a color code change pattern when a ghost occurs (hereinafter , A ghost pattern generation circuit 425 for generating a ghost pattern), and data for five pixels held in the shift register 424 and the ghost pattern generation circuit 425.
The ghost pattern generated by the shift register 4 and the comparator 426 for detecting whether the two match.
And a ghost correction unit 427 that receives the output of the comparator 27 and corrects it according to the output of the comparator 426.

Next, the operation of the ghost cancel unit 42 will be described with reference to FIG. FIG. 26A shows five pixels in which the shift register 424 holds data, and FIG. 26B shows a ghost pattern generated by the ghost pattern generation circuit 425. In the figure, “color” indicates a chromatic color. The color code 428 is ORed by the OR circuit 423 and input to the shift register 424. Further, the density data 429 is input to the background detection unit 422. The background detection unit 422 sets the background flag to “0” when the density data is larger than a predetermined value, and sets the background flag to “1” when the density data is less than the predetermined value. This background flag is input to the shift register 424. The shift register 424 holds the output data of the OR circuit 423 and the background flag for a total of 5 pixels including the determination pixel 431 and two pixels before and after the determination pixel 431 as shown in FIG. The OR circuit 4
The output data of 23 and the background flag identify whether each pixel is black, white or chromatic. On the other hand, the ghost pattern generation circuit 425 generates the six ghost patterns ~ shown in FIG. Then, the comparator 426 compares the pattern of the data of 5 pixels held in the shift register 424 with the 6 ghost patterns to detect the coincidence between them. The ghost correction unit 427 inputs the color code of the determination pixel 431 from the shift register 421, and detects a match between the data pattern of 5 pixels held in the shift register 424 by the comparator 426 and any of the six ghost patterns ~. If yes, all the color codes are set to "0" and the corrected color code 430 is output. In other cases, the input color code is output as the corrected color code 430 as it is.
By performing such processing for all pixels, generation of color ghost is prevented.

The above-described color ghost correction is performed independently and in parallel for every six blocks in order to perform the processing at high speed in real time. In this color ghost correction, in addition to the data of the determination pixel 431, the surrounding data is also used.
In this embodiment, since each block has data in the vicinity of the boundary between adjacent blocks in an overlapping manner, color ghost correction is possible even at the boundary between blocks.

The density data and the color code signal thus generated are sequentially stored in the buffer memory 4 shown in FIG.
It is stored in 3. On the other hand, the color code signal 47 is A
It is sent to the R circuit 205. In this embodiment, various edits can be performed in real time on a region surrounded by a marker written on a document using a marker pen, and the region surrounded by the marker is detected. The AR circuit 205 does this.

After the AR circuit 205 has been described, the rest of the color circuit 204 will be described.

FIG. 24 is a block diagram of the AR circuit 205. The AR circuit 205 receives the color code signal 47 from the color circuit 204 as a marker flag generator 61.
And a parallel-serial conversion (hereinafter, referred to as PS conversion) unit 62, a region recognition unit 63, and a serial-parallel conversion (hereinafter, referred to as SP conversion) unit which are sequentially provided in the subsequent stage of the marker flag generation unit 61. 64 and a control unit 65 that controls the above-mentioned units 61 to 64. The control unit 65 is connected to the VME bus 16, inputs the control signal 51 from the color circuit 204, and sends the control signal 49 to the color circuit 204.

The color code signal 47 sequentially sent from the color circuit 204 is a signal for each block. First, the marker flag generation unit 61 determines from the color code whether or not it is a marker image, and when it is a marker image, generates a marker flag.

Here, the marker flag generator 61 will be described. The marker flag generation unit 61 detects markers,
Three processes are performed: correction of connection of marker breaks and generation of marker flags. The marker detection detects pixels having hue data matching the marker color specified by the user from the hue data (color code) of the read image and generates a region color flag. It is realized by a comparator that compares the color code of the marker color.

Next, the connection correction of marker break will be described in detail. It is difficult to write a marker on a manuscript without causing unevenness in color or blurring, and a break in several pixels may occur. If there is a break in the marker, the area may be erroneously determined. In order to prevent the erroneous determination of this area, the marker discontinuity correction is performed and the marker flag for each pixel is determined.

In order to correct the marker break and determine the marker flag of the pixel of interest, the area flags of a plurality of surrounding pixels are used. The connection correction of the marker discontinuity is a process of thickening a pixel having a region color flag (hereinafter, referred to as an OR process) and a process of increasing the position accuracy by deleting the end of the pixel having the thickened region color flag ( Below, AN
This is called D processing. )I do. Here, an example of correcting a break of a marker of 14 pixels or less is shown.

FIG. 27 is a block diagram showing an example of the arrangement of a connection correction unit which performs connection correction for marker breaks. As shown in this figure, the connection correction unit sequentially inputs the area color flag 505 and holds the 15-pixel area of the 15-bit shift register 50.
1 and 1 held by this shift register 501
OR circuit 5 which takes the logical sum of the area color flags 505 of 5 pixels
02 and the output data of the OR circuit 502 are sequentially input and hold 15 pixels.
And 15 held by this shift register 503.
An AND circuit 504 that obtains a logical product of pixel data is provided.

Next, the operation of the connection correction unit will be described with reference to FIGS. 28 and 29. As shown in FIG. 28,
First, the 15-bit shift register 501 sequentially inputs the area color flags 505, and holds the area color flags of a total of 15 pixels including the pixel of interest 510 and 7 pixels before and after it. Next, the OR circuit 502 calculates the logical sum of the area color flags of the 15 pixels. This means that if there is even one pixel of the designated marker color among the 15 pixels, the target pixel 510 is regarded as a marker color pixel and the marker flag is set to "1". When the above OR processing is performed on an input image in which there are no marker color pixels between the marker color pixels 511 and 512 as shown in FIG. The color pixels will be thickened by 7 pixels on both sides of the pixels 511 and 512,
The marker flag will be supplemented to the discontinuous part. Note that reference numeral 513 in the drawing indicates a pixel regarded as a marker color pixel by the OR processing.

Next, as shown in FIG. 28, the marker flags after the above OR processing are sequentially input to the 15-bit shift register 503, and the marker flag of the target pixel 510 and 7 pixels before and after the target pixel 510 are added in total to a total of 15 pixel marker flags. Hold. Then, the AND circuit 504 calculates the logical product of the marker flags of 15 pixels. This means that the marker flag of the pixel of interest 510 is set to "1" when the marker flags of all 15 pixels are "1", and the marker flag is set to "0" otherwise. As a result of this AND processing, as shown in FIG. 29C, 7 pixels on both sides of the marker color pixel thickened by the OR processing are discarded, and between the two marker color pixels 511 and 512 which are discontinued. Only pixels are considered as marker color pixels. This allows
The positional accuracy of marker detection can be maintained. Note that reference numeral 514 in the drawing indicates a pixel that is finally regarded as a pixel of the marker color by the AND process.

As described above, by the above-mentioned OR processing and AND processing, it is possible to correct the discontinuity of the marker of 14 pixels or less while maintaining the position accuracy of the marker detection.

The above-mentioned concatenation correction is performed independently and in parallel for every six blocks in order to perform the processing at high speed in real time. In this concatenation correction, in addition to the data of the pixel of interest 510, the data around it is also used. However, in this embodiment, since each block has data in the vicinity of the boundary between adjacent blocks in duplicate, at the boundary of the block. Can also be connected correction.

Next, the PS converter 62 of FIG. 24 converts the marker flag subjected to block processing into a signal of one line. The area recognizing unit 63 recognizes the area surrounded by the markers from the thus obtained 1-line marker flag, and the area signal indicating the inside of the area is generated here. The generated area signal is again divided into each block by the SP conversion unit 64, and is sequentially output as the area signal 48 to the color editing unit 44 of the color circuit 204. The reason why the buffer memory 43 is provided in the color circuit 204 is that it takes time for the AR circuit 204 to recognize the area. Therefore, during this period, the color code signal and the density data are stored and the area signal 48 from the AR circuit 204 is stored. To match the timing.

Now, let us return to the description of the color circuit 204 in FIG. The block-divided area signal 48 output from the AR circuit 205 is input to the color editing unit 44, and the control signal 49 is input to the control unit 46. The control unit 46 reads the density data and the color code signal of the corresponding pixel in synchronization with the area signal 48 from the buffer memory 43 and sends them to the color editing unit 44. The copying machine of the present embodiment is a two-color copying machine, and it is possible to specify which color on the original is to be printed by which color of the two colors by the sub color flag. Further, the drop color flag can be used to specify which color image on the document should be erased. With this function, for example, a marker is not necessary and is implicitly deleted. These functions can be performed only within or outside the area designated by the marker. In addition, it is possible to specify whether or not the background removal to be performed in the next stage is performed on the inside and outside of the area by the BKG enable flag. The color editing unit 44 generates these flags.

The flag, the density data and the color code signal thus generated are sequentially sent to the density correcting section 45. The density correction unit 45 whitens (erases) the density data of pixels for which the drop color flag is set,
This is for enabling independent density adjustment for each color on the original (for each color code). The output 52 of the sub color flag, the BKG enable flag, the area signal, the density data, etc. processed in this way is sequentially DF
It is sent to the circuit 206.

FIG. 30 is a block diagram of the DF circuit 206. The DF circuit 206 outputs the output 5 from the color circuit 204.
The background removing unit 71 for inputting 2 is provided, a digital filter 72 and a sub color flag correcting unit 73 which are provided in sequence after the background removing unit 71, and a control unit 74 for controlling each of the units 71 to 73. . Control unit 74 is VME
It is connected to the bus 16 and receives the control signal 50 from the color circuit 204 and sends the control signal 76 to the HTP circuit 207.

In the DF circuit 206, the background removing section 71 is sequentially
Then, the background portion of the document at the portion where the BKG enable flag is set is whitened, and the BKG flag indicating the background portion is generated. Next, the digital filter 72 performs edge enhancement and smoothing processing according to the selected image mode. In addition, the sub color flag correction unit 73
When the background density of the image edge portion is raised by the smoothing process, the sub color flag of the raised background pixel is corrected to be the same as the sub color flag of the image portion. This is to prevent the occurrence of black contours around. The output 75 of the sub color flag, the density data, the area flag, the BKG flag, etc. processed in this way is sequentially sent to the HTP circuit 207.

Here, the digital filter 72 will be described in detail. FIG. 31 is a block diagram showing a configuration example of the digital filter 72 when it is a 7 × 7 two-dimensional digital filter. The digital filter 72 shown in this figure has six memories 702 to 7 for sequentially inputting the density data 701 from the background removing unit 71 and holding six lines.
07, the density data 701 from the background removing unit 71, and the seven latches 711 to 717 holding the density data from each of the memories 702 to 707 for seven pixels, respectively.
Adder 7 for adding the density data held in Nos. 1 and 717
21, an adder 722 for adding the density data held in the latches 712, 716, an adder 723 for adding the density data held in the latches 713, 715, output data of each of the adders 721 to 723, and a latch Four latches 731 to 73 for respectively holding output data of 714
4 and. The digital filter 72 further includes
Four filters 741 to 744 for performing a predetermined filter operation on the data held in each latch 731 to 734
And four latches 751 to 754 for holding output data of the filters 741 to 744, and latches 751 and 752.
Adder 761 for adding the data held in the latch and adder 7 for adding the data held in the latches 753, 754
62 and an adder 763 that adds the output data of both adders 761 and 762.

Next, the operation of the digital filter 72 will be described with reference to FIGS. 32 and 33. The density data 701 from the background removing unit 71 is stored in the memories 702 to 707.
Is converted into 7 lines of data. The 7 lines of data are held in the latches 711 to 717 for 7 pixels. Since the 7 × 7 digital filter 72 in this embodiment is of a target type, the adders 721 to 723 add 1 line + 7 lines, 2 lines + 6 lines, 3 lines + 5 lines as shown in FIG. It The added data and the data on the fourth line from the latch 714 are arithmetically processed by the filters 741 to 744, respectively. Note that in FIG. 32, reference numeral 780 indicates the direction of the order of calculation.

FIG. 33A shows a filter coefficient matrix in this embodiment, and A to J respectively show the filter coefficients. In the filters 741 to 744, FIG.
The 7 × 7 pixel data of the original image shown in FIG. 16 and each filter coefficient shown in FIG. 33A are multiplied and added and output. The output data from the four filters 741 to 744 are added to the adders 761 to 761 in order to obtain a 7 × 7 calculation result.
The calculation result data 770 is output after addition by 763. Thus, as shown in FIG. 33, the frequency characteristic of the original image can be changed by performing convolution with the matrix of the density of the original image and the filter having a specific coefficient.

Also in the above digital filter 72, in order to perform the processing at high speed in real time, the processing is carried out independently and in parallel for every six blocks. In the processing by this digital filter, in addition to the data of the pixel to be processed, the data of the surrounding pixels are also used.
In the present embodiment, since each block has data in the vicinity of the boundary between adjacent blocks in an overlapping manner, it is possible to perform the filtering process even at the boundary between the blocks.

FIG. 34 is a block diagram of the HTP circuit 207. The HTP circuit 207 outputs the output 75 of the DF circuit 206.
A block-line parallel conversion unit 81 for inputting, a reduction / enlargement unit 82 provided at a subsequent stage of the block-line parallel conversion unit 81, a density adjustment unit 88 for inputting image data 94 from the EDIT circuit 208, Halftone processing units 85 and 4 provided in order after the density adjusting unit 88.
A binarized data conversion unit 84, a diagnostic memory 87 for storing output data of the quaternary data conversion unit 84, a control unit 85 for controlling each unit, and a clock generation unit 86 for supplying a clock to each unit. I have it. The control unit 85 is a VME
The control signal 76 from the DF circuit 206 and the control signal 9 from the EDIT circuit 208 are connected to the bus 16.
6 is input, and the EDIT circuit 208 and the data processing circuit 21 are input.
Control signals 95 and 98 are transmitted to 0, respectively.

In the copying machine of the present embodiment, reduction / enlargement in the sub-scanning direction is performed by changing the document conveying speed as in the analog copying machine, but reduction / enlargement in the main-scanning direction is performed by digital image processing. In that case, this processing becomes very complicated in the parallel processing for each block. Therefore, the block-line parallel conversion unit 81 of the HTP circuit 207 converts the image data string for each block into an image data string that can be processed in parallel for each line. This is shown in FIG. 35 (a), for example.
The image data string for each of the six blocks shown in (f) to (f) is converted into a four-line parallel image data string shown in (a) to (d) of FIG. Next, the converted image data, the BKG flag, and the sub color flag are sent to the reduction / enlargement unit 82, while the area flag (area signal) 91.
Is sent to the EDIT circuit 208. In addition, the reduction / enlargement unit 82
The image data 93 output from is also sent to the EDIT circuit 208.

Here, after the description of the EDIT circuit 208, the rest of the HTP circuit 207 will be described.

FIG. 37 is a block diagram of the EDIT circuit 208. The EDIT circuit 208 includes a rectangular area recognition unit 101 that receives an area flag (area signal) 91 from the HTP circuit 207, a mirror editing unit 102 that inputs image data 93 from the HTP circuit 207, and the mirror editing unit 10.
A negative / positive editing unit 103, a density adjusting unit 104, and an ambience editing unit 105, which are sequentially provided in the second stage of the second stage, and a control unit 106 that controls the above-described units. Control unit 106
Is connected to the VME bus 16 and receives the control signal 95 from the HTP circuit 207,
A control signal 96 is sent to

In the copying machine of this embodiment, in addition to the method of designating a region by enclosing it with a marker, as shown in FIG.
By recognizing the rectangular area in the shaded area in the figure and making various edits, as shown in FIG. 39, the distances x _A , y _A , x _B from the upper left corner of the two points A and B on the original 310 are determined. By designating y _B from the control panel 213, the shaded area in the drawing can be recognized as a rectangular area, and various types of editing can be performed. The rectangular area recognition unit 101 performs recognition of these rectangular areas and generation of area flags (area signals) corresponding to each pixel in the rectangular areas. The area flag (area signal) 92 sequentially processed by the rectangular area recognition unit 101 is sent to the reduction / enlargement unit 82 of the HTP circuit 207, and the reduction / enlargement unit 82 reduces the BKG flag, the sub color flag, and the density data together. Enlargement processing is performed. Next, the image data 93 subjected to the sequential reduction / enlargement processing is EDI
It is sent to the mirror editing unit 102 of the T circuit 208.

The EDIT circuit 208 edits the sequentially sent image data 93 in real time. The mirror editing unit 102 performs a mirror image editing process within the rectangular area 331 as shown in FIG. 40 (a) or on the entire surface to obtain a mirror image as shown in FIG. 40 (b). The negative-positive editing unit 103 in the next stage is for obtaining a negative-positive inverted image in which white and black are inverted. Next-stage density adjustment unit 1
Reference numeral 04 corresponds to the copy density adjustment function on the control panel 213, and several kinds of density conversion curves can be selected for each of the two output colors. The next-stage sham-editing section 105 performs an sham-on on the image with the sami pattern selected from the control panel 213. Further, the function of erasing (masking) the inside of the area and erasing (trimming) the outside of the area is also performed by the sham-editing unit 105. Needless to say, the negative / positive editing and the dummy editing can also be performed on the area surrounded by the marker or the entire surface. The image data 94 sequentially processed in this manner is sent to the HTP circuit 207.

Now, return to the description of the HTP circuit 207 in FIG. The image data 94 sent from the EDIT circuit 208 is input to the density adjusting unit 88. The function of the density adjusting unit 88 is the same as that of the density adjusting unit 104 of the EDIT circuit 208. Since the EDIT circuit 208 is an optional circuit, the density adjustment unit 88 of the HTP circuit 207 performs density adjustment when the EDIT circuit 208 is not installed, and nothing is performed here when the EDIT circuit 208 is installed. does not process. The reason why the density adjustment is carried out by the EDIT circuit 208 when the EDIT circuit 208 is installed is that the density of the dummy pattern can be selected from the control panel 213, but the selected density is the control panel 21.
In order not to change with the copy density adjustment of 3,
This is because it is necessary to adjust the density before the artificial edit process.

Next, the halftone processing section 83 converts the multivalued image data into four-valued data having area gradation. This quaternarization means that the density of one pixel has four gradations of white, gray (1), gray (2), and black. The data processed in this way is converted by the four-valued data conversion unit 84 into data 97 that is a collection of image data for a plurality of pixels (four-valued density data and sub color flags), as shown in FIG. The data is sequentially output to the data processing circuit 210 outside the image processing unit 214. The diagnostic memory 87 stores the output data 97 of the quaternary data conversion unit 84 for self-diagnosis.

In FIG. 2, the data processing circuit 210 is
The image data sent from the HTP circuit 207 is sent to the page memory circuit 212.
It is stored in the page memory inside. When all the originals have been read in this way, the CPU 11 of the CPU (1) circuit 209
1 is the CPU (2) circuit 2 through the control data line 120
11 sends information to the CPU. Then, the CPU of the CPU (2) circuit 211 informs the control unit 236 of the printing unit 221 through the control data line 237 that the paper is conveyed and that the image data is stored in the page memory.

In FIG. 3, the control unit 236 of the printing unit 221 conveys a predetermined sheet of paper and a control signal 238.
Then, the image data 215 in the page memory is read from the data processing circuit 210 at a predetermined timing. The read image data 215 is sent to the data separation unit 231. The data separation unit 231 has a function of distributing the density data by the sub color flag. For example, when the sub color flag is “0”, the density data is sent to the first color image data memory 232 and the second color image data memory 23.
White data is sent to 4. When the sub color flag is "1", the density data is stored in the second color image data memory 2
34, and the white data is sent to the first color image data memory 232. The printing unit 221 prints by using the xerography technique, and the charge corotron, the developing device, and the like have two for the first color and the second color, and the two colors on the photoconductor (drum). The image is transferred onto paper at the same time and fixed. The semiconductor lasers for exposure are provided for each of the first color and the second color, and the driving control of these for each of the first color laser drive section 233 and the second color laser drive section 235 is performed based on the image data. Is.

As described above, according to this embodiment, 3
Each image sensor 308a, 308b, 308c divides the image data in the vicinity of the boundary between two adjacent blocks into three blocks so that each block has the same image data, and each of these three blocks is further divided into two adjacent blocks. The image data in the vicinity of the boundary of one block is divided into two blocks so that each block has a total of 6 blocks.
The image processing can be performed at high speed because the image processing is divided into one block and the image processing is performed in parallel for each of the six blocks. Moreover, since each block has image data in the vicinity of the boundary with an adjacent block in an overlapping manner, even in the vicinity of the boundary of each block, color ghost correction, marker connection correction, digital filter processing, etc. A process using image data of a plurality of pixels around it can be performed.

The present invention is not limited to the above embodiment,
For example, although the contact type CCD image sensor is used in the embodiment, a reduction type image sensor can also be realized. Further, four or more CCD image sensors may be arranged in parallel to perform the divided reading, and the overlapping amount of the sensors may be any number of pixels. Also, when the image data of one line or one block is divided into a plurality of blocks by signal processing, the overlapping amount between adjacent blocks may be any number of pixels.

The parallel processing is not limited to color ghost correction, marker connection correction, and digital filter processing, but so-called area processing for performing image processing on the pixel of interest with reference to the data of the surrounding pixels. It may be.

FIG. 41 is an explanatory view showing the outline of an optical system in the case where one line is divided into two blocks by using two reduction type image sensors. In the example shown in this figure, the original image of the first half W1 of the entire reading width W of the same main scanning line of the original image is formed on the reduction type CCD image sensor 802 by the imaging lens 801, and the second half W is formed.
Image of second document is reduced by a focusing lens 803
An image is formed on the image sensor 804, and the same main scanning line is divided and read by the two reduction type CCD image sensors 802 and 804. Also, the first half W
The area 805 for several pixels near the boundary between the first half and the second half W2 is 2
The two reduction type CCD image sensors 802 and 804 are arranged to read them in duplicate. Other configurations, operations and effects are the same as those of the embodiment shown in FIGS. 2 to 40.

[0089]

As described above, according to the first to fourth aspects of the present invention, each block has the image data of one line and the image data in the vicinity of the boundary between two adjacent blocks. Since it is divided into a plurality of blocks and the image processing is performed independently and in parallel for each block, there is an effect that the image processing can be performed at high speed on the image data of one line.

According to the fifth to eighth aspects of the invention, since each divided block has image data in the vicinity of the boundary with an adjacent block in an overlapping manner, a plurality of pixels around the target pixel can be obtained. When the image processing using the image data of the pixels is performed on the image data for one line, the image processing can be performed even in the vicinity of the boundary of each block,
There is an effect that the above-mentioned image processing can be performed at high speed without generating pixels that cannot be processed.

[Brief description of drawings]

FIG. 1 is an explanatory diagram showing a schematic configuration of the present invention.

FIG. 2 is a block diagram showing a configuration of an image scanner unit according to an embodiment of the present invention.

FIG. 3 is a block diagram illustrating a configuration of a printing unit according to an embodiment.

FIG. 4 is an explanatory diagram showing a part of a cross section of an image scanner unit according to an embodiment.

5 is a perspective view showing a part of the reference plate of FIG.

FIG. 6 is a plan view of the image sensor of FIG.

7 is an explanatory diagram showing a pixel array of one chip of the image sensor of FIG.

FIG. 8 is a plan view of three image sensors in one embodiment.

9 is a perspective view of the image sensor of FIG.

10 is a side view of the image sensor of FIG. 8 seen from the longitudinal direction.

11 is an explanatory diagram showing a pixel arrangement at an end portion of the image sensor of FIG.

FIG. 12 is an explanatory diagram showing blocks divided by three image sensors in one embodiment.

13 is a block diagram of a CPU (1) circuit of FIG.

FIG. 14 is a block diagram of the analog circuit of FIG.

15 is a block diagram of the video (1) circuit of FIG.

16 is an explanatory diagram showing an output image data string of the CCD gap correction unit in FIG.

17 is an explanatory diagram showing an output image data string of the RGB separation unit in FIG.

FIG. 18 is a block diagram of the video (2) circuit of FIG. 2.

19 is an explanatory diagram showing blocks divided by a data block division unit of FIG. 18. FIG.

20 is a block diagram showing a configuration example of a data block division unit in FIG. 18.

FIG. 21 is a timing chart showing the operation of the data block division unit in FIG.

22 is an explanatory diagram showing input image data and output data of the data block division unit of FIG. 20. FIG.

FIG. 23 is a block diagram of the color circuit of FIG.

FIG. 24 is a block diagram of the AR circuit of FIG.

FIG. 25 is a block diagram showing a configuration example of a ghost cancel unit in FIG. 23.

FIG. 26 is an explanatory diagram showing five pixels and a ghost pattern to be compared in the ghost cancel unit of FIG. 25.

27 is a block diagram illustrating a configuration example of a connection correction unit that performs connection correction of marker breaks in the marker flag generation unit of FIG. 24.

FIG. 28 is an explanatory diagram for explaining the operation of the connection correction unit in FIG. 27.

FIG. 29 is an explanatory diagram for explaining the operation of the connection correction unit in FIG. 27.

FIG. 30 is a block diagram of the DF circuit of FIG.

FIG. 31 is a block diagram showing the digital filter of FIG. 30.

32 is an explanatory diagram showing the order of operations in the digital filter in FIG. 31. FIG.

FIG. 33 is an explanatory diagram for explaining a calculation process in the digital filter in FIG. 31.

FIG. 34 is a block diagram of the HTP circuit of FIG.

FIG. 35 is an explanatory diagram showing an input data string of the block-line parallel conversion unit in FIG. 34.

FIG. 36 is an explanatory diagram showing an output data string of the block-line parallel conversion unit in FIG. 34.

FIG. 37 is a block diagram of the EDIT circuit of FIG. 2.

38 is an explanatory diagram showing a method of designating a rectangular area to be processed by the EDIT circuit of FIG. 37. FIG.

39 is an explanatory diagram showing another example of the method of designating the rectangular area to be processed in the EDIT circuit of FIG. 37. FIG.

FIG. 40 is an explanatory diagram for explaining mirror editing in the mirror editing unit of FIG. 37.

FIG. 41 is an explanatory diagram showing an outline of an optical system in another example of the present invention.

[Explanation of symbols]

25 ... Data block dividing unit, 42 ... Ghost canceling unit, 61 ... Marker flag generating unit, 72 ... Digital filter, 220 ... Image scanner unit, 308 ... Image sensor

Claims (8)

[Claims] 1. The image data for one line is divided into two adjacent image data.
A dividing unit that divides image data in the vicinity of the boundary of one block into a plurality of blocks so that each block has the same, and image processing that performs image processing independently and in parallel for each block divided by this dividing unit. An image processing apparatus comprising: 2. The dividing means divides the image information of one line area of the document into predetermined areas and reads the image information, and simultaneously reads the image information in the vicinity of the boundary of each area, and the image of each block is read. The image processing apparatus according to claim 1, further comprising a plurality of image sensors for outputting as data. 3. The dividing means captures image data of a predetermined area of the input image data, simultaneously captures image data in the vicinity of the boundary of each area, and outputs the image data as image data of each block. The image processing apparatus according to claim 1, further comprising a data input / output unit. 4. The data input / output unit includes a memory that stores image data of a predetermined area of the input image data and image data near a boundary of the area, and outputs the stored data. The image processing apparatus according to claim 3. 5. The image processing apparatus according to claim 1, wherein the image processing means performs image processing on a target pixel using image data of a plurality of pixels around the target pixel. 6. The image processing apparatus according to claim 5, wherein the image processing means includes a correction means for correcting the color information of the pixel of interest based on image data of a plurality of pixels around the pixel. 7. The image processing means, when identifying a portion where pixels having a specific feature are connected, identifies a portion where the pixel connection is interrupted based on image data of a plurality of adjacent pixels. The image processing apparatus according to claim 5, further comprising a connection correction unit that performs supplementary correction. 8. The image processing apparatus according to claim 5, wherein the image processing means includes a filter processing means for performing an operation using image data of a plurality of pixels around a target pixel.