JPH0646306A - Video signal processing circuit - Google Patents

Abstract

PURPOSE:To realize an electronic zoom even if a circuit scale is small. CONSTITUTION:The output of a CCD 1 is inputted in an IC for blurring correction 3 after an A/D conversion is performed for the output. Noise is eliminated by a noise reducer composed of a noise reduction circuit 31 and a field memory F in the IC for camera shake correction 3. In accordance with a zoom magnification, a memory control circuit 33 controls the reading of the field memory F and controls the interpolation factor of an interpolation circuit 501. Further, by the moving vector specified based on the output of a moving vector detection circuit 32, the reading start location image from the field memory F is controlled and camera shake is corrected.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video signal processing circuit suitable for use in a video camera having an electronic zoom function.

[0002]

2. Description of the Related Art Conventionally, a video camera having an electronic zoom function is a National Technical Report Vol.37 No.3 Jun.199.
1 As shown in P48 to P54, the IC having the control circuit for controlling the reading and writing of the field memory and the IC performing the interpolation processing for the electronic zoom were separate.

By the way, when electronic zooming is performed, the same data is read from the field memory in duplicate depending on the zoom magnification, so that the color order is different from the CCD output.

Therefore, there is a drawback that a control circuit for creating an interpolation coefficient according to the color order is required in the IC for interpolation processing, and the circuit scale becomes large.

[0005]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned points, and it is not necessary to provide control means for generating an interpolation coefficient of an interpolation circuit in an IC for interpolation processing in this IC. Provided is a video signal processing circuit capable of realizing electronic zoom even if the scale is small.

[0006]

SUMMARY OF THE INVENTION The present invention is based on the imaging output A
A video signal processing circuit including a memory that stores at least one field of D conversion output, a memory control circuit that controls reading of the memory according to the zoom magnification, and an interpolation circuit that interpolates the memory output according to the zoom magnification. In the video signal processing circuit, the memory control circuit controls the memory, creates an interpolation coefficient according to the zoom magnification, and supplies the interpolation coefficient to the interpolation circuit.

[0007]

The memory control circuit of the present invention controls the reading of the memory according to the zoom magnification, creates the interpolation coefficient, and supplies the interpolation coefficient to the interpolation circuit.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a schematic block diagram of a video signal processing circuit of a video camera according to this embodiment. In the figure, 1 is C in which a predetermined mosaic color filter is arranged on the image pickup surface.
A CD (solid-state image sensor) 2 is an A / D converter that converts this CCD output into a 10-bit digital signal.

Reference numeral 3 denotes an image stabilization IC, which is roughly divided into a noise reduce circuit 31, a motion vector detection circuit 32, and a memory control circuit 33. The noise reduce circuit 31 removes noise having no correlation in the time axis direction from the output of the A / D converter 2, and constitutes a cyclic noise reducer as shown in FIG. 2 together with the field memory F outside the IC. The coefficient K of the multiplier of the noise reduce circuit 31 is controlled in the range of 0 <K <1 according to the amount of movement of the image detected by the first microcomputer described later.

Reference numeral 34 is a compression circuit for compressing the output of the 10-bit noise reduce circuit 31 into 8-bit data and supplying it to the 8-bit field memory F. Reference numeral 35 is 10-bit data of 8-bit read from the field memory F. The decompression circuit decompresses the bit and supplies it to the noise reduce circuit 31. The field memory F is originally used for electronic zoom and camera shake correction as described later.

However, when the electronic zoom and camera shake correction functions are operating, the noise reduce circuit 3
Since the data correlation between the input of 1 and the output of the field memory F is lost, it is necessary to stop the operation of the noise reducer. Therefore, in this embodiment, the noise reduce circuit 3
A selector 37 for selecting and outputting one output and the output of the expansion circuit 35 is provided, and the expansion circuit output is selected and the coefficient K of the noise reduce circuit is set to 1 during the electronic zoom or camera shake correction operation. Control to stop the operation of the circuit.

On the other hand, a part of the output of the A / D converter 2 is input to the motion vector detection circuit 32. The motion vector detection circuit 32 detects a motion vector for every four detection blocks by the well-known representative point matching method, and supplies it to the first microcomputer 4. The first microcomputer 4 specifies one motion vector from the motion vectors for each detection block.

At the time of camera shake correction, electronic zoom is performed at a predetermined zoom magnification (1.2 times), and the read start position from the field memory F is controlled according to this motion vector to cut out the image. To control camera shake.

Next, the memory control circuit 33 will be described.

The memory control circuit 33 controls writing in the field memory F according to the write start address from the first microcomputer 4. When reading, the read start address is controlled according to the motion vector and / or the zoom magnification (1 to 4 times), and a read pulse corresponding to the zoom magnification is generated to control the duplicate reading of the same data.

Further, the memory control circuit 33 calculates an interpolation coefficient to be supplied to an interpolation circuit described later according to the zoom magnification. That is, the memory control circuit 33 controls the writing and reading of the field memory F and controls the interpolation circuit to perform zoom control.

Further, during zooming, the color order of the signals from the field memory F is different from the CCD output. Since the YC separation circuit described later does not operate in this state, the memory control circuit 33 creates a color order identification signal indicating the color order based on the read pulse and supplies it to the YC separation circuit.

Next, 36 is a synchronizing signal generating circuit which generates horizontal and vertical synchronizing signals based on the clock and start pulse and supplies them to the motion vector detecting circuit 32 and the memory control circuit 33.

Reference numeral 5 is a digital signal processing IC for digitally processing the output of the image stabilization IC 3.

Reference numeral 501 denotes an interpolation circuit to which the output of the noise reduce circuit 31 is supplied, which performs data interpolation in the horizontal and vertical directions according to the interpolation coefficient corresponding to the zoom magnification, and two color signals and a luminance signal Y. Further, horizontal and vertical aperture signals AP which are contour correction signals are generated.

The two color signals are Y / C separation circuit 502.
Is supplied to the RGB matrix circuit 503 and is separated into the color signals Cr and Cb and the low-frequency luminance signal YL.
It is a B color signal. This RGB color signal is sent to the γ correction circuit 50.
.Gamma.-correction is performed in step 4, and then the color difference matrix circuit 505 performs R-
It is converted into Y and BY color difference signals. Further, this color difference signal is processed by the color signal processing circuit 506, modulated into an NTSC color signal, and output.

On the other hand, the luminance signal Y of the output of the interpolation circuit
Is added with the aperture signal AP by the aperture adding circuit 507 and is then γ corrected by the γ correction circuit 508. Further, this luminance signal is processed by the luminance signal processing circuit 509,
The sync addition circuit 510 adds a sync signal based on the output of the sync signal generation circuit 36 and outputs the sync signal.

The output of the color signal processing circuit 506 and the output of the synchronization adding circuit 510 are the D / A converter 7 and the output, respectively.
At 8, it is converted into an analog color signal and a luminance signal.

Regarding each block of the above-mentioned signal processing circuit, Japanese Patent Application No. 3-150 previously filed by the applicant of the present application.
Since it is described in detail in No. 365, detailed description is omitted.

Next, AF (autofocus) and AE
(Auto iris) and AWB (auto white balance) will be described.

One of the luminance outputs from the interpolation circuit 501 before the addition of the aperture signal is supplied to the AF integration circuit 512 after the high frequency component of the luminance signal is extracted by the HPF 511. The AF integration circuit 512 digitally integrates in a field cycle for each integration area obtained by dividing the imaging area into a plurality of areas. Then, the integrated value is subjected to predetermined arithmetic processing by the second microcomputer 6 which can communicate with the first microcomputer 4, and is supplied to a focus motor (not shown) as an AF control output.

Further, the luminance output from the interpolation circuit 501 is further integrated by the AE integrator circuit 514 after the low frequency component of the luminance signal is further extracted by the LPF 513. And
This integrated value is subjected to predetermined arithmetic processing by the second microcomputer 6 and supplied as an AE control output to an iris motor (not shown).

Further, either the RGB signal from the RGB matrix circuit 503 or the color difference signal (RG, BG) from the color difference matrix circuit 505 is selected by the selector 515, and the LPF 516 selects the low range of the color signal. After the components are extracted, they are similarly digitally integrated by the AWB integrating circuit 517. Then, the integrated value is subjected to predetermined arithmetic processing by the second microcomputer 6 and supplied to the RGB matrix circuit 503 as an AWB control output.
The coefficients of the R, G, and B coefficient circuits provided in this circuit are controlled.

The reason why the color difference signals used for the AWB control are RG and BG instead of RY and BY are that the coefficient control can be easily performed.

As described above, since AF, AE, and AWB are detected using the output after camera shake correction, the integrated result does not fluctuate due to camera shake and can be accurately controlled.

Further, since AF and AE are detected using the luminance signal before γ correction and before the addition of the aperture, that is, before the non-linear processing, accurate detection can be performed.

It should be noted that the selector 515 can select either one by setting the second microcomputer 6.

Furthermore, the RGB signals are selected so that the same color signal can be obtained for each field before being selected by the selector 515, and the same color signal is integrated for one field period by the integrating circuit in the subsequent stage. It is made possible.
Similarly, the color difference signals are selected so that the same signal can be obtained for each field.

Reference numeral 518 denotes a timing control circuit which receives the 14 MHz master clock from the clock generation circuit 9 and can generate four kinds of sampling clocks each having a phase difference of 90 degrees, and controls the AD conversion circuit 2. The timing control circuit is switched by an external control signal so that a suitable one can be selected from four types of sampling clocks according to the characteristics of the AGC circuit (not shown) in the preceding stage of the AD conversion circuit.

Next, another embodiment of the digital signal processing IC will be described with reference to FIG.

In the present embodiment, 519 is a low chroma chroma suppressing circuit for suppressing the low chroma part of the output of the color difference matrix circuit 505 according to preference, and outputs the simultaneous color difference signals RY and BY. . This color difference signal is sequentially converted into a signal by the selector 520. That is, by controlling the selector 520 for each dot, a dot-sequential color difference signal can be obtained by controlling the dot-sequential operation and by controlling the line-sequential color difference signal. The output of the selector 520 is led to the color signal input / output terminal of the IC 5 via the selector 522 selected on the output side.

On the other hand, when inputting an external digital color signal, the selector 522 is switched to the input side in conjunction with the selector 525 for switching the input / output of the luminance signal, which will be described later.
The color signal input / output terminal is connected to the selector 521.
With this configuration, the input / output terminal of the IC 5 can be used also.

The selector 521 is controlled so as to switch every dot when the input digital color signal is dot-sequential, and every line when the input digital color signal is line-sequential, and is further synchronized by a synchronizing circuit (not shown) to obtain a color difference signal B. -Y and RY are obtained. This color difference signal is supplied to the selectors 523 and 524, respectively, together with the output of the low chroma chroma suppression circuit 519, and one of them is selected by the input / output control signal and supplied to the color signal processing circuit 506. Therefore, by this switching, video composition of the internal signal and the external signal can be realized.

The RGB output from the RGB matrix circuit 503, the aperture output from the interpolation circuit 501, and the sequential R-from the low chroma chroma suppression circuit 519.
The Y, BY color difference signals can be selected as a monitor output by the selector 526. Then, the output of the selector 526, the luminance output from the synchronization adding circuit 510 and the external digital luminance input from the selector 525 are selected by the selector 527 and supplied to the DA conversion circuit 8.

[0041]

As described above, according to the present invention, since the memory control circuit controls the memory and creates and outputs the interpolation coefficient to be supplied to the interpolation circuit, it is not necessary to provide a separate control circuit in the interpolation processing IC. The electronic zoom can be realized even if the circuit scale is small.

[Brief description of drawings]

FIG. 1 is a block diagram of a video signal processing circuit of a video camera according to an embodiment of the present invention.

FIG. 2 is a block diagram showing another embodiment of a digital signal processing IC.

[Explanation of symbols]

 3 IC for image stabilization 32 motion vector detection circuit 33 memory control circuit F field memory 5 IC for digital signal processing 501 interpolation circuit

[Procedure amendment]

[Submission date] July 3, 1992

[Procedure Amendment 1]

[Document name to be amended] Statement

[Correction target item name] 0010

[Correction method] Change

[Correction content]

Reference numeral 3 denotes an image stabilization IC, which is roughly classified into a noise reduce circuit 31 and a motion vector detection circuit 32.
And a memory control circuit 33. The noise reduce circuit 31 removes noise having no correlation in the time axis direction from the output of the A / D converter 2, and constitutes a cyclic noise reducer together with the field memory F outside the IC.

[Procedure Amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0035

[Correction method] Change

[Correction content]

The AD conversion circuit 2 has a frequency of 14 MHz.
Is controlled by a timing control circuit (not shown) capable of receiving four master clocks and generating four types of sampling clocks each having a phase difference of 90 degrees. Then, this timing control circuit uses
It is switched by a control signal from the outside so that a suitable one can be selected from four types of sampling clocks according to the characteristics of the C circuit (not shown).

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Toshiyuki Okino 2-18 Keihan Hondori, Moriguchi City, Osaka Sanyo Electric Co., Ltd. (72) Inventor Toshiya Iinuma 2-18 Keihan Hondori, Moriguchi City, Osaka Sanyo Denki Incorporated (72) Inventor Masao Takuma 2-18 Keihanhondori, Moriguchi-shi, Osaka Sanyo Electric Co., Ltd. (72) Inventor Akio Kobayashi 2-18-2 Keihanhondori, Moriguchi-shi, Osaka Sanyo Electric Co., Ltd. ( 72) Inventor Seiji Kawakami 2-18 Keihan Hondori, Moriguchi City, Osaka Sanyo Electric Co., Ltd.

Claims (1)

[Claims] 1. At least one AD conversion output of imaging output
A video signal processing circuit comprising: a memory for storing a field; a memory control circuit for controlling reading of the memory according to a zoom magnification; and an interpolation circuit for interpolating the memory output according to the zoom magnification. Is a video signal processing circuit, which controls the memory, creates an interpolation coefficient according to the zoom magnification, and supplies the interpolation coefficient to the interpolation circuit.